BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an example of the configuration of the principle part of an image processing apparatus according to one embodiment of the present invention;
FIG. 2 depicts an example of an error diffusion process table used for an error diffusion process according to the present invention;
FIG. 3 is a circuit diagram of an example of the detailed configuration of an error diffusion process portion according to the present invention;
FIG. 4 is a circuit diagram of an example of the detailed configuration of a diffusion error calculating portion shown in FIG. 3;
FIG. 5 depicts an example of a diffusion error calculation condition;
FIG. 6 is a circuit diagram of an example of the detailed configuration of a latch/adder shown in FIG. 3;
FIG. 7 is an explanatory flowchart of an example of an error diffusion processing method according to the present invention;
FIG. 8 is an explanatory flowchart of another example of the error diffusion processing method according to the present invention;
FIG. 9 depicts an example of tone values of an original image that is before undergoing an error diffusion process in binarization;
FIG. 10 depicts an example of the error diffusion process table used for the error diffusion process;
FIG. 11 depicts a result of calculation of diffusion errors at the first noted pixel in the original image in a case of the use of the error diffusion process table;
FIG. 12 depicts tone values that results after the diffusion errors are scattered in the original image;
FIG. 13 an explanatory view of a trouble occurring at the boundary between bands; and
FIG. 14 is an explanatory flowchart of a conventional error diffusion processing method.