BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic for explaining electrical connection in an image processing apparatus according to a first embodiment of the present invention;
FIG. 2 is a functional block diagram of the image processing apparatus that performs a layout analyzing process implemented by a CPU shown in FIG. 1;
FIG. 3 is a schematic flowchart of the layout analyzing process;
FIG. 4 is a schematic flowchart of an image-feature-amount calculating process performed by an image-feature-amount calculating unit shown in FIG. 2;
FIG. 5 is a schematic flowchart of a block classifying process;
FIG. 6 is a schematic for explaining a multiresolution process;
FIG. 7 is examples of mask patterns for calculating a higher-order autocorrelation function;
FIGS. 8A to 8F are schematics of examples of block classification;
FIG. 9 is a flowchart of an example of region-extraction-method selection based on image types;
FIG. 10 is a schematic for explaining a basic approach of the layout analyzing process based on a top-down-type region extraction method;
FIGS. 11A and 11B are schematics for explaining a result of region extraction for an image of FIG. 8B;
FIG. 12 is an external perspective view of a digital multifunction product (MFP) according to a second embodiment of the present invention; and
FIG. 13 is a schematic of a server-client system according to a third embodiment of the present invention.