BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating the functional structure of a known image processing apparatus;
FIG. 2 illustrates a frame on which image processing is to be carried out;
FIG. 3 illustrates a frame on which image processing is to be carried out;
FIG. 4 illustrates an example of the processing results of known one-dimensional image processing carried out on the frame illustrated in FIG. 3 in the horizontal direction;
FIG. 5 illustrates an example of the processing results of known one-dimensional image processing carried out on the frame illustrated in FIG. 3 in the vertical direction;
FIG. 6 illustrates an example of the processing results of one-dimensional image processing according to an embodiment of the present invention carried out on the frame illustrated in FIG. 3 in a diagonal direction;
FIG. 7 illustrates an image processing method according to an embodiment of the present invention;
FIG. 8 is a block diagram illustrating the functional structure of an image processing apparatus according to an embodiment of the present invention;
FIG. 9 is a flowchart illustrating a correction process carried out by the image processing apparatus illustrated in FIG. 8;
FIG. 10 is a block diagram illustrating the functional structure of an image processing apparatus according to another embodiment of the present invention;
FIG. 11 is a block diagram illustrating the functional structure of an image processing apparatus according to another embodiment of the present invention;
FIG. 12 is a block diagram illustrating the details of the functional structure of an overall correction unit of the image processing illustrated in FIG. 11;
FIG. 13 is a block diagram illustrating the functional structure of an image processing apparatus according to another embodiment of the present invention;
FIG. 14 is a block diagram illustrating the total or partial hardware structure of an image processing apparatus according to another embodiment of the present invention;
FIG. 15 is a block diagram illustrating the total or partial hardware structure of an image processing apparatus according to another embodiment of the present invention;
FIG. 16 is a block diagram illustrating the detailed functional structure of a VLPF unit of the image processing apparatus illustrated in FIG. 15;
FIG. 17 illustrates the characteristic of a function held by a gain determining unit illustrated in FIG. 16; and
FIG. 18 is a block diagram illustrating the total or partial hardware structure of an image processing apparatus according to another embodiment of the present invention.