This application relates to and claims priority rights from Japanese Patent Application No. 2021-196443, filed on Dec. 2, 2021, the entire disclosures of which are hereby incorporated by reference herein.
The present disclosure relates to an image processing apparatus.
An image processing apparatus performs a shrinking process of an image using a line buffer.
For example, when shrinking an image by half in both vertical and horizontal directions, one pixel of output is sampled per two-by-two pixels of input. In such a case, as shown in
For example, as shown in
An image processing apparatus according to an aspect of the present disclosure includes a line buffer, an input circuit, and an output circuit. The input circuit is configured to write image data into the line buffer. The output circuit is configured to read pixel data of a pixel to be sampled among the pixel data, the pixel specified correspondingly to a shrinking ratio. Further, with a throughput obtained by multiplying a throughput of the output circuit by a square of an inverse number of the shrinking ratio, the input circuit skips another pixel than the pixel to be sampled among the pixel data of an input block of a predetermined size that extends over lines of an inverse number of the shrinking ratio, and writes pixel data of the pixel to be sampled into the line buffer. Upon writing pixel data of an adjacent input block of the input block in a secondary scanning direction into the line buffer, the output circuit reads from the line buffer the pixel data of the pixel to be sampled and continuously outputs the pixel data.
These and other objects, features and advantages of the present disclosure will become more apparent upon reading of the following detailed description along with the accompanied drawings.
Hereinafter, an embodiment according to an aspect of the present disclosure will be explained with reference to drawings.
The image processing apparatus shown in
The input circuit 2 writes pixel data into the line buffer 1. Specifically, as shown in
The pixel to be sampled is specified correspondingly to a shrinking ratio, the output circuit 3 reads pixel data of the specified pixel among the pixel data. Specifically, as shown in
Further, in this embodiment, as shown in
Further, the controller 4 selectively specifies one of an actual size operation and a shrinking operation to the input circuit 2 and the output circuit 3. The input circuit 2 (a) in the actual size operation, writes the pixel data of the input block into the line buffer without skipping a pixel, and (b) in the shrinking operation, skips another pixel than the pixel to be sampled among the pixel data of an input block of a predetermined size that extends over lines of an inverse number of the shrinking ratio, and writes pixel data of the pixel to be sampled into the line buffer 1. The output circuit 3 continuously reads the image data of the pixels to be sampled both in the actual size operation and in the shrinking operation.
It should be noted that the controller 4 may perform a hardware process to control the input circuit 2 and the output circuit 3, or may perform a software process to control the input circuit 2 and the output circuit 3.
The following part explains a behavior of the aforementioned image processing apparatus.
The controller 4 specifies the shrinking operation to the input circuit 2 and the output circuit 3 if a shrunk image is required in a subsequent processing unit, and specifies the actual size operation to the input circuit 2 and the output circuit 3 if the line buffer 1 is used but a shrunk image is not required in a subsequent processing unit (e.g. line delay, a window-referring image process such as a filter process without image shrinking).
In a case shown in
Subsequently to a last input block in the primary scanning direction, a top input block in the primary scanning direction is read of two lines adjacent in the secondary scanning direction.
In this embodiment, pixel data of the input image block is stored in a predetermined memory area of the aforementioned SRAM, and is read from the memory area and written into the aforementioned memory area of the line buffer 1. Specifically, as shown in
In this case, every 8 cycles of the clock, the output circuit 3 reads the image data of 8 by 2 pixels (for two words) into the line buffer 1 in synchronization with the input circuit 2, and continuously outputs the output block of 1 by 2 pixels per cycle of the clock.
Consequently, the pixel data is continuously outputted even in the shrinking operation as shown in
As mentioned, in the aforementioned embodiment, with a throughput obtained by multiplying a throughput of the output circuit 3 by a square of an inverse number of the shrinking ratio, the input circuit 2 skips another pixel than the pixel to be sampled among the pixel data of an input block of a predetermined size that extends over lines of an inverse number of the shrinking ratio, and writes pixel data of the pixel to be sampled into the line buffer 1; and upon writing pixel data of an adjacent input block of the input block in a secondary scanning direction into the line buffer 1, the output circuit 3 reads from the line buffer 1 the pixel data of the pixel to be sampled and continuously outputs the pixel data.
Consequently, the image shrinking is performed as a hardware process without suspension of line output.
It should be understood that various changes and modifications to the embodiments described herein will be apparent to those skilled in the art. Such changes and modifications may be made without departing from the spirit and scope of the present subject matter and without diminishing its intended advantages. It is therefore intended that such changes and modifications be covered by the appended claims.
For example, in the aforementioned embodiment, the shrinking ratio is set as half. Alternatively, the shrinking ratio may be set as another value (i.e. quarter).
Further, in the aforementioned embodiment, the number of pixels of pixel data stored in one word of the line buffer is not limited to that as mentioned.
Number | Date | Country | Kind |
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2021-196443 | Dec 2021 | JP | national |