Claims
- 1. An image processing comprising:a plurality of processors; a bus for connecting said processors; a bus controlling unit which performs adjustment for said bus; and a memory which is accessed via said bus controlling unit, wherein at least one of said plurality of processors includes a portion which limits the bit range in said bus when using said bus and said bus control unit includes a control function which permits simultaneous access to said memory from said plurality of processor, and wherein said memory includes a plurality of modules, and in the connections between said memory and said processors all of the address lines are wired in common, all of the data lines are wired separately and at least one control line is wired separately.
- 2. An image processing system according to claim 1, wherein at least two modules in said plurality of modules include a portion which sets different row addresses.
- 3. An image processing system according to claim 1, wherein at least two modules in said plurality of modules include a portion which sets different row addresses and said portion further includes a subportion which negates a chip enable signal for at least one module at the timing of issuing a row address.
- 4. An image processing system according to claim 1, wherein said bus use bit range limiting portion is realized by at least one processor which sets the use bit ranges for the respective processors via software.
- 5. An image processing system according to claim 1, wherein start and stop commands for at least one processor are performed via register access from another processor.
- 6. An image processing system according to claim 1, wherein the processing capacity of at least one processor exceeds 100 MIPS.
- 7. An image processing system according to claim 1, wherein at least one processor is a RISC type.
- 8. An image processing system according to claim 1, wherein said memory is a synchronous DRAM.
Priority Claims (3)
Number |
Date |
Country |
Kind |
6-157183 |
Jul 1994 |
JP |
|
6-210923 |
Sep 1994 |
JP |
|
6-224740 |
Sep 1994 |
JP |
|
Parent Case Info
This is a continuation of application Ser. No. 08/956,113, filed Oct. 24, 1997 now U.S. Pat. No. 6,084,599; which is a divisional application of Ser. No. 08/498,055, filed Jul. 5, 1995 now U.S. Pat. No. 5,748,202.
US Referenced Citations (22)
Foreign Referenced Citations (3)
Number |
Date |
Country |
61261969 |
Nov 1986 |
JP |
5120114 |
May 1993 |
JP |
5258040 |
Oct 1993 |
JP |
Non-Patent Literature Citations (2)
Entry |
A. Goris et al, A Configurable Pixel Cache for Fast Image Generation, IEEE CCC & F, Mar. 1987, pp. 24-32. |
J. Foley et al, “Fundamentals of Interactive Computer Graphics” translated by Atsumi Imamiya, Published by Japan Computer Association, 1982, pp. 569-572. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
08/956113 |
Oct 1997 |
US |
Child |
09/482642 |
|
US |