BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram depicting the image processor according to an embodiment of the present invention;
FIG. 2 is a block diagram depicting the line segment extraction section in FIG. 1;
FIG. 3 shows an example of a captured image in FIG. 1 and FIG. 2;
FIG. 4 shows an example of an image after log filter processing in FIG. 3;
FIG. 5 shows an example of area selection from the image in FIG. 4;
FIG. 6 shows an example of an image after the morphology processing in FIG. 4;
FIG. 7 shows an example of an image after the extraction target selection processing in FIG. 6;
FIG. 8 shows an example of an image after log filter processing in FIG. 7;
FIG. 9 shows an example of an image after the binary processing in FIG. 8;
FIG. 10 is diagram depicting the log filter processing in FIG. 2;
FIG. 11 is a flow chart depicting the area selection processing and top hat summation processing in FIG. 2;
FIG. 12 is a diagram depicting the area selection processing in FIG. 11;
FIG. 13 is a diagram depicting the opening processing in FIG. 11;
FIG. 14 is diagram depicting the area selection processing and top hat summation processing in FIG. 11;
FIG. 15 is a diagram depicting the top hat summation processing in FIG. 11;
FIG. 16 is a flow chart depicting the extraction area selection processing in FIG. 2;
FIG. 17 is a diagram depicting the area specification processing in FIG. 16;
FIG. 18 is a diagram depicting the histogram creation and mask area and marker area detection processing in FIG. 16;
FIG. 19 area diagrams depicting the reconstruction processing in FIG. 16;
FIG. 20 area diagrams depicting the log filter processing in FIG. 2; and
FIG. 21 is diagram depicting the line segment extraction operation by the log filter processing in FIG. 20.
Patent Application
20070177825
