Image quality improvement for liquid crystal displays

Abstract

A liquid crystal display (LCD) system, comprising a matrix of pixels, analyzes a video data stream for grayscale level jumps from extreme black to moderate gray levels. Transitions in grayscale levels are restricted between adjacent pixels so as to reduce image degradation due to fringe field effects. A memory, such as a plurality of shift registers, may be used to store grayscale levels of adjacent pixels which are compared and if a ratio between these grayscale levels exceeds a desire value then at least one of the grayscale levels is modified.

Description

FIELD OF THE INVENTION

The present invention relates generally to liquid crystal display (LCD) devices, and more particularly to a system, apparatus and method for improving image quality by limiting the difference between gray scale values of adjacent pixels.

BACKGROUND OF THE INVENTION TECHNOLOGY

Liquid crystal displays (LCDs) are commonly used in devices such as portable televisions, portable computers, control displays, and cellular phones to display information to a user. LCDs act in effect as a light valve, i.e., they allow transmission of light in one state, block the transmission of light in a second state, and some include several intermediate stages for partial transmission. When used as a high resolution information display, as in one application of the present invention, LCDs are typically arranged in a matrix configuration with independently controlled display areas called “pixels” (the smallest segment of the display). Each individual pixel is adapted to selectively transmit or block light from a backlight (transmission mode), from a reflector (reflective mode), or from a combination of the two (transflective mode).

A LCD pixel can control the transference for different wavelengths of light. For example, an LCD can have pixels that control the amount of transmission of red, green, and blue light independently. In some LCDs, voltages are applied to different portions of a pixel to control light passing through several portions of dyed glass. In other LCDs, different colors are projected onto the area of the pixel sequentially in time. If the voltage is also changed sequentially in time, different intensities of different colors of light result. By quickly changing the wavelength of light to which the pixel is exposed an observer will see the combination of colors rather than sequential discrete colors. Several monochrome LCDs can also result in a color display. For example, a monochrome red LCD can project its image onto a screen. If a monochrome green and monochrome blue LCD are projected in alignment with the red, the combination will be a full range of colors.

The monochrome resolution of an LCD can be defined by the number of different levels of light transmission or reflection that each pixel can perform in response to a control signal. A second level is different from a first level when a user can tell the visual difference between the two. An LCD with greater monochrome resolution will look clearer to the user.

LCDs are actuated pixel-by-pixel, either one at a time or a plurality simultaneously. A voltage is applied to each pixel area by charging a capacitor formed in the pixel area. The liquid crystal responds to the charged voltage of the pixel capacitance by twisting and thereby transmitting a corresponding amount of light. In some LCDs an increase in the actuation voltage decreases transmission, while in others it increases transmission. When multiple colors are involved for each pixel, multiple voltages are applied to the pixel at different positions (different capacitance areas being charged of a pixel) or times depending upon the LCD illumination method. Each voltage controls the transmission of a particular color. For example, one pixel can be actuated for only blue light to be transmitted while another for green light, and a third for red light. A greater number of different light levels available for each color results in a much greater number of possible color combinations. Colors may be combined from a red pixel, a green pixel and a blue pixel, each residing on a different LCD, to produce any desired combined pixel color. The three LCDs (red-green-blue or RGB) are optically aligned so that the resulting light from each of the corresponding RGB pixels produces one sharp color pixel for each of the pixels in the LCD pixel matrix. The LCD pixel matrix is adapted for displaying one frame of video per light strobe. Each light strobe (RGB) produces one video frame. A sequence of video frames produces video images that may change over time (e.g., motion video).

Converting a complex digital signal that represents an image or video into voltages to be applied to charge the capacitance of each pixel of an LCD involves circuitry that can limit the monochrome resolution. The signals necessary to drive a single color of an LCD are both digital and analog. It is digital in that each pixel requires a separate selection signal, but it is analog in that an actual voltage is applied to charge the capacitance of the pixel in order to determine light transmission thereof.

Each pixel in the array of the LCD is addressed by both a column (vertical) driver and a row (horizontal) driver. The column driver turns on an analog switch that connects an analog voltage representative of the video input (control voltage necessary for the desired liquid crystal twist) to the column, and the row driver turns on a second analog switch that connects the column to the desired pixel.

The video inputs to the LCD are analog signals centered around a center reference voltage of typically from about 6.5 to 8.0 volts. A voltage equal or close to this center reference voltage is called “VCOM” and is supplied to the LCD Cover glass electrode which is a transparent conductive coating on the inside face (liquid crystal side) of the cover glass. This transparent conductive coating is typically Indium Tin Oxide (ITO).

One frame of video pixels are run at voltages above the center reference voltage (positive inversion) and for the next frame the video pixels are run at voltages below the center reference voltage (negative inversion). Alternating between positive and negative inversions results in substantially a zero net DC bias at each pixel. This substantially reduces the “image sticking” phenomena.

LCD technology has reduced the size of displays from full screen sizes to minidisplays less than 1.3 inches diagonal measurement, to microdisplays that require a magnification system. Microdisplays may be manufactured using semiconductor integrated circuit (IC) dynamic random access memory (DRAM) process technologies. The microdisplays consist of a silicon substrate backplane, a cover glass and an intervening liquid crystal layer. The microdisplays are arranged as a matrix of pixels arranged in a plurality of rows and columns, wherein an intersection of a row and a column defines a position of a pixel in the matrix. To incident light, each pixel is a liquid crystal cell above a reflecting mirror. By changing the liquid crystal state, the incident light can be made to change its polarization. The silicon backplane is an array of pixels, typically 10 to 20 microns in pitch. Each pixel has a mirrored surface that occupies most of the pixel area. The mirrored surface is also an electrical conductor that forms a pixel capacitor with the ITO layer as the other plate of the pixel capacitor (common to all pixel capacitors in the matrix of pixels. As each pixel capacitor is charged to a certain pixel value, the liquid crystals between the plates of the pixel capacitors “twist” or “untwist” which affects the polarization of the light incident to the pixels (reflections from the pixel mirrors).

Microdisplays may have an analog video signal input (“analog display”) or a digital video signal input (digital display). Analog displays, generally, are addressed in a raster mode, while the pixels in a digital display may be addressed like a DRAM, in a random order. Random access allows updating only pixels requiring updating, thus saving on processing time and associated power consumption.

A problem exists in small LCDs, especially microdisplays, which have small pixel cell areas compared to the area of the gaps between the pixel cells. Fringe fields between the pixels are therefore significant in magnitude and the area affected by fringe fields is significant with respect to the overall pixel area. This leads to image degradation of increasing severity for small LCDs and high driving voltages. Limiting the driving voltages helps, but reduces the available contrast of the LCD.

SUMMARY OF THE INVENTION

The present invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing a system, method and apparatus for improving image quality of a liquid crystal display (LCD) by modifying the video source values written to the pixels in order to smooth the magnitude of voltage transitions from one adjacent pixel to another. If the voltage transitions between adjacent pixels is too large in magnitude, the large voltage transition can generate a strong fringe field effect between the adjacent pixels.

A liquid crystal on silicon (LCoS) microdisplay is adapted to receive video information from a digital video data source. The LCoS microdisplay may operate, e.g., in a normally white twisted nematic LC mode. A rubbing direction may be selected so that disclinations appear preferably at vertical pixel borders (between columns), e.g., a 60 degree twist self-compensated reflective twisted nematic mode. If a source image with black areas surrounded by light gray areas is displayed, a white line may be observed within a gray area that borders the black area on one side thereof, while on the other side of the black area a white spot may be observed therein. If the source video image for the pixels at the border of the gray/black areas are modified, e.g., a normally black pixel written more toward gray (lighter than black but darker than the normal gray), or a gray pixel written more toward black (darker), then the resulting LCD video image has significantly less image distortion due to fringe effect fields. Such a slight reduction in the blackness of a pixel or reduction of lightness of a pixel next to a black pixel has a strong effect in the applied voltage since the electro-optical response of the liquid crystal has a small gradient close to the saturation voltage for a black pixel.

For exemplary purposes in describing the embodiments disclosed herein, a pixel voltage value (the voltage value charge on the pixel capacitor) representing black may be referred to as black or level A (00 h input to an 8-bit DAC), and a pixel voltage value representing white may be referred to as white or level D (FF h input to the 8 bit DAC). Gray levels may be referred to as gray or level C (greater than black—00 h and less than white—FF h to the 8 bit DAC). 00 h is 0 in base 10 and FF h is 255 in base 10.

There is a liquid crystal (LC) defect called “disclination” on a border where deep black pixels meet brighter (lighter or whiter) pixels. Top and bottom borders generally are not affected, but left and right borders may emit a bright line. A grayshade of 60 (out of 255) at a border of grayshade 10 (out of 255) is hardly noticeable, however, a grayshade (gs) of 60 at a border of grayshade 0 is very noticeable. A solution, according to the present invention, is to display black as gs 0 when it detects a fairly large swath of black. For example, given a gray flatfield of gs 60 with a broad black (grayshade 0) line running vertically across it. If the black line were 20 columns wide, the first few columns may be written, for example but not limited to, gs 15, gs 11, gs 7, gs 4, gs 2, gs 1 and finally gs 0. When coming out of the 20 column wide swath, the last few columns may be written, for example but not limited to, gs 1, gs 2, gs 4, gs 7, gs 11 and gs 15. Simply halving, e.g., dividing by two, the pixel gs values accomplishes the intended purpose of the present invention. Other divide ratios may be effectively used and are contemplated here.

An additional feature of the invention controls at what point the adjacent pixel gs values are “softened” or rounded. A limit may be defined which is used to restrict the range of gs values being divided by two. For example, if the limit were set to zero, all gs values would pass through the video stream without change. Conversely, if the limit where set to 255, then the divide-by-two operation would occur under all circumstances, e.g., whenever adjacent pixel gs values vary by more than a factor of two. For example an adjacent pixel pair transformation may be represented as follows:

{left, right} {0, 255} : {128, 255}
{left, right} {255, 0} : {128, 0}

An intermediate limit, e.g., 64, would not affect pixel gs values greater than 64. For example:

	{left, right}	{75, 255}: {75, 255}	(unchanged)
	{left, right}	{247, 65} : {247, 65}	(unchanged)
	{left, right}	{61, 255} : {64, 255}
	{left, right}	{255, 53} : {255, 64}
	{left, right}	{0, 255} : {64, 255}
	{left, right}	{255, 0} : {255, 64}

In an exemplary embodiment of the invention, eight registers may be used in performing the “divide-by-two” operations on the pixel gs values. It is contemplated and within the scope of the present invention that more or less than eight registers may be used to perform the divide-by-two operations. One implementation of the “divide-by-2” algorithm may be as follows. Assign the input video pixel stream to 8 registers, A through G:

G→E→C→A :Aprm→Aprmdly

H→F→D→B :Bprm→Bprmdly

Where {Bprm, Aprm} are the transformed pixel values at the same time point as {B, A} The arrows indicate where the clock steps are. {Bprmdly, Aprmdly} is just the solution of the previous pixel input which is needed to help in the calculation of Aprm and Bprm. Aprm and Bprm can be solved mathematically by the following:

Amin=MAX{min(H/128), limit/64), min (G/64, limit/32), min(F/32, limit/16), min(E/16, limit/8), min(D/8, limit/4), min(C/4, limit/2), min(B/2, limit), min(Bprmdly/2, limit)}

then if A<Amin, Aprm=Amin; else Aprm=A

Bmin=MAX{min(H/64), limit/32), min (G/32, limit/16), min(F/16, limit/8), min(E/8, limit/4), min(D/4, limit/2), min(C/2, limit), min(Aprm/2, limit)}

then if B<Bmin, Bprm=Bmin; else Bprm=B

The above equations may be implemented with digital logic, e.g., FPGA, PLA, ASIC, microcontroller, microprocessor and the like using reduced terms as follows:

term0=maximum(trunc(H/4), trunc(G/2))

term1=minimum(trunc(term0/16), trunc(limit/16))

term2=minimum(trunc(term0dly/4), trunc(limit/4)) (where term0dly is delayed one clock)

term3=minimum(term0dlydly, limit)(where term0dlydly is delayed two clocks)

term4=minimum(trunc(Aprm/2), limit)

term5=minimum(trunc(B/2), limit)

term6=minimum(trunc(Bprmdly/2), limit)

Amin=maximum(trunc(term1/2), trunc(term 2/2), trunc(term 3/2), term 5, term6)(calculate this before Bprm)

Bmin =maximum(term1, term2, term3, term4)

If A<Amin, then Aprm=Amin; else Aprm=A

If B<Bmin, then Bprm=Bmin; else Bprm=B

In an alternate embodiment, the above equations may be modified slightly to remove the Bmin dependency on Aprm and use terms based on A and Bprm_dly in its stead as follows:

Bmin=MAX{min(H/64), limit/32), min (G/32, limit/16), min(F/16, limit/8), min(E/8, limit/4), min(D/4, limit/2), min(C/2, limit), min(A/2, limit), min(Bprmdly/4, limit/2)}

Table 1 hereinbelow depicts some test vectors to illustrate how an exemplary embodiment of the invention may function. The vectors are depicted in single file, e.g., H, G, F, E, D, C, B, A rather than two-pixels per clock: e.g., {H,G}, {F,E}, {D,C}, {B,A}.

	TABLE 1
	Limit
Output		7	15	30	15	7	3	2	5	10	20	100	20	10	5
Input	20	0	0	30	0	0	0	0	0	0	0	100	0	0	0
Output		1	2	3	4	5	6	5	4	3	2	1	0	1	2
input	8	1	2	3	4	5	6	5	4	3	2	1	0	1	2
output		255	127	63	31	15	7	8	16	32	64	128	255	160	80
input	255	255	0	0	1	2	4	8	16	32	64	128	255	160	80
output		64	32	64	32	64	127	255	127	255	127	255	127	255	127
input	255	64	0	64	0	64	0	255	0	255	0	255	0	255	0
output		64	3	64	3	64	3	255	3	255	3	255	3	255	3
input	3	64	0	64	0	64	0	255	0	255	0	255	0	255	0
output		64	10	64	10	64	10	255	10	255	10	255	10	255	10
input	10	64	0	64	0	64	0	255	0	255	0	255	0	255	0
output		64	247	205	189	64	64	145	95	81	64	227	80	53	106
input	64	29	247	205	189	17	3	145	95	81	42	227	80	30	106
output		29	247	205	189	20	20	145	95	81	42	227	80	30	106
input	20	29	247	205	189	17	3	145	95	81	42	227	80	30	106

For a sequential color LCD system, only one set of shift registers need be used. For a three color (red-green-blue) LCD system, three sets of shift registers may be used, one for each color portion of the RGB LCDs.

Adjacent pixels on the same row may be as described herein as well as adjacent pixels on adjacent rows. It is contemplated and within the scope of the present invention that a video memory may be utilized to store voltage values written to pixels on previous rows and/or columns so that no adjacent pixel has a voltage value difference great enough to cause field fringe effects.

The present invention is directed to a system for improving image quality of a liquid crystal display (LCD), said system comprising: a matrix of pixels arranged in a plurality of columns and a plurality of rows, wherein an intersection of a row and a column defines a location of a pixel in said matrix; at least one digital-to-analog converter (DAC) having a digital input and an analog output; a plurality of column switches adapted for coupling the analog output of said at least one DAC to each of said plurality of columns; a plurality of row switches adapted for selectively coupling each of said plurality of rows to said plurality of columns; column control logic for controlling said plurality of column switches; row control logic for controlling said plurality of row switches; a video frame to gray scale conversion and pixel address logic for converting video information into LCD gray scale values and corresponding pixel address locations thereof; and video data comparator/modifier logic, said video data comparator/modifier logic adapted to receive the LCD gray scale values for each pixel of the matrix of pixels, wherein gray scale values of adjacent pixels are compared and if a ratio of the gray scale values of adjacent pixels is greater than a desired value, then one of the gray scale values is modified so that the ratio of adjacent pixel gray scale values is no greater than the desired value; said video data comparator/modifier logic is adapted for sending all unmodified gray scale values and any modified gray scale values to said at least one DAC; said video frame to gray scale conversion and pixel address logic adapted for sending said pixel address locations to said column control logic and said row control logic.

The present invention is also directed to a method for improving image quality of a liquid crystal display (LCD) comprising a matrix of pixels arranged in a plurality of rows and columns, wherein an intersection of a row and a column defines a position of a pixel in the matrix, said method comprising the steps of: determining if a ratio of gray scale values of adjacent pixels is greater than a desired value, wherein; if the ratio is less than or equal to the desired value, then writing the gray scale values to the adjacent pixels, and if the ratio is greater than the desired value, then modifying one of the gray scale values of the adjacent pixels so that the ratio is less than or equal to the desired value, and then writing a gray scale value and the modified gray scale value to the adjacent pixels.

A technical advantage of the present invention is improved image quality in microdisplays. Another technical advantage is in smoothing transitions between pixel voltages that generate strong fringe field effects. Other technical advantages of the present disclosure will be readily apparent to one skilled in the art from the following figures, descriptions, and claims. Various embodiments of the invention obtain only a subset of the advantages set forth. No one advantage is critical to the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present disclosure and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic plan view of a portion of a liquid crystal display;

FIG. 2 is a schematic elevational view of a portion of the liquid crystal display of FIG. 1 ;

FIG. 3 is a schematic block diagram of a liquid crystal display system;

FIG. 4 is a schematic diagram of a portion of the liquid crystal display of FIG. 3 ;

FIG. 5 is a schematic block diagram of an exemplary embodiment of the invention;

FIG. 6 is a graph of pixel voltage levels verses pixel locations illustrating operation of prior art liquid crystal display systems;

FIG. 7 is a graph of pixel voltage levels verses pixel locations illustrating operation of a liquid crystal display system according to an exemplary embodiment of the invention; and

FIG. 8 is a schematic flow diagram of an exemplary embodiment of the invention.

While the present invention is susceptible to various modifications and alternative forms, specific exemplary embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

The present invention is directed to a liquid crystal display (LCD) comprising a matrix of liquid crystal pixels having light modifying properties controlled by voltage values stored in capacitors comprising the areas representing the pixels in the matrix of pixels of the LCD. A plurality of digital-to-analog converters (DACs) are coupled through analog switches to columns of the pixel matrix for voltage charging of the columns. Row analog switches connect each column to a desired respective pixel capacitor plate on a selected row, thereby transferring the voltage values on the columns to the respective pixel capacitors. The embodiments of the invention improve image quality of a liquid crystal display (LCD) by modifying the video voltage values written to the pixel capacitors in order to reduce the magnitude change of voltage transitions from one adjacent pixel area to another. If the voltage change transition between adjacent pixel areas is too large in magnitude, the voltage change transition can generate a strong fringe field effect between the adjacent pixel areas call “disclinations.”

Referring now to the drawings, the details of exemplary embodiments of the invention are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.

Referring to FIG. 1 , depicted is a schematic plan view of a portion of a liquid crystal display (LCD). The LCD is generally represented by the numeral 102 and comprises a plurality of pixels 108 (FIG. 3 ). Each pixel 108 has a respective pixel capacitor plate or “mirror” 84 . The pixels 108 are arranged in a matrix array. In an exemplary embodiment of the invention, pixel mirrors 84 are disposed on a silicon substrate 82 . A pixel mirror 84 forms one plate of a pixel capacitor, the other pixel capacitor plate is formed by the transparent ITO layer. The substrate 82 may be a semiconductor integrated circuit die having transistors fabricated therein and some of these transistors may be connected to the pixel mirrors 84 . Spaces 86 between the pixel mirrors 84 are very small and a voltage potential difference of large enough magnitude between adjacent pixel mirrors 84 may cause disclinations in the liquid crystal material.

Referring now to FIG. 2 , depicted is a schematic elevational view of a portion of the liquid crystal display of FIG. 1 . The LCD 102 comprises the substrate 82 on which the pixel mirrors 84 are transposed on a surface thereof. Liquid crystal material 88 surrounds the pixel mirrors 84 . A transparent cover 92 , e.g., glass or plastic, has on one side thereof a transparent electrically conductive coating 90 , e.g., Indium Tin Oxide (ITO), that forms the other capacitor plate for the pixel mirrors 84 . An outside face 94 of the cover 92 is the viewed portion of the LCD 102 . Typically, light 96 is flashed onto the outside face 94 of the LCD 102 , and the liquid crystal material 88 modifies light 98 that is reflected from the pixel mirrors 84 . Each pixel mirror 84 in combination with the ITO layer 90 has a unique voltage charge therebetween which modifies the twist of the liquid crystal material 88 that is within that voltage charge. The amount of twist of the liquid crystal material 88 determines how much light 96 is returned as the reflected light 98 (light polarization filters, not illustrated, are also utilized in combination with the liquid crystal modified light polarization). A sharp and clear video frame will have smooth and distinct light polarization transitions between the pixel mirrors 84 , however, when the voltage difference between adjacent pixel mirrors 84 is too large, disclinations may occur. The present invention overcomes these disclinations by limiting the magnitude of the voltage difference between the adjacent pixel mirrors 84 .

Referring to FIG. 3 , depicted is a schematic block diagram of a liquid crystal display system. A high-level block diagram of a system for writing voltage values to pixels of a liquid crystal display (LCD) system is generally represented by the numeral 100 . The voltage values being written to the pixels are representative of a frame of video data. The voltage values control the “twist” of the liquid crystal material at each pixel area so that when a light is flashed on or through the LCD, the light polarization and ultimately the intensity of the light passing through a polarization filter is controlled by the “twist” of the liquid crystal material at each pixel area of the LCD.

For illustrative and exemplary purposes, the LCD 100 depicted in FIG. 3 comprises a pixel matrix 102 of M rows 106 by N columns 104 for a total of M×N individually addressable pixels 108 . The combination of row control logic 110 and column control logic 112 are used to select each of the pixels 108 for writing thereto in the LCD 100 , as more filly described herein. Video to pixel translation logic and a look-up table (LUT) (hereinafter translation logic) 114 perform the necessary calculations and steps to translate a video frame image 116 into discrete digital values, each digital value representing a pixel video voltage value. The digital values are sent to digital-to-analog converters (DACs) 120 , 121 , 122 and 123 , and the pixel location addresses thereof are sent to the row and column control logic 110 and 112 .

It is contemplated and within the scope of the present invention that any number of DACs may be used according to exemplary embodiments of the present invention. The DACs 120 , 121 , 122 and 123 have outputs comprising analog values, e.g., voltage or current, corresponding to digital input words from the translation logic 114 .

Referring now to FIG. 4 , depicted is a schematic block diagram of a portion of the liquid crystal display system 100 of FIG. 3. A portion of the pixel matrix 102 is represented for illustrative and exemplary purposes as pixels 108 aa - 108 dd (4×4matrix), pixel row switches 300 through 333 and pixel column switches 290 through 293 . An LCD operates by placing a desired voltage charge at each pixel 108 aa - 108 dd of the LCD 100 . A voltage charge at a pixel 108 causes liquid crystals at that pixel area to change their “twist” orientation so that light passing through the LCD 100 or being reflected is thereby affected. The translation logic 114 uses the received video frame information 116 to create appropriate digital values that are sent to the DACs 120 - 123 which are representative of that portion of the video frame at each one of the pixel locations. In addition, the translation logic 114 associates an x-y coordinate (row-column) location for each of these pixel voltage values and sends same to the row control logic 110 and column control logic 112 .

The DACs 120 - 123 receive digital representations of video pixel values from the translation logic 114 and convert these digital representations to analog values, e.g., voltage or current, which must then be applied to each corresponding column 104 . Each of the pixels 108 aa - 108 dd has a capacitance 178 associated therewith, and each of the columns 0 , 1 , 2 (not illustrated) and 3 has a capacitance 180 , 181 , 182 (not illustrated) and 183 , respectively, associated therewith. The capacitance 178 of each pixel may not all be the same, nor may the capacitance 180 , 181 , 182 and 183 of each column be the same. However, a column capacitance, e.g., 180 is greater than a pixel capacitance, e.g., 178 . The column capacitance is charged to a desired voltage value. The output of the DAC is connected to the column and thereby charges the column capacitance to a desired analog voltage, each pixel in a selected row is connected to a corresponding column. Therefore, the voltage on the pixel will be substantially the same as the voltage on the corresponding column.

For example, a column(s) is charged to a certain voltage while a pixel row is selected so that the intersection(s) thereof is the desired pixel to be charged. For example, columns 0 - 3 are charged from the DACs 120 - 123 , respectively, when the column switches 290 - 293 are closed. The capacitance 178 of each of the pixels 108 aa - 108 dd are charged from the columns 0 - 3 , respectively, when the row switches 300 - 303 are closed. A plurality of DACs may be used to simultaneously charge the capacitance of a like number of columns, then a like number of switches in a row may be used to charge the capacitance of a like number of pixels from the respective charged columns. The column control logic 112 and row control logic 110 control operation of the column switches 290 - 293 and row switches 300 - 333 , respectively, for the group of pixels 108 aa - 108 dd . Other pixel groups 108 are controlled in a similar fashion.

Referring now to FIG. 5 , depicted is a schematic block diagram of an exemplary embodiment of the invention. The DACs 120 - 123 are adapted to receive digital amplitude information from a gray scale look up table 304 . The gray scale look up table 304 receives pixel grayscale information from the video data comparator/modifier logic 310 which compares gray scale values of adjacent pixels and may modify one or both values so as to keep the voltage magnitude change between pixel voltage values to within a desired limit. The video data comparator/modifier logic 310 receives pixel gray scale values 312 from the video frame to LCD pixel gray scale conversion and pixel address logic 302 . The video frame to LCD pixel gray scale conversion and pixel address logic 302 is adapted to convert video information 116 into corresponding pixel information (grayscale and pixel address information). Pixel address information is sent to an LCD pixel address controller 306 which is adapted to control the row control logic 110 and column control logic 112 (FIG. 3 ). A video memory 308 may be used to store the modified video data. In addition, the video memory 308 may also be used to store a previous row of video data for comparison with the present row of video data. The video memory may also be used to store one or more adjacent pixel video data values before and/or after modification, etc.

In describing the exemplary embodiments disclosed herein, a pixel voltage value (the voltage value charge on the pixel capacitor) representing black may be referred to as black or level A (00 h input to an 8-bit DAC), and a pixel voltage value representing white may be referred to as white or level D (FF h input to the 8 bit DAC). 00 h is 0 in base 10 and FF h is 255 in base 10. Gray levels may be referred to as gray or level C (greater than black—00 h and less than white—FF h to the 8 bit DAC). DACs having more or less input bits are contemplated herein and are within the scope of the present invention.

Referring to FIG. 6 , depicted is a graph of pixel voltage levels verses pixel locations illustrating operation of a prior art liquid crystal display system. A pixel at location 3 has a voltage level 610 (white FF h ) and an adjacent pixel at pixel location 4 has a voltage level 612 (black 00 h ). This voltage magnitude difference ( 612 , 610 ) between the pixels at locations 3 and 4 may be large enough to cause image degradation by fringe effect fields between those two adjacent pixels.

Referring now to FIG. 7 , depicted is a graph of pixel voltage levels verses pixel locations illustrating operation of a liquid crystal display system, according to an exemplary embodiment of the invention. A voltage level 610 at pixel locations 3 has a white voltage level 255 (FF h ) and an adjacent pixel at location 4 has a voltage level 714 (grayshade 127) which is half of the voltage level 610 (grayshade 255) of the pixel adjacent thereto (location 3 ). The next adjacent pixel at location 5 has a voltage level 716 (grayshade 63) which is half of the voltage level 714 (grayshade 127) of the pixel adjacent thereto (location 4 ). The next adjacent pixel location 6 has a voltage level 718 (grayshade 31) which is half of the voltage level 716 (grayshade 63) of the pixel adjacent thereto (location 5 ). The next adjacent pixel location 7 has a voltage level 720 (grayshade 15) which is half of the voltage level 718 (grayshade 31) of the pixel adjacent thereto (location 6 ). The next adjacent pixel location 8 has a voltage level 722 (grayshade 7) which is half of the voltage level 720 (grayshade 15) of the pixel adjacent thereto (location 7 ). The next adjacent pixel location 9 has a voltage level 724 (grayshade 3) which is half of the voltage level 722 (grayshade 7) of the pixel adjacent thereto (location 8 ). The next adjacent pixel location 10 has a voltage level 726 (grayshade 1) which is half of the voltage level 724 (grayshade 3) of the pixel adjacent thereto (location 9 ). Finally, the next adjacent pixel location 11 has a voltage level 612 (grayshade 0) which is half of the voltage level 726 (grayshade 1) of the pixel adjacent thereto (location 10 ).

The voltage magnitude differences between of the voltage levels 610 , 714 , 716 , 718 , 720 , 722 , 724 , 726 and 612 of the adjacent pixels at locations 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 and 11 , respectively, are not of sufficient magnitude to cause image degradation by fringe effect fields. The aforementioned example is for no limit on the pixel values. If a limit was used, e.g., 20 , then pixel location 4 would be grayshade 20, pixel location 5 would be grayshade 5, pixel location 7 would be grayshade 2 and pixel location 8 would be grayshade 1. Pixels at locations 9 , 10 and 11 would now be grayshade 0. The effect of a lower limit is to sharpen the edge transitions. A limit of 0 would result in no adjustment of the original pixel voltage levels, and the transition edges would be completely straight (i.e., FIG. 6 ).

Referring back to FIG. 5 , the video data comparator/modifier 310 may comprise a set of eight shift registers, a comparator and a divide by two circuit. The video source data 116 is fed from the video frame to LCD pixel gray scale conversion logic 302 to the set of eight shift registers in the video data comparator/modifier 310 . The comparator in the video data comparator/modifier 310 analyzes the pixel values in the set of shift registers and restricts a change in pixels values that is greater than a factor of two between adjacent pixels. For a sequential color LCD system, only one set of shift registers need be used. For a three color (red-green-blue) LCD system, three sets of shift registers may be used, one for each color portion of the RGB LCDs.

The video source pixel data may be stored in a video memory in the video data comparator/modifier 310 so more flexibility in timing of the pixel values modifications describe herein. In addition, both adjacent column and row pixels may be compared so that any adjacent pixel will not be written to a voltage level producing a fringe field great enough to cause image degradation. Modification of voltage values for adjacent pixels on the same row may be as described herein as well as adjacent pixels on adjacent rows. It is contemplated and within the scope of the present invention that a video memory may be utilized to store voltage values written to pixels on previous rows and/or columns so that no adjacent pixels have a voltage value difference great enough to cause field fringe effects.

Referring to FIG. 8 , depicted is a schematic flow diagram of an exemplary embodiment of the invention. The graph of FIG. 7 illustrates the operation of this exemplary embodiment. Video data values are received in step 802 . Received video data values are checked in step 804 to determine if a ratio of magnitudes between adjacent pixel data values is greater than a factor of two. In step 808 , if the ratio is greater than a factor of two, then one of the two adjacent pixel data values is modified so that there is at most a ratio of two between the adjacent pixel voltage values. In step 806 , a limit may be used so that adjacent pixel voltage values at or above the limit are not modified in step 808 ). In step 810 , the modified or unmodified video data is written to the respective pixel locations.

It is contemplated and within the scope of the invention that the LCD and/or LCD system may be partially or entirely fabricated on a semiconductor integrated circuit or integrated circuits.

The invention, therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned, as well as others inherent therein. While the invention has been depicted, described, and is defined by reference to exemplary embodiments of the invention, such references do not imply a limitation on the invention, and no such limitation is to be inferred. The invention is capable of considerable modification, alternation, and equivalents in form and function, as will occur to those having ordinarily skills in the pertinent arts and having the benefit of this disclosure. The depicted and described embodiments of the invention are exemplary only, and are not exhaustive of the scope of the invention. Consequently, the invention is intended to be limited only by the spirit and scope of the appended claims, giving full cognizance to equivalents in all respects.

Claims

1. A system for improving image quality of a liquid crystal display (LCD), said system comprising:a matrix of pixels arranged in a plurality of columns and a plurality of rows, wherein an intersection of a row and a column defines a location of a pixel in said matrix; at least one digital-to-analog converter (DAC) having a digital input and an analog output; a plurality of column switches adapted for coupling the analog output of said at least one DAC to each of said plurality of columns; a plurality of row switches adapted for selectively coupling each of said plurality of rows to said plurality of columns; column control logic for controlling said plurality of column switches; row control logic for controlling said plurality of row switches; a video frame to gray scale conversion and pixel address logic for converting video information into LCD gray scale values and corresponding pixel address locations thereof; and video data comparator/modifier logic, said video data comparator/modifier logic adapted to receive the LCD gray scale values for each pixel of the matrix of pixels, wherein gray scale values of adjacent pixels are compared and if a ratio of the gray scale values of adjacent pixels is greater than a desired value, then one of the gray scale values is modified so that the ratio of adjacent pixel gray scale values is no greater than the desired value; said video data comparator/modifier logic is adapted for sending all unmodified gray scale values and any modified gray scale values to said at least one DAC; said video frame to gray scale conversion and pixel address logic adapted for sending said pixel address locations to said column control logic and said row control logic.

2. The system of claim 1, wherein the desired value is two.

3. The system of claim 1, further comprising a video memory for storing said LCD gray scale values.

4. The system of claim 1, further comprising a video memory for storing said unmodified and said modified LCD gray scale values.

5. The system of claim 1, further comprising a video memory coupled to said video data comparator/modifier logic.

6. The system of claim 1, wherein said video data comparator/modifier logic comprises a plurality of registers adapted for storing gray scale values for at least N adjacent pixels.

7. The system of claim 6, wherein said video data comparator/modifier logic comprises a level writing decision logic for determining the ratio of the adjacent pixel LCD gray scale values.

8. The system of claim 7, wherein said level writing decision logic determines which of said LCD gray scale values are to be modified.

9. The system of claim 6, wherein N is equal to eight.

10. The system of claim 6, wherein N is equal to six.

11. The system of claim 6, wherein N is equal to ten.

12. The system of claim 6, wherein N is selected from the group consisting of 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16.

13. The system of claim 1, further comprising a gray scale look-up table coupled between said video data comparator/modifier logic and said at least one DAC.

14. The system of claim 1, wherein said LCD, said plurality of column switches and said plurality of row switches are fabricated on a semiconductor integrated circuit.

15. The system of claim 1, wherein said LCD, said plurality of column switches, said plurality of row switches, said column control logic, and said row control logic are fabricated on a semiconductor integrated circuit.

16. The system of claim 1, wherein said video frame to gray scale conversion and pixel address logic, said video data comparator/modifier logic and said at least one DAC are fabricated on at least one semiconductor integrated circuit.

17. A method for improving image quality of a liquid crystal display (LCD) comprising a matrix of pixels arranged in a plurality of rows and columns, wherein an intersection of a row and a column defines a position of a pixel in the matrix, said method comprising the steps of:determining if a ratio of gray scale values of adjacent pixels is greater than a desired value, wherein; if the ratio is less than or equal to the desired value, then writing the gray scale values to the adjacent pixels, and if the ratio is greater than the desired value, then modifying one of the gray scale values of the adjacent pixels so that the ratio is less than or equal to the desired value, and then writing a gray scale value and the modified gray scale value to the adjacent pixels.

18. The method of claim 17, further comprising the steps of:receiving video information; and converting the video information into the LCD gray scale values and the corresponding pixel address locations thereof.

19. The method of claim 17, further comprising the step of storing the LCD gray scale values and modified gray scale values in a memory.

20. The method of claim 17, further comprising the step of storing the gray scale values of adjacent pixels in a plurality of registers.

21. The method of claim 20, further comprising the step of storing the modified gray scale values of adjacent pixels in some of the plurality of registers.