Image Sensor and Method of Manufacturing the Same

Abstract

An image sensor includes a first type semiconductor layer, a second type semiconductor layer and a first type well. The first type semiconductor layer is formed on a semiconductor substrate and includes a plurality of pixels which receive external light and convert optical charges into an electrical signal. The second type semiconductor layer is supplied with a drain voltage to have a potential different from that of the first semiconductor layer, and the first type well controls a power source voltage (VDD) using the drain voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention can be understood in more detail from the following description taken in conjunction with the attached drawings in which:

FIG. 1 schematically illustrates an image sensor according to a conventional technique;

FIG. 2 is a graph representing a potential formed along a doted line X-X′ of FIG. 1;

FIG. 3 schematically illustrates an image sensor according to an exemplary embodiment of the present invention;

FIG. 4 is a graph representing a potential formed along a dotted line Y-Y′ of FIG. 3; and

FIG. 5 is a flow chart illustrating a method of manufacturing the image sensor according to an exemplary embodiment of the present invention.

Claims

1. An image sensor comprising: a first type semiconductor layer including a plurality of pixels which receive external light and convert optical charges into an electrical signal, the first type semiconductor layer is formed on a semiconductor substrate;a second type semiconductor layer supplied with a drain voltage to have a potential different from that of the first semiconductor layer; anda first type well controlling a power source voltage (VDD) using the drain voltage.

2. The image sensor of claim 1, wherein the first type semiconductor layer is a P-type semiconductor layer, the second type semiconductor layer is an N+ type semiconductor layer, and the first type well is a P-type well.

3. The image sensor of claim 1, wherein the first type well is formed in a lower portion of the pixel of the first semiconductor layer.

4. The image sensor of claim 1, wherein the first type well is formed by ion implantation.

5. The image sensor of claim 4, wherein the drain voltage is varied in accordance with an implantation energy of the first type well.

6. The image sensor of claim 5, wherein signal sensitivity and color mixing characteristics of the electrical signal are controlled in accordance with the drain voltage.

7. The image sensor of claim 5, wherein the first type well controls the drain voltage to be lower than the power source voltage (VDD).

8. The image sensor of claim 1, further comprising a power source connection element for electrically connecting the power source voltage (VDD) to the second type semiconductor layer.

9. The image sensor of claim 8, wherein the power source connection element is electrically connected to the first type well, and is spaced apart from the second semiconductor layer by a regular distance.

10. The image sensor of claim 8, wherein the power source connection element is formed by ion implantation.

11. The image sensor of claim 10, wherein the power source connection element is implanted with an N-type impurity.

12. The image sensor of claim 1, wherein the second type semiconductor layer is formed on the first type semiconductor layer.

13. The image sensor of claim 12, wherein the second type semiconductor layer is formed by doping.

14. The image sensor of claim 1, wherein the image sensor is a complementary metal oxide semiconductor (CMOS) image sensor.

15. A method of manufacturing an image sensor comprising; forming a first type semiconductor layer including a plurality of pixels which receive external light and convert optical charges into an electrical signal on a semiconductor substrate;forming a second type semiconductor layer supplied with a drain voltage to have a potential different from that of the first type semiconductor layer; andforming a first type well controlling a power source voltage (VDD) using the drain voltage.

16. The method of claim 15, wherein the first type semiconductor layer is a P-type semiconductor layer, the second type semiconductor layer is an N+ type semiconductor layer, and the first type well is a P-type well.

17. The method of claim 15, wherein the first type well is formed in a lower portion of the pixel of the first type semiconductor layer.

18. The method of claim 15, wherein the first type well is formed by ion implantation.

19. The method of claim 18, wherein the drain voltage is varied in accordance with an implantation energy of the first type well.

20. The method of claim 19, wherein the first type well controls the drain voltage to be lower than the power source voltage (VDD).

21. The method of claim 15, further comprising forming a power source connection element for electrically connecting the power source voltage (VDD) to the second type semiconductor layer.

22. The method of claim 21, wherein the power source connection element is formed by being electrically connected to the first type well, and being spaced apart from the second semiconductor layer by a regular distance.

23. The method of claim 21, wherein the power source connection element is formed by ion implantation.

24. The method of claim 23, wherein the forming of the power source connection element comprises implanting an N-type impurity.

25. The method of claim 15, wherein the image sensor is a complementary metal oxide semiconductor (CMOS) image sensor.

26. An image sensor comprising: a first type semiconductor layer including a plurality of pixels which receive external light and convert optical charges into an electrical signal, the first type semiconductor layer is formed on a semiconductor substrate;a second type semiconductor layer supplied with a drain voltage to have a potential different from that of the first semiconductor layer, the second type semiconductor layer is formed on the first type semiconductor layer; anda first type well controlling a power source voltage (VDD) using the drain voltage, the first type well is formed on the first type semiconductor layer.