Patent Application
20250227389
This application relates to the field of sensor technologies, and in particular, to an image sensor circuit, an image sensor chip, and a camera device.
Currently, two solutions are usually adopted for a common complementary metal oxide semiconductor (CMOS) image sensor to obtain images with a high dynamic range (HDR). A first solution is to perform long and short exposure (that is, exposure time is classified into long time and short time) on a photodiode when a capacitance of a floating diffusion (FD) potential point is fixed, so that quantities of generated photo-generated electrons are different, and an FD generates different voltages. A second solution is single exposure. A capacitance value of an FD point is changed, so that a same quantity of photo-generated electrons is used to generate different voltages. Currently, a single exposure manner is widely used. However, in the single exposure solution, a feedback line needs to be added to an automatic conversion gain determining mechanism currently introduced. This easily causes crosstalk to a voltage on a column bus.
An objective of embodiments of this application is to provide an image sensor circuit, an image sensor chip, and a camera device, to resolve a problem that an automatic conversion gain determining mechanism in an existing image sensor easily causes crosstalk to a voltage on a column bus coupled to a pixel unit.
To achieve the foregoing objective, implementation solutions provided in embodiments of this application are as follows:
According to a first aspect, an image sensor circuit is provided. The image sensor circuit includes a driver and a pixel array. The pixel array includes a plurality of pixel units that are coupled to the driver and that have two conversion gain modes. In addition, the image sensor circuit further includes a plurality of conversion gain selection circuits. Pixel units in a same column of the pixel array are coupled to the conversion gain selection circuit through a column bus. The driver is configured to drive the pixel unit to output a plurality of voltage signals in the two conversion gain modes. The conversion gain selection circuit is configured to output one analog signal and one digital signal based on the plurality of voltage signals. The digital signal indicates a conversion gain mode of the pixel unit, and the analog signal represents an output voltage corresponding to the conversion gain mode. In this manner, the conversion gain selection circuit may directly select a conversion gain mode under a present incident light intensity based on a voltage output by the column bus connected to the pixel unit, without disposing an additional feedback line. This does not cause crosstalk to the voltage on the column bus.
In a possible implementation, the pixel unit includes a photodiode, and a floating diffusion node coupled to the photodiode through a switch. The driver may first input a low level to the switch, and drive the pixel unit to output a first voltage signal in a low conversion gain and output a second voltage signal in a high conversion gain mode. Then, the driver inputs a high level to the switch, and drives the pixel unit to output a third voltage signal in the high conversion gain mode and output a fourth voltage signal in the low conversion gain mode. The conversion gain selection circuit outputs a first analog signal and a first digital signal, or outputs a second analog signal and a second digital signal. The first analog signal is obtained by subtracting the third voltage signal from the second voltage signal, and the second analog signal is obtained by subtracting the fourth voltage signal from the first voltage signal. The first digital signal and the second digital signal are obtained by comparing the third voltage signal with a first reference voltage, or the first digital signal and the second digital signal are obtained by comparing the fourth voltage signal with a second reference voltage. Levels of the first digital signal and the second digital signal are opposite. Based on this, the pixel circuit may separately output voltage signals in the two conversion gain modes when the switch is in an on state and an off state, and the conversion gain selection circuit may directly select a proper conversion gain mode based on the received voltage signal, and output a corresponding analog signal for subsequent processing, without providing feedback to the pixel unit.
In a possible implementation, the conversion gain selection circuit includes a first output port, a second output port, a correlated double sampling circuit, a determining circuit, and a control circuit. Both an input end of the correlated double sampling circuit and an input end of the determining circuit are coupled to the column bus, an output end of the correlated double sampling circuit is coupled to the first output port, an output end of the determining circuit is separately coupled to the second output port and an input end of the control circuit, and the correlated double sampling circuit is further coupled to an output end of the control circuit. The correlated double sampling circuit is configured to receive the first voltage signal and the second voltage signal. The determining circuit is configured to: receive the third voltage signal and the first reference voltage, and output the first digital signal or the second digital signal; or the determining circuit is further configured to: receive the fourth voltage signal and the second reference voltage, and output the first digital signal or the second digital signal. The control circuit is configured to send a first signal and a second signal to the correlated double sampling circuit when receiving the first digital signal. In response to the first signal, the correlated double sampling circuit receives the third voltage signal. In response to the second signal, the correlated double sampling circuit outputs the first analog signal. The control circuit is further configured to send a third signal and a fourth signal to the correlated double sampling circuit when receiving the second digital signal. In response to the third signal, the correlated double sampling circuit receives the fourth voltage signal. In response to the fourth signal, the correlated double sampling circuit outputs the second analog signal. Based on this, the conversion gain selection circuit can automatically select a conversion gain mode and output a corresponding analog signal based on an output result of the determining circuit. In addition, there is no feedback signal between the conversion gain selection circuit and the pixel unit, and impact of the feedback signal on the pixel unit does not need to be considered when optimization is performed on the conversion gain selection circuit.
In a possible implementation, the correlated double sampling circuit includes a first voltage receiving circuit, a second voltage receiving circuit, a third voltage receiving circuit, and a subtractor. The first voltage receiving circuit and the second voltage receiving circuit are connected in parallel between the column bus and a non-inverting input end of the subtractor, the third voltage receiving circuit is coupled between the column bus and an inverting input end of the subtractor, and an output end of the subtractor is coupled to the first output port. The first voltage receiving circuit receives the first voltage signal based on an input first clock signal. The second voltage receiving circuit receives the second voltage signal based on an input second clock signal. The third voltage receiving circuit receives the third voltage signal based on the first signal. The third voltage receiving circuit outputs the third voltage signal based on an input third clock signal, and the second voltage receiving circuit outputs the second voltage signal based on the second signal. The subtractor outputs the first analog signal based on the second voltage signal and the third voltage signal, or the third voltage receiving circuit receives the fourth voltage signal based on the third signal. The third voltage receiving circuit outputs the fourth voltage signal based on an input fourth clock signal, and the first voltage receiving circuit outputs the first voltage signal based on the fourth signal. The subtractor outputs the second analog signal based on the first voltage signal and the fourth voltage signal. Based on this, capacitors disposed in a plurality of voltage receiving circuits may receive, in a process of selecting the conversion gain mode, voltage signals output by the pixel circuit in different time periods, so that a circuit structure is simpler, and costs are reduced.
In a possible implementation, the first voltage receiving circuit includes a first transistor, a second transistor, and a first capacitor. A control electrode of the first transistor is configured to input the first clock signal, a first electrode of the first transistor is coupled to the column bus, both a second electrode of the first transistor and a first end of the first capacitor are coupled to a first electrode of the second transistor, a second end of the first capacitor is grounded, a control electrode of the second transistor is coupled to the control circuit, and is configured to input the fourth signal, and a second electrode of the second transistor is coupled to the non-inverting input end of the subtractor. Based on this, conduction and cut-off of the first transistor and the second transistor are controlled, so that a process of receiving or outputting the first voltage signal can be accurately controlled.
In a possible implementation, the second voltage receiving circuit includes a third transistor, a fourth transistor, and a second capacitor. A control electrode of the third transistor is configured to input the second clock signal, a first electrode of the third transistor is coupled to the column bus, both a second electrode of the third transistor and a first end of the second capacitor are coupled to a first electrode of the fourth transistor, a second end of the second capacitor is grounded, a control electrode of the fourth transistor is coupled to the control circuit, and is configured to input the second signal, and a second electrode of the fourth transistor is coupled to the non-inverting input end of the subtractor. Based on this, conduction and cut-off of the third transistor and the fourth transistor are controlled, so that a process of receiving or outputting the second voltage signal can be accurately controlled.
In a possible implementation, the third voltage receiving circuit includes a fifth transistor, a sixth transistor, and a third capacitor. A control electrode of the fifth transistor is configured to input the first signal or the third signal, a first electrode of the fifth transistor is coupled to the column bus, both a second electrode of the fifth transistor and a first end of the third capacitor are coupled to a first electrode of the sixth transistor, a second end of the third capacitor is grounded, a control electrode of the sixth transistor is configured to input the third clock signal or the fourth clock signal, and a second electrode of the sixth transistor is coupled to the inverting input end of the subtractor. Based on this, conduction and cut-off of the transistors are controlled, so that a process of receiving or outputting the third voltage signal can be accurately controlled.
In a possible implementation, the determining circuit includes a reference voltage input end, a seventh transistor, and a comparator. When a control electrode of the seventh transistor inputs a high level, the comparator receives the third voltage signal or the fourth voltage signal. A first electrode of the seventh transistor is coupled to the column bus, a second electrode of the seventh transistor is coupled to an inverting input end of the comparator, a non-inverting input end of the comparator is coupled to the reference voltage input end, and an output end of the comparator is separately coupled to the input end of the control circuit and the second output port. Based on this, a clock generator may control the seventh transistor to compare voltages in different conversion gain modes with a given reference voltage, so that a voltage for comparison is selected according to an actual requirement.
In a possible implementation, the image sensor circuit further includes an analog-to-digital converter coupled to the first output port, and the comparator is included in the analog-to-digital converter. Based on this, no additional comparator needs to be disposed, so that a quantity of used components can be reduced while a function requirement is met. This reduces production costs.
In a possible implementation, a gain amplifier may be further disposed between the first output port and the analog-to-digital converter. Based on this, amplification processing may be performed on an analog signal output by the correlated double sampling circuit. This increases a quantity of signals that can be used for image processing, and further improves image precision.
In a possible implementation, the conversion gain selection circuit includes a first output port, a second output port, a correlated double sampling circuit, a determining circuit, and a control circuit. An input end of the correlated double sampling circuit is coupled to the column bus, and both an input end of the determining circuit and the first output port are coupled to an output end of the correlated double sampling circuit. Both an input end of the control circuit and the second output port are coupled to an output end of the determining circuit, and an output end of the control circuit is further coupled to the correlated sampling circuit. The correlated double sampling circuit is configured to receive the first voltage signal and the second voltage signal. The correlated double sampling circuit is further configured to: receive the third voltage signal, and output a fifth voltage to the determining circuit. The fifth voltage is obtained by subtracting the third voltage signal from the second voltage signal. The determining circuit is configured to: receive the fifth voltage and the first reference voltage, and output the first digital signal or the second digital signal. The control circuit is configured to output a first signal when receiving the first digital signal. In response to the first signal, the correlated double sampling circuit outputs the first analog signal. The control circuit is further configured to output a second signal and a third signal when receiving the second digital signal. In response to the second signal, the correlated double sampling circuit receives the fourth voltage signal. In response to the third signal, the correlated double sampling circuit outputs the second analog signal.
In this manner, after receiving a voltage signal output by the pixel unit, the conversion gain selection circuit may select a conversion gain mode based on a signal output by the conversion gain selection circuit.
In a possible implementation, the correlated double sampling circuit includes a first voltage receiving circuit, a second voltage receiving circuit, a third voltage receiving circuit, and a subtractor. The first voltage receiving circuit and the second voltage receiving circuit are connected in parallel between the column bus and a non-inverting input end of the subtractor, the third voltage receiving circuit is coupled between the column bus and an inverting input end of the subtractor, and an output end of the subtractor is coupled to the first output port. The first voltage receiving circuit receives the first voltage signal based on an input first clock signal. The second voltage receiving circuit receives the second voltage signal based on an input second clock signal. The third voltage receiving circuit receives the third voltage signal based on an input third clock signal; the third voltage receiving circuit outputs the third voltage signal based on an input fourth clock signal, and the second voltage receiving circuit outputs the second voltage signal based on the first signal; and the subtractor outputs the first analog signal based on the second voltage signal and the third voltage signal; or the third voltage receiving circuit receives the fourth voltage signal based on the input second signal; the third voltage receiving circuit outputs the fourth voltage signal based on an input fifth clock signal, and the first voltage receiving circuit outputs the first voltage signal based on the third signal; and the subtractor outputs the second analog signal based on the first voltage signal and the fourth voltage signal.
In a possible implementation, the first voltage receiving circuit includes a first transistor, a second transistor, and a first capacitor. A control electrode of the first transistor is configured to input the third clock signal, a first electrode of the first transistor is coupled to the column bus, both a second electrode of the first transistor and a first end of the first capacitor are coupled to a first electrode of the second transistor, a second end of the first capacitor is grounded, a control electrode of the second transistor is coupled to the control circuit, and is configured to input the third signal, and a second electrode of the second transistor is coupled to the non-inverting input end of the subtractor.
In a possible implementation, the second voltage receiving circuit includes a third transistor, a fourth transistor, and a second capacitor. A control electrode of the third transistor is configured to input the second clock signal, a first electrode of the third transistor is coupled to the column bus, both a second electrode of the third transistor and a first end of the second capacitor are coupled to a first electrode of the fourth transistor, a second end of the second capacitor is grounded, a control electrode of the fourth transistor is coupled to the control circuit, and is configured to input the first signal, and a second electrode of the fourth transistor is coupled to the non-inverting input end of the subtractor.
In a possible implementation, the third voltage receiving circuit includes a fifth transistor, a sixth transistor, and a third capacitor. A control electrode of the fifth transistor is configured to input the second signal or the third clock signal, a first electrode of the fifth transistor is coupled to the column bus, both a second electrode of the fifth transistor and a first end of the third capacitor are coupled to a first electrode of the sixth transistor, a second end of the third capacitor is grounded, a control electrode of the sixth transistor is configured to input the fourth clock signal or the fifth clock signal, and a second electrode of the sixth transistor is coupled to the inverting input end of the subtractor.
In a possible implementation, the determining circuit includes a reference voltage input end and a comparator. An inverting input end of the comparator is coupled to the output end of the correlated double sampling circuit, a non-inverting input end of the comparator is coupled to the reference voltage input end, and an output end of the comparator is separately coupled to the input end of the control circuit and the second output port.
In a possible implementation, the image sensor circuit further includes an analog-to-digital converter coupled to the first output port, and the comparator is included in the analog-to-digital converter.
In a possible implementation, the conversion gain selection circuit further includes a gain amplifier. An input end of the gain amplifier is coupled to the output end of the subtractor, and an output end of the gain amplifier is coupled to the input end of the determining circuit and the first output port. Based on this, a quantity of used components can be reduced while a function requirement is met. This reduces production costs.
According to a second aspect, an image sensor chip is provided. The image sensor chip includes the image sensor circuit, in any one of the foregoing possible implementations, packaged in a package structure.
According to a third aspect, a camera device is provided. The camera device includes the image sensor chip in the second aspect.
The following describes technical solutions in embodiments of this application with reference to the accompanying drawings in embodiments of this application.
In descriptions of this application, unless otherwise specified, “/” represents an “or” relationship between associated objects. For example, A/B may represent A or B. The term “and/or” in this application is merely an association relationship for describing the associated objects, and represents that three relationships may exist. For example, A and/or B may represent the following three cases: Only A exists, both A and B exist, and only B exists, where A and B may be singular or plural. In addition, in the descriptions of this application, unless otherwise specified, “a plurality of” means two or more than two. “At least one item (piece) of the following” or a similar expression thereof means any combination of these items, including a singular item (piece) or any combination of plural items (pieces). For example, at least one item (piece) of a, b, or c may indicate: a; b; c; a and b; a and c; b and c; or a, b, and c; where a, b, and c may be singular or plural. In addition, to clearly describe the technical solutions in embodiments of this application, terms such as first and second are used in embodiments of this application to distinguish between same items or similar items that provide basically same functions or purposes. A person skilled in the art may understand that the terms such as “first” and “second” do not limit a quantity or an execution sequence, and the terms such as “first” and “second” do not indicate a definite difference. In addition, in embodiments of this application, terms such as “example” or “for example” are used to represent giving an example, an illustration, or a description. Any embodiment or design scheme described as an “example” or “for example” in embodiments of this application should not be explained as being more preferred or having more advantages than another embodiment or design scheme. In embodiments of this application, unless otherwise clearly specified and limited, the term “coupling” may be a manner of implementing an electrical coupling for signal transmission, and the term “coupling” may be a direct electrical coupling, or may be an indirect electrical coupling through an intermediate medium. For example, coupling is implemented by using a resistor, an inductor, or another electrical element.
Exactly, use of the terms such as “example” or “for example” is intended to present a related concept in a specific manner for ease of understanding.
A pixel unit in a CMOS image sensor that is commonly used currently includes a photodiode, and a floating diffusion node coupled to the photodiode through a switch. For example, as shown in
To obtain images with a high dynamic range (HDR), two solutions may be adopted. A first solution is to perform long-term and short-term exposure (that is, exposure time is classified into long time and short time) on the photodiode (PD), so that quantities of photo-generated electrons are different. In this way, voltage changes at the FD point are different, and CFD is fixed at this time. A second solution is single exposure. A capacitance value of CFD is changed, so that a same quantity of photo-generated electrons is used to generate different voltage.
For the single exposure solution, two conversion gain modes are usually used, to obtain an image with a high dynamic range. In a low-illumination environment, the capacitance value of CFD is small when a high conversion gain mode (HCG) is used. In a high-illumination environment, the capacitance value of CFD is large when a low conversion gain mode (LCG) is used. Certainly, the foregoing method may also be applicable to a multi-gain solution in which different CFD values correspond to different incident light intensities.
In an existing pixel design, the capacitance value of CFD is usually changed by using a method of connecting a capacitor CS in parallel with the FD. Specifically, in the high conversion gain mode (HCG), the switch for double conversion gain (SDCG) is turned off, and a parasitic capacitance Cpar of the FD is denoted as CFD, namely, CFD, HCG=Cpar. In the low conversion gain mode (LCG), the switch for double conversion gain (SDCG) is turned on, and CS is connected to the FD point, so that the capacitance of the FD point is changed to Cpar+CS, namely, CFD, LCG=Cpar+CS.
For the photo-generated electrons generated in the single exposure solution, regardless of the incident light intensity, two times of switching, namely, the HCG and the LCG, need to be performed, and two corresponding voltage values are output separately. An ADC generates two quantization results, HDR synthesizing is performed, and a frame of image is finally output. Specific steps are as follows:
It can be learned from the steps that, in this solution, two quantization results need to be output each time of exposure for final HDR synthesizing, and the CDS, the PGA, and the ADC all need to work twice. Therefore, a calculation amount is large, a large memory space is occupied, power consumption is increased, and improvement of a frame rate is also limited.
As shown in
As shown in
To resolve the foregoing problem, an embodiment of this application provides an image sensor circuit 400. As shown in
In a possible implementation, the driver 410 is configured to: input a low level to a switch TG, and drive the pixel unit to output a first voltage signal in a low conversion gain and output a second voltage signal in a high conversion gain mode. In addition, the driver 410 is further configured to: input a high level to the switch TG, and drive the pixel unit to output a third voltage signal in the high conversion gain mode and output a fourth voltage signal in the low conversion gain mode. The conversion gain selection circuit 430 is configured to: output a first analog signal and a first digital signal, or output a second analog signal and a second digital signal. The first analog signal is obtained by subtracting the third voltage signal from the second voltage signal, and the second analog signal is obtained by subtracting the fourth voltage signal from the first voltage signal. The first digital signal and the second digital signal are obtained by comparing the third voltage signal with a first reference voltage, or the first digital signal and the second digital signal are obtained by comparing the fourth voltage signal with a second reference voltage. Levels of the first digital signal and the second digital signal are opposite.
The pixel unit in
In the foregoing implementation process, the first digital signal and the second digital signal indicate the two conversion gain modes of the pixel unit. The first digital signal indicates the high conversion gain mode of the pixel unit, and may be represented by a digit “0”; and the second digital signal indicates the low conversion gain mode of the pixel unit, and may be represented by a digit “1”. The first digital signal and the second digital signal may be stored into a memory coupled to a second output port 433. A first output port 432 may be coupled to an analog-to-digital converter ADC, and the analog-to-digital converter may convert the first analog signal or the second analog signal into a digital signal for subsequent image processing.
In the foregoing implementation process, no feedback line needs to be disposed between the conversion gain selection circuit 430 and the pixel unit. This reduces cabling difficulty, and avoids crosstalk to a voltage on the column bus (VSL). In addition, the conversion gain selection circuit 430 and the pixel array 420 are disposed independently, so that it is more flexible when optimization is performed on the circuit.
The image sensor circuit 400 further includes a clock generator 440. The clock generator 440 is coupled to the driver 410 and each conversion gain selection circuit 430. The clock generator 440 is configured to provide a clock control signal for the driver 410 and each conversion gain selection circuit 430.
As shown in
Optionally, the control circuit 436 may further send a third signal and a fourth signal to the correlated double sampling circuit 434 when receiving the second digital signal. The correlated double sampling circuit 434 receives the fourth voltage signal when receiving the third signal. The correlated double sampling circuit 434 outputs the second analog signal when the correlated double sampling circuit 434 receives the fourth signal.
For example, the correlated double sampling circuit 434 may be controlled, based on a first clock signal output by the clock generator 440, to receive the first voltage signal, and the correlated double sampling circuit 434 may be controlled, based on a second clock signal output by the clock generator 440, to receive the second voltage signal. The determining circuit 435 compares the third voltage signal with the first reference voltage. When it is determined that the third voltage signal is greater than the first reference voltage, the first digital signal is output. When it is determined that the third voltage signal is less than the first reference voltage, the second digital signal is output. Alternatively, the determining circuit 435 may compare the fourth voltage signal with the second reference voltage. When it is determined that the fourth voltage signal is greater than the second reference voltage, the first digital signal is output. When it is determined that the fourth voltage signal is less than the second reference voltage, the second digital signal is output. The control circuit 436 may output the first signal and the second signal to the correlated double sampling circuit 434 when receiving the first digital signal. The correlated double sampling circuit 434 receives the third voltage signal when receiving the first signal. When the second signal is received, the second voltage signal is output. In this case, the correlated double sampling circuit 434 outputs the third voltage signal based on a third clock signal sent by the clock generator 440, and obtains the first analog signal by subtracting the third voltage signal from the second voltage signal. The control circuit 436 may send the third signal and the fourth signal to the control correlated double sampling circuit 434 when receiving the second digital signal. The correlated double sampling circuit 434 receives the fourth voltage signal when receiving the third signal; and outputs the first voltage signal when receiving the fourth signal. In this case, the correlated double sampling circuit 434 outputs the fourth voltage signal based on a fourth clock signal sent by the clock generator 440, and obtains the second analog signal by subtracting the fourth voltage signal from the first voltage signal.
In the foregoing manner, the correlated double sampling circuit 434 may automatically select, under control of the control circuit 436 and the clock generator 440, a most appropriate conversion gain mode under a present incident light intensity. The control circuit 436 controls the correlated double sampling circuit 434 based on the digital signal output by the determining circuit 435, so that a voltage output by the correlated double sampling circuit 434 can be more flexibly regulated. In addition, the digital signal and the analog signal that are output can be also combined, so that a subsequent processing circuit can perform image processing more conveniently.
Optionally, a gain amplifier may be further disposed between the first output port 432 and the analog-to-digital converter ADC, and the output voltage is amplified by the gain amplifier and then sent to the ADC for conversion into a digital signal. A programmable gain amplifier (PGA) may be selected as the gain amplifier, so that a gain of the amplifier can be adjusted according to an actual requirement. The ADC and the PGA are enabled based on a clock signal output by the clock generator 440, so that start time can be accurately controlled.
It may be understood that another type of gain amplifier may alternatively be selected. This is not specifically limited in this embodiment of this application.
In an implementation solution, as shown in
In an implementation solution, the first voltage receiving circuit 4341 includes a first transistor ΦRL, a second transistor Φ1, and a first capacitor CRL. A control electrode of the first transistor ΦRL is coupled to the clock generator 440, and is configured to input the first clock signal. A first electrode of the first transistor ΦRL is coupled to the input port 431. Both a second electrode of the first transistor ΦRL and a first end of the first capacitor CRL are coupled to a first electrode of the second transistor Φ1. A second end of the first capacitor CRL is grounded. A control electrode of the second transistor Φ1 is coupled to the control circuit 436, and is configured to input the fourth signal. A second electrode of the second transistor Φ1 is coupled to the non-inverting input end of the subtractor 4344. When the first capacitor needs to receive a voltage, the clock generator 440 may control the first transistor ΦRL to be conducted. When a voltage received by the first capacitor needs to be output, the control circuit 436 may control the second transistor Φ1 to be conducted.
Further, the second voltage receiving circuit 4342 includes a third transistor ΦRH, a fourth transistor Φ2, and a second capacitor CRH. A control electrode of the third transistor ΦRH is coupled to the clock generator 440, and is configured to input the second clock signal. A first electrode of the third transistor ΦRH is coupled to the input port 431. Both a second electrode of the third transistor ΦRH and a first end of the second capacitor CRH are coupled to a first electrode of the fourth transistor Φ2. A second end of the second capacitor CRH is grounded. A control electrode of the fourth transistor Φ2 is coupled to the control circuit 436, and is configured to input the second signal. A second electrode of the fourth transistor Φ2 is coupled to the non-inverting input end of the subtractor 4344.
Further, the third voltage receiving circuit 4343 includes a fifth transistor Φsig, a sixth transistor Φ3, and a third capacitor Csig. A control electrode of the fifth transistor Φsig is coupled to the control circuit 436, and is configured to input the first signal or the third signal. A first electrode of the fifth transistor Φsig is coupled to the input port 431. Both a second electrode of the fifth transistor Φsig and a first end of the third capacitor Csig are coupled to a first electrode of the sixth transistor Φ3. A second end of the third capacitor Csig is grounded. A control electrode of the sixth transistor Φ3 is coupled to the clock generator 440, and is configured to input the third clock signal or the fourth clock signal. A second electrode of the sixth transistor Φ3 is coupled to the inverting input end of the subtractor 4344.
In the foregoing manner, the clock generator 440 and the control circuit 436 can more accurately control output voltages in different conversion gain modes.
In an implementation solution, the determining circuit 435 includes a reference voltage input end (namely, an input end corresponding to a reference voltage VREF), a seventh transistor Φcomp, and a comparator U1. A control electrode of the seventh transistor Φcomp is coupled to the clock generator 440. A first electrode of the seventh transistor Φcomp is coupled to the input port 431 end. A second electrode of the seventh transistor Φcomp is coupled to an inverting input end of the comparator U1. A non-inverting input end of the comparator U1 is coupled to the reference voltage input end. An output end of the comparator U1 is separately coupled to the control circuit 436 and the second output port 433. When controlling the seventh transistor Φcomp to be conducted, the control circuit 436 may compare an output voltage of the pixel unit with the given reference voltage VREF.
In the foregoing manner, the clock generator 440 controls a conducted/cut-off state of the seventh transistor Φcomp, so that the determining circuit may be controlled to use a voltage output by the pixel unit in a specific conversion gain mode as a determining basis. This is more convenient during use.
Further, the comparator may use an independent comparator, or may reuse a comparator inside the analog-to-digital converter ADC. For example, as shown in
In an implementation solution, as shown in
Optionally, the first control unit 4362 includes a first AND gate A1. A first input end of the first AND gate A1 is coupled to the clock generator 440, a second input end of the first AND gate A1 is coupled to the output end of the determining circuit 435, and an output end of the first AND gate A1 is coupled to the control electrode of the second transistor Φ1. The second control unit 4362 includes a first NOT gate N1 and a second AND gate A2. An input end of the first NOT gate N1 is coupled to the output end of the determining circuit 435, and a first input end of the second AND gate A2 is coupled to the clock generator 440. A second input end of the second AND gate A2 is coupled to an output end of the first NOT gate N1, and an output end of the second AND gate A2 is coupled to the control electrode of the fourth transistor Φ2. The third control unit 4363 includes a second NOT gate N2, a D trigger U2, a first transmission gate Φ5, a second transmission gate Φ6, and a third AND gate A3. A first electrode of the first transmission gate Φ5 is coupled to the output end of the determining circuit 435, and both an input end of the second NOT gate N2 and a first electrode of the second transmission gate Φ6 are coupled to a second electrode of the first transmission gate Φ5. An output end of the second NOT gate N2 is coupled to an input end of the D trigger U2. A clock pin of the D trigger U2, a control electrode of the first transmission gate Φ5, a control electrode of the second transmission gate Φ6, and a first input end of the third AND gate A3 are all coupled to the clock generator 440. Both a second input end of the third AND gate A3 and a second electrode of the second transmission gate Φ6 are coupled to an output end of the D trigger U2. An output end of the third AND gate A3 is coupled to the control electrode of the fifth transistor Φsig.
In the foregoing implementation process, when the digital signal (DCGFlag) is 0, the clock generator controls, based on an output control signal, the first transmission gate Φ5 to be conducted, inputs the digital signal to the D trigger, cuts off the first transmission gate Φ5, and conducts the second transmission gate Φ6.
Optionally, the control circuit 436 may alternatively be implemented by using a single-chip microcomputer, a digital signal processor, or another logic circuit that can implement a same or similar function. This is not specifically limited in this embodiment of this application. An NMOS transistor may be selected as the first transmission gate Φ5 and the second transmission gate Φ6.
To facilitate understanding of the technical solutions of this application, in this embodiment of this application, a process of selecting a conversion gain mode of the image sensor circuit is briefly described by using the pixel array 420 including pixel units in
As shown in
In the foregoing implementation process, when the digital signal (DCGFlag) is 0 (namely, a low level), the clock generator 440 controls, based on the high level output by “Φ5 clock”, the first transmission gate Φ5 to be conducted, and inputs the digital signal to the D trigger. Secondly, the clock generator 440 cuts off the first transmission gate Φ5 based on the low level output by “Φ5 clock”, and controls, based on the high level output by “Φ4 clock”, the D trigger to output an inverted signal 1 (namely, a high level) of the second NOT gate N2. Then, the high level output by “Φsig clock” and the output signal of the D trigger pass through the third AND gate A3 to obtain a high-level control signal of Φsig. Finally, “Φ6 clock” outputs a high level to the second transmission gate Φ6, feeds back an output of the D trigger to the input end of the D trigger, and stores the output in the D trigger after the output passes through the second NOT gate N2. In this manner, the D trigger can be enabled in a timely manner, to ensure that the third AND gate A3 can output an accurate digital signal.
With reference to
After the image sensor circuit is powered on, at a moment T1, the driver 410 continuously outputs high levels to the RST, the TG, and the switch for double conversion gain (SDCG), to reset the FD, the PD, and the CS. Duration during which the driver 410 continuously outputs the high levels to the RST, the TG, and the switch for double conversion gain (SDCG) may be set according to an actual reset requirement of a component.
After the reset ends, the driver 410 continuously outputs low levels to the RST and the TG, so that the RST and the TG are cut off, an integration stage is entered, and the pixel unit starts to be exposed. At the same time, the switch for double conversion gain (SDCG) is still in an on state (that is, the pixel unit enters the LCG mode by default).
When a moment T2 is reached, the switch for double conversion gain (SDCG) is still in the on state, and the clock generator 440 outputs a high level to the first transistor ΦRL, so that the first transistor ΦRL is conducted, and the capacitor CRL, receives the first voltage signal VRL in the LCG mode. After a period of time, the driver 410 outputs low levels to the first transistor ΦRL and the switch for double conversion gain (SDCG), so that the first transistor ΦRL is cut off and the switch for double conversion gain (SDCG) is turned off, and the pixel unit enters the HCG mode. Turn-off time of the switch for double conversion gain (SDCG) is later than cut-off time of the first transistor ΦRH.
When a moment T3 is reached, the clock generator 440 continuously outputs a high level to ΦRH for a period of time, so that ΦRH is conducted, and the capacitor CRH receives the second voltage signal VRH in the HCG mode; and then the clock generator 440 continuously outputs a low level to ΦRH, so that ΦRH is cut off.
When a moment T4 is reached, the driver 410 continuously outputs a high level to the TG in the pixel unit for a period of time, so that the TG is conducted, and photo-generated electrons in the PD are transferred to the FD; and then the driver 410 continuously outputs a low level to the TG, so that the TG is cut off.
When a moment T5 is reached, the clock generator 440 outputs a high level to the seventh transistor ΦComp for a period of time, so that the seventh transistor ΦComp is conducted, and the third voltage signal VSH at this time (namely, in the HCG mode) is sent to the comparator for comparison with the first reference voltage VREF. If VSH is greater than VREF, there are fewer photo-generated electrons, and the HCG mode is more suitable for a present incident light intensity. In this case, a digital signal (DCGFlag) output from the second output port in the HCG mode is a logic level “0”, and is sent to the memory.
When a moment T6 is reached, the control circuit continuously outputs a high level to ΦSig for a period of time, so that ΦSig is conducted, VSH is stored into Csig, and then a low level is continuously output to ΦSig.
When a moment T7 is reached, the driver 410 continuously outputs a high level to the SDCG, so that the SDCG is turned on, and the pixel unit is switched to the LCG mode. At the same time, the driver 410 outputs a high level to the TG for a period of time; and after the photo-generated electrons in the PD are transferred to the FD, the driver 410 outputs a low level to the TG, so that the TG is cut off.
When a moment T8 is reached, the control circuit 436 continuously outputs a low level to ΦSig, so that ΦSig is cut off, to prevent the voltage VSH that has been stored into Csig from being changed.
When a moment T9 is reached, the driver 410 continuously outputs a low level to the SDCG, so that the SDCG is turned off.
When a moment T10 is reached, the clock generator 440 continuously outputs a high level to Φ3 for a period of time, and outputs the second voltage signal received by Csig. At the same time, the control circuit 436 continuously outputs a high level to Φ2 for a period of time, and outputs the third voltage signal received by CRH. After the second voltage signal and the third voltage signal are processed by the subtractor 4344, a result Vout (namely, VRH−VSH) is output from the first output port.
In the foregoing implementation process, “Φ2 clock” output by the clock generator 440 is at a high level only at the moment T10, and “Φ1 clock” is at a low level throughout the process. “Φsig clock” is at a high level at the moment T6. Duration of each high level and each low level may be adjusted according to an actual requirement of each component. In addition, the foregoing moments may alternatively be preset according to a requirement of each component. For example, high-level duration of a corresponding transistor when each capacitor receives a voltage signal may be obtained by dividing a capacity of each capacitor by a current in a corresponding line. A step performed at the moment T6 may still be performed at the moment T5.
Optionally, when the moment T5 is reached, the clock generator 440 may alternatively continue to output a low level to the seventh transistor ΦComp, so that the seventh transistor ΦComp remains in a cut-off state, and then continue to perform processes at the moment T6 and the moment T7. When the moment T8 is reached, the clock generator 440 outputs a high level again to the seventh transistor ΦComp for a period of time, so that the seventh transistor ΦComp is conducted, and the fourth voltage signal VSL at this time (namely, in the LCG mode) is sent to the comparator for comparison with the second reference voltage Vref. If VSL is greater than Vref, there are fewer photo-generated electrons, and the HCG mode is more suitable for a present incident light intensity. In this case, a digital signal (DCGFlag) output from the second output port in the HCG mode is set to a logic level “0”, and is sent to the memory. At the same time, the control circuit continuously outputs a low level to ΦSig, so that ΦSig is cut off, to prevent the voltage VSH that has been stored into Csig from being changed. Then, a subsequent process continues to be performed.
As shown in
When a moment T6 is reached, the control circuit continuously outputs a low level to ΦSig, so that ΦSig is cut off.
When a moment T7 is reached, the driver 410 continuously outputs a high level to the SDCG, so that the SDCG is turned on, and the pixel unit is switched to the LCG mode. At the same time, the driver 410 outputs a high level to the TG for a period of time; and after the photo-generated electrons in the PD are transferred to the FD, the driver 410 continuously outputs a low level to the TG, so that the TG is cut off.
When a moment T8 is reached, the control circuit 436 continuously outputs a high level again to ΦSig for a period of time, so that ΦSig is conducted, the third voltage signal VSL is stored into CSig, and then a low level is continuously output to ΦSig.
When a moment T9 is reached, the driver 410 continuously outputs a low level to the SDCG, so that the SDCG is turned off.
When a moment T10 is reached, the clock generator 440 continuously outputs a high level to Φ3 for a period of time, and outputs the fourth voltage signal VSL received by Csig. At the same time, the control circuit continuously outputs a high level to Φ1 for a period of time, and outputs the first voltage signal VRL received by CRL. After the first voltage signal VRL and the fourth voltage signal VSL are processed by the subtractor 4344, a result Vout (namely, VRL−VSL) is output from the first output port.
Optionally, when the moment T5 is reached, the clock generator 440 may alternatively continue to output a low level to the seventh transistor ΦComp, so that the seventh transistor ΦComp remains in a cut-off state, and then continue to perform processes at the moment T6 and the moment T7. When the moment T8 is reached, the clock generator 440 outputs a high level again to the seventh transistor ΦComp for a period of time, so that the seventh transistor ΦComp is conducted, and the fourth voltage signal VSL at this time (namely, in the LCG mode) is sent to the comparator for comparison with the second reference voltage Vref. If VSL is less than Vref, there are more photo-generated electrons, and the LCG mode is more suitable for a present incident light intensity. In this case, a digital signal (DCGFlag) output from the second output port in the LCG mode is a logic level “1”, and is sent to the memory. At the same time, the control circuit continuously outputs a high level to ΦSig for a period of time, so that ΦSig is conducted, and the fourth voltage signal VSL is stored into Csig. Then, the control circuit continuously outputs a low level to ΦSig, so that ΦSig is cut off, and a subsequent process continues to be performed.
It may be understood that the memory may be a volatile memory or a non-volatile memory, or may include both a volatile memory and a non-volatile memory. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (random access memory, RAM) and is used as an external cache. Through an example rather than a limitative description, random access memories (RAMs) in many forms may be used, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous coupled dynamic random access memory (SLDRAM), and a direct rambus random access memory (DR RAM).
As shown in
A difference between the image sensor circuit 1300 and the first image sensor circuit 400 provided in embodiments of this application lies in that: The conversion gain selection circuit 1330 is configured to: receive a third voltage signal, and compare a fifth voltage obtained by subtracting the third voltage signal from a second voltage signal with a first reference voltage. When it is determined that the fifth voltage is less than the first reference voltage, the fifth voltage is output as a first analog signal. When it is determined that the fifth voltage is greater than the first reference voltage, a fourth voltage signal is received, and a sixth voltage obtained by subtracting the fourth voltage signal from a first voltage signal is output as a second analog signal. Alternatively, the conversion gain selection circuit 1330 is configured to: receive a fourth voltage signal, and compare a sixth voltage with a second reference voltage. When it is determined that the sixth voltage is greater than the second reference voltage, the sixth voltage is output as a second analog signal. When it is determined that the sixth voltage is less than the second reference voltage, a third voltage signal is received, and a fifth voltage is output as a first analog signal.
In the foregoing implementation process, no feedback line needs to be disposed between the conversion gain selection circuit 1330 and the pixel unit. This reduces cabling difficulty, and avoids crosstalk to a voltage on the column bus (VSL). In addition, the conversion gain circuit 1330 and the pixel array 1320 are disposed independently, so that it is more flexible when optimization is performed on the circuit.
In an implementation solution, as shown in
For example, the correlated double sampling circuit 1370 may be controlled, based on a clock signal output by the clock generator 1400, to receive the first voltage signal and the second voltage signal. In addition, the control circuit 1390 controls the correlated double sampling circuit 1370 to receive the third voltage signal or the fourth voltage signal. The control circuit 1390 and the clock generator 1400 may further control the correlated double sampling circuit 1370 to output the fifth voltage or the sixth voltage. The determining circuit 1380 compares the fifth voltage with the first reference voltage. When it is determined that the fifth voltage is less than the first reference voltage, the first digital signal is output. When it is determined that the fifth voltage is greater than the first reference voltage, the second digital signal is output. Alternatively, the determining circuit 1380 compares the sixth voltage with the second reference voltage. When it is determined that the sixth voltage is less than the second reference voltage, the first digital signal is output. When it is determined that the sixth voltage is greater than the second reference voltage, the second digital signal is output. The control circuit 1390 may send the first signal to the correlated double sampling circuit 1370 based on the first digital signal. The correlated double sampling circuit 1370 outputs the second voltage signal when receiving the first signal, and the correlated double sampling circuit 1370 outputs the third voltage signal based on a fourth clock signal input by the clock generator 1400, and obtains the first analog signal by subtracting the third voltage signal from the second voltage signal. Alternatively, the control circuit 1390 may send the second signal and the third signal to the correlated double sampling circuit 1370 based on the second digital signal. The correlated double sampling circuit 1370 receives the fourth voltage signal when receiving the second signal, and outputs the first voltage signal when receiving the third signal. In this case, the correlated double sampling circuit 1370 outputs the fourth voltage signal based on a fifth clock signal sent by the clock generator 1400, and obtains the second analog signal by subtracting the fourth voltage signal from the first voltage signal.
In the foregoing implementation process, the first digital signal and the second digital signal may be stored into a memory coupled to the second output port 1360. The first output port 1350 may be coupled to an analog-to-digital converter (ADC), and the ADC may convert the first analog signal or the second analog signal into a digital signal for subsequent image processing.
In an implementation solution, the determining circuit 1380 includes a reference voltage input end and a comparator U1. An inverting input end of the comparator U1 is coupled to the output end of the correlated double sampling circuit 1370. A non-inverting input end of the comparator U1 is coupled to the reference voltage input end. An output end of the comparator U1 is separately coupled to the input end of the control circuit 1390 and the second output port 1360. In the foregoing manner, the determining circuit 1380 may compare an output voltage of the correlated double sampling circuit 1370 with a given reference voltage at the reference voltage input end, and output a corresponding comparison result.
It may be understood that the comparator U1 may use an independent comparator, or may reuse a comparator inside the analog-to-digital converter.
In an implementation solution, as shown in
Further, still as shown in
The second voltage receiving circuit 1372 includes a third transistor ΦRH, a fourth transistor Φ2, and a second capacitor CRH. A control electrode of the third transistor ΦRH is coupled to the clock generator 1400, and is configured to input the second clock signal. A first electrode of the third transistor ΦRH is coupled to the input port 1340. Both a second electrode of the third transistor ΦRH and a first end of the second capacitor CRH are coupled to a first electrode of the fourth transistor Φ2. A second end of the second capacitor CRH is grounded. A control electrode of the fourth transistor Φ2 is coupled to the control circuit 1390, and is configured to input the first signal. A second electrode of the fourth transistor Φ2 is coupled to the non-inverting input end of the subtractor 1374.
The third voltage receiving circuit 1373 includes a fifth transistor Φsig, a sixth transistor Φ3, a clock signal input port Ts, and a third capacitor Csig. A control electrode of the fifth transistor Φsig is separately coupled to the control circuit 1390 and the clock signal input port Ts, and is configured to input the second signal output by the control circuit 1390 or input the third clock signal input by the clock generator 1400 through the clock signal input port Ts. A first electrode of the fifth transistor Φsig is coupled to the input port 1340. Both a second electrode of the fifth transistor Φsig and a first end of the third capacitor Csig are coupled to a first electrode of the sixth transistor Φ3. A second end of the third capacitor Csig is grounded. A control electrode of the sixth transistor Φ3 is coupled to the clock generator 1400, and is configured to input the fourth clock signal or the fifth clock signal. A second electrode of the sixth transistor Φ3 is coupled to the inverting input end of the subtractor 1374.
Optionally, as shown in
In an implementation,
To facilitate understanding of the technical solutions of this application, in this embodiment of this application, a process of selecting a conversion gain mode of the image sensor circuit is briefly described by using the pixel array 1320 including pixel units in
With reference to
After the image sensor circuit is powered on, at a moment T1, the driver 1310 continuously outputs high levels to the RST, the TG, and the switch for double conversion gain (SDCG), to reset the FD, the PD, and the CS. Duration during which the driver 1310 continuously outputs the high levels to the RST, the TG, and the switch for double conversion gain (SDCG) may be set according to an actual reset requirement of a component.
After the reset ends, the driver 1310 continuously outputs low levels to the RST and the TG, so that the RST and the TG are cut off, an integration stage is entered, and the pixel unit starts to be exposed. At the same time, the switch for double conversion gain (SDCG) is still in an on state (that is, the pixel unit enters the LCG mode by default).
When a moment T2 is reached, the SDCG is still in the on state, and the clock generator 1400 outputs a high level to the first transistor ΦRL, so that the first transistor ΦRL is conducted, and the capacitor CRL, receives the first voltage signal VRL in the LCG mode. After a period of time, the driver 1310 outputs low levels to the first transistor ΦRL and the SDCG, so that the first transistor ΦRL is cut off and the switch for double conversion gain (SDCG) is turned off, and the pixel unit enters the HCG mode.
When a moment T3 is reached, the clock generator 1400 continuously outputs a high level to ΦRH for a period of time, so that ΦRH is conducted, and the capacitor CRH receives the second voltage signal VRH in the HCG mode; and then the clock generator 1400 continuously outputs a low level to ΦRH, so that ΦRH is cut off.
When a moment T4 is reached, the pixel unit is still in the HCG mode, and the driver 1310 continuously outputs a high level to the TG in the pixel unit for a period of time, so that the TG is conducted, and photo-generated electrons in the PD are transferred to the FD; and then the driver 1310 continuously outputs a low level to the TG, so that the TG is cut off.
When a moment T5 is reached, the control circuit 1390 continuously outputs a high level to ΦSig for a period of time, so that ΦSig is conducted, VSH is stored into Csig, and then a low level is continuously output to ΦSig.
When a moment T6 is reached, the clock generator 1400 continuously outputs a high level to Φ3 for a period of time, and outputs the third voltage signal received by Csig. At the same time, the control circuit 1390 continuously outputs a high level to Φ2 for a period of time, and outputs the second voltage signal received by CRH. The comparator compares a result Vout (namely, VRH−VSH) output by the subtractor with VREF. If VRH−VSH is less than VREF, there are fewer photo-generated electrons, and the HCG mode is more suitable for a present incident light intensity. In this case, a digital signal (DCGFlag) output from the second output port in the HCG mode is set to a logic level “0”, and is sent to the memory.
When a moment T7 is reached, the driver 1310 continuously outputs a high level to the SDCG, and the pixel unit is switched to the LCG mode. At the same time, the driver 1310 outputs a high level to the TG for a period of time; and after the photo-generated electrons in the PD are transferred to the FD, the driver 1310 continuously outputs a low level to the TG, so that the TG is cut off.
When a moment T8 is reached, the control circuit 1390 continuously outputs a low level to ΦSig, so that ΦSig is cut off, to prevent the voltage VSH that has been stored into Csig from being changed.
When a moment T9 is reached, the driver 1310 continuously outputs a low level to the SDCG.
When a moment T10 is reached, the clock generator 1400 continuously outputs a high level to Φ3 for a period of time, and outputs the second voltage signal VRH received by Csig. At the same time, the control circuit continuously outputs a high level to Φ2 for a period of time, and outputs the third voltage signal VSH received by CRH. After the second voltage signal VRH and the third voltage signal VSH are processed by the subtractor 1374, a result Vout (namely, VRH−VSH) is output from the first output port.
As shown in
When a moment T7 is reached, the driver 1310 continuously outputs a high level to the SDCG, and the pixel unit is switched to the LCG mode. At the same time, the driver 1310 outputs a high level to the TG for a period of time; and after the photo-generating electrons in the PD are transferred to the FD, the driver 1310 continuously outputs a low level to the TG, so that the TG is cut off.
When a moment T8 is reached, the control circuit outputs a high level to ΦSig for a period of time, so that ΦSig is conducted, and the fourth voltage signal VSL is stored into Csig.
When a moment T9 is reached, the driver 1310 continuously outputs a low level to the SDCG.
When a moment T10 is reached, the clock generator 1400 continuously outputs a high level to Φ3 for a period of time, and outputs the fourth voltage signal VSL received by Csig. At the same time, the control circuit continuously outputs a high level to Φ1 for a period of time, and outputs the first voltage signal received by CRL. After the first voltage signal and the fourth voltage signal are processed by the subtractor 1374, a result Vout (namely, VRL−VSL) is output from the first output port.
In the foregoing implementation process, a step performed at the moment T6 may still be performed at the moment T5. It may be understood that the memory may be a volatile memory or a non-volatile memory, or may include both a volatile memory and a non-volatile memory. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM) and is used as an external cache. Through an example rather than a limitative description, random access memories (RAMs) in many forms may be used, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous coupled dynamic random access memory (SLDRAM), and a direct rambus random access memory (DR RAM).
In an implementation solution, an embodiment of this application further provides an image sensor chip. The image sensor chip includes any one of the foregoing image sensor circuits packaged in a package structure.
An embodiment of this application further provides a camera device. The camera device includes the image sensor chip.
The foregoing descriptions about implementations allow a person skilled in the art to understand that, for the purpose of convenient and brief description, division into the foregoing functional modules is only taken as an example for illustration. During actual application, the foregoing functions can be allocated to different functional modules and implemented according to a requirement, that is, an inner structure of an apparatus is divided into different functional modules to implement all or some of the functions described above.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the described apparatus embodiment is merely an example. For example, division into the modules or the units is merely logical function division and may be other division during actual implementation. For example, a plurality of units or components may be combined or integrated into another apparatus, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication couplings may be implemented through some interfaces. The indirect couplings or communication couplings between the apparatuses or units may be implemented in electronic, mechanical, or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may be one or more physical units, may be located in one place, or may be distributed in different places. Some or all of the units may be selected according to an actual requirement to achieve the objectives of solutions of embodiments.
In addition, functional modules in embodiments of this application may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in a form of hardware, or may be implemented in a form of a software functional unit.
The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Any variation or replacement within the technical scope disclosed in this application shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211204098.3 | Sep 2022 | CN | national |
This application is a continuation of International Application No. PCT/CN2023/099536, filed on Jun. 9, 2023, which claims priority to Chinese Patent Application No. 202211204098.3, filed on Sep. 29, 2022. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2023/099536 | Jun 2023 | WO |
| Child | 19092992 | US |
