CROSS REFERENCE TO RELATED APPLICATIONS
The instant disclosure is related to a co-pending application having attorney docket number 41369.00.0026, filed on even date herewith.
FIELD OF THE INVENTION
The present invention relates to the field of integrated images sensors and, more specifically, to the field of sensors enabling a fine detection under a low light.
DISCUSSION OF PRIOR ART
Many integrated image capture devices are known. The most current structure of such sensors comprises a plurality of elementary detection devices or pixels, each comprising a photodiode formed in a semiconductor substrate, associated with a charge transfer device and with a circuit for reading the charges which have been transferred. It is generally desired to minimize the number of sensor elements by using one read circuit for several photodiodes.
When an image sensor receives a light beam, the incident photons penetrate into the semiconductor substrate and form electron/hole pairs in this substrate. The electrons of these pairs are then captured by the photodiode, and transferred by the charge transfer transistor towards the associated read circuit.
US patent application 2007/0176216 describes a structure comprising, in addition to the above-mentioned elements, devices, associated with each pixel, enabling to amplify the electrons photogenerated in this pixel to improve the sensitivity of the sensors. To perform this amplification or charge multiplication, it is known to use techniques associated with CCD (charge coupled device) registers, that is, to form, at the substrate surface, an assembly of alternately biased metal gates. Such an alternated biasing of the gates enables, by so-called electronic avalanche effect, to multiply the photogenerated electrons.
FIG. 1 illustrates a pixel of an image sensor comprising a charge multiplication stage and FIGS. 2A to 2E are voltage curves illustrating the operation of this pixel in different steps of the detection.
The pixel of FIG. 1 is formed inside and on top of a P-type substrate 10 biased to a reference voltage, for example, the ground. In substrate 10, at the surface thereof, is formed a photodiode formed of a heavily-doped N-type region 12 (N+). The photodiode is illuminated by a light beam 13. An insulated transfer gate 14 controlled by a transfer signal VT is placed in the vicinity of the photodiode. Several insulated gates enabling to multiply the charges by avalanche effect are formed next to transfer gate 14. In the shown example, four gates 16, 18, 20, 22 are respectively controlled by control signals Φ1, Φ2, Φ3, and Φ4. The representation of FIG. 1 is extremely simplified; in particular, it should be noted that in a real device, the most part of the surface of each pixel is assigned to the photodiode.
FIGS. 2A to 2E illustrate the voltage in substrate 10, in the plane of FIG. 1, in different steps of the image capture. In these drawings, a single electron storage, transfer, and multiplication cycle is described. The voltage illustrated in each of the drawings is the voltage in substrate 10, following a line which will be called “maximum potential line” hereinafter. This line runs, in depth in the substrate, through the points of highest biasing in front of the insulated gates and in the photodiode. It should be noted that, according to the voltage applied on the different insulated gates, the maximum biasing line runs through points of variable depth in the substrate. It should be noted that, in the following description, gate 16 will be called “multiplication gate” although this gate also plays a role in the initial transfer step.
FIG. 2A shows the curve of the voltage in photodiode 12 and in substrate 10, in an initial phase of charge storage in photodiode 12. The illumination of the sensor of FIG. 1 causes the storage of electrons in region 12 and the voltage of this region, initially equal to V1, decreases to reach a value V2 which is a function of the number of stored electrons and thus of the number of incident photons. During the storage phase, voltage VT applied to the transfer gate is zero to form a potential wall and avoid for electrons to come out from photodiode 12. Voltage Φ1, associated with first charge multiplication gate 16 is, preferably just before the transfer step V3, greater than V1, in anticipation of the next step.
At the step of FIG. 2B, a transfer voltage VT, substantially equal to or slightly greater than V1, is applied to transfer gate 14, while voltage Φ1 applied to first charge multiplication gate 16 is equal to V3 (greater than V1) and voltage 12 applied to second multiplication gate 18 is zero. The charges stored in photodiode 12 are thus transferred into the potential well formed, in substrate 10, under first multiplication gate 16.
At the step of FIG. 2C, voltage VT (transfer gate) returns to a reference voltage while voltage Φ2 remains at this reference voltage, for example, equal to zero, which blocks the electrons in substrate region 10 located under gate 16. A new charge storage phase can then start at the level of photodiode 12.
At the step illustrated in FIG. 2D, voltage Φ1 applied to gate 16 is decreased to a low voltage V4. The voltage of substrate 10 located under gate 16 is thus lowered. During this step, voltages VT and Φ2 respectively applied to gates 14 and 18 are zero (reference voltage). Preferably, just before the next step, voltage Φ3 applied to gate 20 is set to a voltage V5 much greater than voltage V4, in anticipation of the next step.
At the step illustrated in FIG. 2E, voltage Φ2 applied to gate 18 increases fast to be on the order of voltage V4, or slightly greater than V4. Voltage Φ3 being equal to V5 (much greater than V4), the charges are transferred to the substrate region located under gate 20. The voltage difference between the region located under gate 18 (□ V4) and under gate 20 (V5) is sufficiently high to enable to multiply the charges by electronic avalanche effect. During this step, gate 22 is biased to a zero voltage to form a potential wall and to block the charges at the level of gate 20. As an example, voltage V4 may be on the order of 1 V and voltage V5 may be on the order of 10 V. It should be noted that the charge transfer step (FIG. 2B) may also take part in the charge amplification, the voltage applied to gate 16 during this step being then capable of causing a multiplication (high voltage).
For the charge multiplication by avalanche effect to be significant, the steps of FIGS. 2D and 2E are repeated several times. For this purpose, back and forth transfers are performed at the level of gates 14, 16, 18, 20, and 22, which enables to limit the number of gates to be formed.
A problem arises if the device remains under a very low lighting level for a long time, for example in the case where the image sensor is intended to detect images in a dark environment (for example, nocturnal images). In this case, it will be shown that the charge transfer during the step of FIG. 2B may be incomplete or be distorted. The signal originating from the sensor then has very degraded performances, especially in terms of signal-to-noise ratio.
Thus, a device enabling to detect and to transmit a high-quality signal, even under a low lighting, is needed.
SUMMARY
An object of an embodiment of the present invention is to provide an image sensor providing a good detection under a low lighting.
Thus, an embodiment of the present invention provides an elementary device of an image sensor, comprising a charge photogeneration and collection region formed at the surface of a semiconductor substrate of a first conductivity type capable of being biased to a reference voltage, the photogeneration region being associated with a charge transfer, multiplication, and insulation device. The photogeneration region is topped with an insulated gate capable of being alternately biased to a first voltage and to a second voltage, the insulated gate being made of a low-absorption material.
According to an embodiment of the present invention, the transfer device comprises an insulated transfer gate capable of being biased to a fixed voltage and the first voltage is greater, in absolute value, than the fixed voltage to enable the charge collection and the second voltage is smaller, in absolute value, than the fixed voltage to enable a transfer of the built-up charges.
According to an embodiment of the present invention, the charge multiplication and insulation device is formed of a plurality of insulated gates capable of being biased to set the voltage of the underlying substrate and to enable the charge transfer and their multiplication by electronic avalanche effect.
According to an embodiment of the present invention, the charge transfer, multiplication, and insulation device comprises at least five insulated gates.
According to an embodiment of the present invention, the reference voltage is the ground.
According to an embodiment of the present invention, the first conductivity type is type P.
According to an embodiment of the present invention, the device further comprises an optical mask formed on the charge transfer, multiplication, and insulation device.
According to an embodiment of the present invention, the substrate is thinned and is intended to be illuminated from the surface opposite to that on which the charge transfer, multiplication, and insulation device is formed.
The present invention also provides an image sensor comprising a plurality of elementary devices such as mentioned hereabove.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, among which:
FIG. 1, previously described, illustrates a conventional charge amplification image sensor;
FIGS. 2A to 2E are voltage curves illustrating the operation of the device of FIG. 1 when it is submitted to a significant lighting;
FIG. 3 shows the structure of FIG. 1 and FIGS. 4A to 4C are voltage curves illustrating an issue that may arise in this structure in the absence of any light or under a very low light;
FIG. 5 illustrates an image sensor according to an embodiment of the present invention; and
FIGS. 6A and 6B are voltage curves illustrating the operation of the device of FIG. 5; and
FIG. 7 illustrates a variation of a device according to an embodiment of the present invention.
For clarity, the same elements have been designated with the same reference numerals in the different drawings and, further, as usual in the representation of integrated circuits, the various drawings are not to scale.
DETAILED DESCRIPTION
FIG. 3 shows the structure of FIG. 1, in the case of a quasi absent lighting (no light beam 13). The device comprises a photodiode 12 formed of a heavily-doped N-type region (N+) formed at the surface of a P-type substrate 10, an insulated transfer gate 14 formed at the surface of substrate 10 and controlled by a transfer signal VT and insulated charge multiplication gates 16, 18, 20, 22 respectively controlled by signals Φ1, Φ2, Φ3, Φ4.
FIGS. 4A to 4C are voltage curves in substrate 10, following the maximum potential lines, during different operating steps of the device of FIG. 3.
FIG. 4A illustrates the voltage in substrate 10 during a succession of charge storage and transfer steps (with voltage VT of gate 14 varying between zero and V1). When the photodiode is not illuminated, no electron/hole pair is created and the photodiode voltage should theoretically remain constant. However, it can be observed that said voltage increases progressively along storage/transfer cycles, to reach, in the shown example, a voltage V1′ (FIG. 4B).
The voltage increase in the photodiode, in a succession of cycles under no or very low light, is due to a leakage current between heavily-doped N-type photodiode 12 and the substrate located in front of gate 16. During transfer phases (VT=V1), the voltages of the photodiode and of the channel located under gate 14 are very close and the charges of region 12 leak, through the channel located under gate 14, towards the potential well formed under gate 16, according to a low-inversion current law expressed in exp(−qV/kT), q being the elementary charge, V being the potential difference between gate 14 and photodiode 12, k being Boltzmann's constant, and T being the temperature. Thus the voltage of region 12 becomes greater than the facing voltage of gate 14. It should be noted that, in case of a significant lighting, this issue does not arise since the leakage current is then negligible as compared with the current resulting from the lighting. However, at a low lighting level, this phenomenon disturbs the charge injection into the multiplication stage, thus making this stage useless in the most critical cases where it should play an essential role.
Once voltage V1′ has been reached, if there is a low lighting and a small amount of electrons is stored in photodiode 12 (FIG. 4C), the charge reading efficiency will be very poor, a small amount of electrons succeeding in passing the potential barrier formed by the region located under gate 14 in a transfer. Indeed, since the voltage in the photodiode has varied from V1 to V1′, one has V1′>VT during the transfer, which forms a potential wall preventing any transfer of the electrons stored in the photodiode or only enabling a partial transfer thereof. Further, if a sufficient amount of electrons for the transfer is stored in photodiode 12, the transfer is distorted due to the voltage variation during the period when photodiode is not illuminated (less charges than there where really stored in photodiode 12 are transferred).
Thus, in the case of a very low or of no lighting, the charge reading performed by the device of FIG. 3 is not good.
To solve this problem, the inventors provide forming an insulated gate above a substrate and applying a voltage on this gate to create a space charge in the substrate and collect electrons from the electron/hole pairs photogenerated in this region.
FIG. 5 illustrates such a device. The device comprises a substrate 30, for example of type P, biased to a reference voltage (for example, the ground) from its rear surface. On this substrate is formed an insulated gate 32, controlled by a signal Va. Gate 32 will be called “build-up gate” hereafter. Gate 32 is little absorbing, for example transparent, so that a light beam 34 reaching the substrate surface crosses gate 32 and penetrates into substrate 30 to form electron/hole pairs therein. Next to build-up gate 32, at the surface of substrate 30, are formed an insulated gate 36, charge multiplication gates 38, 40, 42, and a charge insulation gate 44. Gates 36, 38, 40, 42, 44 are insulated gates and are respectively controllable by control signals VT, Φ1, Φ2, Φ3, Φ4. Conversely to what is shown in FIG. 5, in a real device, the most part of the surface of each pixel is assigned to build-up gate 32, which forms the detection area of the device. Preferably, a protection layer (not shown), or optical mask, is provided above transfer gate 36, amplification gates 38, 40, 42, and insulation gate 44, so that incident light beams generate no charges in the substrate located under these gates.
FIG. 6A is a curve of the voltage in substrate 30 of FIG. 5, following a maximum potential line, in a charge build-up phase, before the charge injection into the multiplication stage.
During the detection phase, voltage VT applied to transfer gate 36 is equal to a fixed voltage V1 and voltage Va applied to build-up gate 32 is equal to a voltage Va1 greater than voltage V1. A potential well is thus formed under build-up gate 32. When electron/hole pairs are photogenerated in substrate 30, the electrons are collected in substrate 30 by build-up gate 32. Thus, the surface potential under gate 32 decreases proportionally to the number of photogenerated electrons, to reach a voltage Va2. It should be noted that voltage V1 is provided to be sufficiently low to be smaller than Va2, so that electrons build up under gate 32.
When the multiplication stage is empty, a low voltage, close to zero, is preferably applied to gates 38, 40, and 42, to minimize the direct collection of free carriers by the multiplication stage.
Before the charge injection into the multiplication stage, the situation is such as shown in FIG. 6A, the voltage applied to gate 38 being high, at a voltage V2, and the voltage applied to gate 40 being at a low level, close to zero. Voltage V2 is greater than V1 to enable the reception of the charges during the injection.
FIG. 6B is a curve of the voltage in substrate 30 of FIG. 4, following a maximum potential line, during a charge transfer phase. Voltage Va applied to build-up gate 32 passes to a voltage Va3, smaller than V1. This enables to transfer charges built up at the surface of substrate 30 under gate 32 towards the potential well formed, at the surface of this substrate, under first multiplication gate 38. During the charge transfer, the reference voltage (close to zero) applied to gate 40 enables to avoid for the transferred charges to come out of the potential well formed under gate 38.
Since the voltage of gate 32 is alternately imposed to Va1 and to Va3, the above-mentioned problems of potential increase at the surface of substrate 30 under gate 32 under a low light are avoided. A full transfer of the charges into the multiplication stage is thus obtained. Thus, the provided device is efficient even in case of no or of very low light.
Optionally, a thin N-type doped layer 46 may be formed at the surface of substrate 30, in front of build-up gate 32, of transfer gate 36, of multiplication gates 38, 40, 42, and of insulation gate 44. Thin layer 46 enables to slightly move the maximum voltage point away from the substrate surface to avoid parasitic phenomena (noise) often present at the interfaces between the gate insulator and the semiconductor substrate.
Once the electrons have been transferred from gate 32 to gate 38, a charge amplification cycle is conventionally performed. For this purpose, advantage may be taken from the electronic avalanche effect by forcing the charges to travel back and forth under gates 38, 40, and 42 to obtain a significant amplification. The amplification is adjusted by controlling the number of back and forth travels. Transfer gate 36 and insulation gate 44 are then used as potential walls to avoid for charges to come out of the device during the charge amplification. Gates 38 and 42 are alternately biased to distant voltages to enable an amplification by electronic avalanche effect. It should be noted that the charge transfer and amplification device may also be formed by combining more than five neighboring gates in adapted fashion.
FIG. 7 illustrates a variation of the device of FIG. 5 wherein the image sensor is illuminated from the back side of substrate 30. The device of FIG. 7 differs from that of FIG. 5 in that substrate 30 is thinned and is illuminated from the surface opposite to that on which build-up gate 32, transfer gate 36, charge multiplication gates 38, 40, 42, and insulation gate 44 are formed. During the build-up phase, a light beam 46 reaching the substrate generates electron/hole pairs therein and the electrons of these pairs are collected in the potential well formed under gate 32. Advantageously and conventionally, a beam arriving from the back side of a substrate comes across fewer obstacles and is more easily detectable than a beam arriving on the front surface of the substrate. The operation of this device is then similar to that described in relation with FIGS. 6A and 6B.
Specific embodiments of the present invention have been described. Various alterations and modifications will occur to those skilled in the art. In particular, it should be noted that the reference voltage applied to P-type substrate 30 may be different from ground. Further, although a device where the useful photogenerated charges are electrons has been described herein, it should be noted that similar devices where the useful charges are holes may also be provided. To achieve this, substrate 30 will be N-type doped and the voltages applied to the different gates for the transfers will be of a sign opposite to those discussed herein (the absolute values of the different voltages applied to the different insulated gates being by same ratios than those discussed in relation with FIGS. 6A and 6B).
The devices of FIGS. 5 and 7 may also be used in the case of strong lighting levels. In this case, it may be provided to adapt the integration or charge build-up time in the build-up area according to the lighting, by means of an adapted electronic circuit, to avoid the pixel saturation.
Patent Application
20120112247
