Patent Application
20150200229
1. Field
The present disclosure relates generally to an image sensor, and more particularly, to an image sensor having a pixel with multilevel transfer gate.
2. Background
In recent years, CMOS image sensor (CIS) technology is gaining in popularity over charged coupled device (CCD). Starting with mobile devices, CIS offers lower cost because it can be manufactured using a standard CMOS process. CCD requires a specialized process. Moreover, CIS allows for more function integration, due to the use of the standard CMOS process. For example, each CIS pixel includes a buffer, which may improve the performance of the CIS over the CCD. Recently, CIS is starting to be adopted for broadcasting systems.
CIS is an example of active matrix sensor. In a pixel of a CIS, a photodiode generates electrical charges. An example of the photodiode is a p-n junction diode. In one implementation, the photodiode generates hole-electron pairs. The electrons are accumulated or integrated in the p-diffusion region of the photodiode. After an integration period, the charges accumulated are transferred to a floating diffusion via a transfer gate. In other words, the floating diffusion (C) generates a voltage (dV) from the accumulated charges (dQ) or dV=dQ/C and is coupled to the output line. In one aspect, the floating diffusion functions as a storage element. The voltage on the floating diffusion is coupled to an output line via a buffer.
In another aspect, the CIS includes an array (rows and columns) of the described pixels. In one implementation, the output lines may function as the column lines of the array. The pixels are coupled to the output lines by the rows sequentially. An output circuit coupled to the output lines performs further determining functions. For example, the output circuit may include an integrator that integrates the voltage of an output line, an operational amplifier, or an analog-to-digital converter that convert the integrated voltage to a digital value.
In another aspect, the CIS may include electronic shutter function. In one example, the shutter resets the charge integration in a group of pixels. An example is a global shutter which resets all the pixels in the CIS. The examples given are based on using the electrons to generate the wanted signal. The holes are drained off in this case. The mechanism works equally well for holes except that voltage changes reverses. Now the holes generate the wanted signal and the electrons are drained off.
In an aspect of the disclosure, an image sensor and a method for operating an image sensor are provided. In one aspect, the image sensor includes a pixel with multilevel transfer gate. The image sensor includes a pixel coupled to an output line. The pixel includes a photodiode configured to generate electrical charges in response to light. The pixel also includes a capacitive element for storing electrical charges for providing a value to the output line. A transfer gate is coupled between the photodiode and the capacitive element. The transfer gate is configured to activate to transfer the electrical charges between the photodiode and the capacitive element. The image sensor is configured to provide at least one control signal operating in a plurality of voltages to the transfer gate. The plurality of voltages is in addition to a voltage which deactivates the transfer gate.
In another aspect, the image sensor further includes a control circuit for providing the at least one control signal to the transfer gate. The control circuit includes a multiplexer configured to selectively couple at least one of the plurality of voltages onto the control signal.
In another aspect, the transfer gate includes a metal-oxide-semiconductor (MOS) transistor, and a gate of the MOS transistor is coupled to the control signal.
In another aspect, the plurality of voltages includes a voltage which activates the transfer gate to transfer the electrical charges between the photodiode and the capacitive element.
In another aspect, the plurality of voltages further includes a second voltage between the voltage which activates the transfer gate and the voltage which deactivates the transfer gate. In yet another aspect, the second voltage is provided prior to providing the voltage which activates the transfer gate to the at least one control signal of the transfer gate in a cycle.
In another aspect, the plurality of voltages further includes a third voltage between the voltage which activates the transfer gate and voltage which deactivates the transfer gate. In yet another aspect, the third voltage is provided after providing the voltage which activates the transfer gate to the at least one control signal of the transfer gate in the cycle.
In another aspect, the second voltage is provided after providing the voltage which activates the transfer gate to the at least one control signal of the transfer gate in a cycle.
It is understood that other aspects of apparatus and methods will become readily apparent to those skilled in the art from the following detailed description, wherein various aspects of apparatus and methods are shown and described by way of illustration. As will be realized, these aspects may be implemented in other and different forms and its several details are capable of modification in various other respects. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.
The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
Several aspects of the image sensor will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.
In one implementation, a shutter circuit 130 may perform the shutter function by, e.g., controlling the integration time of the pixel 100. In one example, the integration time may be controlled by the shutter circuit 130 resetting the charge generating circuit 102 according to a predetermined timing. Such predetermined timing may correspond to the integration time. In one example, the shutter circuit 130 may be part of a global shutter function. I.e., all pixels in an array may be controlled by the same shutter timing.
Pixel 150 is another view of an image sensor pixel. In one implementation, a photodiode 152 may generate electrical charges (e.g., electrons) in response to light. In one example, the photodiode 152 may be a pinned photodiode completely depleted and pinned to a voltage potential (known as Vpin) before any charges are generated. The electrical charges may be accumulated or integrated at node PD (which may be, e.g., a node in the photodiode 152) in an integration period. After the integration period, the charges accumulated at node PD may be transferred to a floating diffusion 156 via a transfer gate 154. In one aspect, the accumulated charges at node PD may be coupled to the floating diffusion 156 generating a voltage.
In one aspect, the floating diffusion 156 may function as a storage element for storing the generated charges for outputting a value to the output line 110. In one example where the accumulated charges are electrons, the floating diffusion 156 may be an N-type diffusion that is floating (i.e., not directly tied to any voltage potential). The transfer gate 154 may be a metal-oxide-semiconductor field-effect transistor (MOSFET) device controlled by a TG control signal 153. For example, the TG control signal 153 may be connected to the gate of the transfer gate 154.
The voltage on the floating diffusion 156 may be coupled to an output line 160 via a MOSFET 158 and a MOSFET 172. In example, the MOSFET 158 may be connected to voltage potential VDDPIX and may perform the buffer function on the voltage of the floating diffusion 156. The MOSFET 172 may selectively provide the output of the MOSFET 158 to the output line 160. In one aspect, the MOSFET 172 may be controlled by a SEL signal, and the SEL signal may correspond to a row activation of the pixel array. The reset circuit 170 may reset the voltage on the floating diffusion 156 by, e.g., supplying VDDPIX to the floating diffusion 156.
In one implementation, a MOSFET 180 may perform the shutter function by, e.g., controlling the integration time of the pixel 150. In one example, the integration time is controlled by the MOSFET 180 resetting the voltage on the node PD (which may be, e.g., a node in the photodiode 152) according to predetermined timing. Such predetermined timing may correspond to the integration time. In one example, the MOSFET 180 may be part of a global shutter function. I.e., all pixels in an array may be controlled by the same shutter timing. In one example, the resetting may include the MOSFET 180 functioning as a supply circuit supplying, in a first charge holding capacity, a reset voltage to the node PD. The supply voltages to the drain of MOSFET 180 and/or 170 may be different from MOSFET 158. A control signal, shutter control 182, may be supplied to the gate of the MOSFET 180 to control the drain capacity of the MOSFET 180. In one aspect, the control signal (shutter control 182) may operate at a high voltage level to enable the MOSFET 180 to drain the electrons from the photodiode 152, at a first capacity. In another aspect, the control signal (shutter control 182) may be at a low voltage level, to turn the MOSFET 180 off and not draining any electrons from the photodiode 152.
Acquisition of an image takes for 20 ms for 50 Hz systems. During these 20 ms, dark current may be generated within the pixel. In one aspect, dark current is the small electric current that flows through photosensitive devices such as a photodiode or CCD, even when no photons are entering the device. The dark current may be due to the random generation of electrons and holes within the depletion region of the device that are then swept by the high electric field. To minimize dark current, the TG control signal 153 may be switched low.
In one aspect, charges, such as holes, may accumulate in the transfer gate channel before the transfer (i.e., before the transfer gate 154 is turned on for the transfer). The TG control signal 153 going low or even negative may minimize dark current, but may lead to hole accumulation in the transfer gate channel.
In another aspect, during the opening of the transfer gate channel, the photo-generated charges recombine, and electrons may be in surface traps. When the transfer gate channel is closed, charge (such as the electrons) might be captured in potential pockets and traps. In one example, charges may remain under the transfer gate channel after the transfer gate 154 is turned off after the transfer. The charges remaining in the transfer channel may be read out in a subsequent transfer. However, when applying exposure time control such as the global shutter, these charges may be reset and lost. A loss of picture quality (e.g., in darker areas) may result. In one aspect, the relationship of an image and a generated, corresponding photo-current of a pixel may become non-linear.
In one aspect of a pixel with multilevel transfer gate, the multilevel transfer gate may receive a control signal at a voltage prior that generate charges in the transfer gate channel, before the transfer. The control signal voltage may be slightly above the ground level and may have an effect of generating electrons in the transfer gate channel, causing the trapped holes to recombine with the electrons before the transfer. In another aspect of a pixel with multilevel transfer gate, the multilevel transfer gate may receive the control signal at a different voltage after the transfer. The different control signal voltage may be lower than the activation voltage of the transfer gate and may have an effect of allowing a more complete transfer of the charges (e.g., less charges trapped remain in the transfer gate channel after the transfer).
In one aspect, the control circuit includes multiplexers 392 and 394 and provides a plurality of voltage to the TG control signal 353 controlling the transfer gate 354. In one example, the plurality of voltages of the TG control signal 353 may include a TG high voltage level (at 396) which activates the transfer gate 354 for transferring charges between the photodiode 352 and the floating diffusion 356. In one example, TG high may be between 3.3-4.5 volt.
In one example, the second multiplexer 394 selects from a voltage level TG low #1 (at 398), a voltage level TG low #2 (at 399), and a voltage level TG low #2 (at 399), and a voltage level TG low #3 (at 397), and output the selected voltage to TG low′. In one example, the voltage level TG low #3 may be a small positive or a ground level. In another example, the voltage level TG low #3 may be a level below ground or a negative voltage for minimizing the dark current. In one example, TG low #3 may be between −0.5-1.0 volt. The control signal TGLS controls the selection. In one example, TGLS includes a plurality of signals for selecting from the three inputs (in this example, TGLS may include two signals). As is known in the art, when the ground level or below (e.g., TG low #3) is provided to the TG control signal 353, the transfer gate 354 may be shut off.
In another example, the first multiplexer 392 selects from TG high (at 396) and the TG low′, and provides the selected voltage to the TG control signal 353. Thus, in one example, a plurality of voltages including TG high, TG low #1, TG low #2, and TG low #3 may be provided to the TG control signal 353. Selectively providing additional voltages to the TG control signal 353 is possible.
At T1, TGLS 395 goes to state 1, which selects TG low #1 (398). As shown in
At T2, the TG global 393 goes high, and voltage level TG high is provided to the TG control 353. As a result, transfer gate 354 is activated (the charge transfer period starts), and charges/voltage on the node PD is transferred to the floating diffusion 356. The period between T2 and T3 is the charge transfer period.
At T3, the TG global 393 goes low (the charge transfer period ends), and the TGLS 395 switches to state 2, which selects TG low #2 (399). Accordingly, the voltage level TG low #2 is provided to the TG control 353. In one example, the voltage level TG low #2 is an intermediate level between TG high and the TG low #3 (e.g., the voltage which deactivates the transfer gate 354). In another example, the voltage level TG low #2 is between TG high and photodiode pin voltage Vpin. In one example, TG low #2 may be between −0.5-3.0 volt. Accordingly, the TG control 353 does not drop to the ground level quickly, and the charge transfer period does not end abruptly. In one aspect, the voltage level TG low #2 on the TG control 353 may have an effect of allowing a more complete transfer of the charges into the floating diffusion 356 (e.g., less charges remain trapped in the transfer gate channel after the transfer).
At T4, TGLS switches back to state 3 and selects the TG low #3 (the ground level to below) the TG low.′ TG global 393 is also low, selecting and proving the ground level or below at the TG low′ to the TG control 353. Therefore, the transfer gate 354 is gradually shut off.
At T3, the current integration cycle ends, and at T5 a new integration cycle may begin. The shutter control activates to resets, e.g., the photodiode 352. Effects flowing from the above described operations may include reduction of charges trapped in the transfer gate channel before and after the transfer of charges to the floating diffusion, and improved linearity between the image and the generated photo-current.
Diagram 710 is a potential diagram of a state before the transfer cycle and TG low #1 being provided to the TG control 353 (e.g., the period before T1 and T2 in
Diagram 720 is a potential diagram of the charge transfer period (e.g., the period before T2 and T3 in
Diagram 730 is a potential diagram of a state after the charge transfer period and TG low #2 being provided to the TG control 353 (e.g., the period before T3 and T4 in
At 880, in another aspect, the second voltage may be provided after providing the voltage which activates the transfer gate to the at least one control signal of the transfer gate before a reset of the photodiode. The disclosed operations of the flowchart may be in accordance of the operation described with
It is understood that the specific order or hierarchy of steps in the processes/flow charts disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes/flow charts may be rearranged. Further, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.” Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”
