Patent Application
20230290795
This application claims the priority benefit of Korean Patent Application No. 10-2022-0029487, filed on Mar. 8, 2022, and all the benefits accruing therefrom under 35 U.S.C. ยง 119, the contents of which are incorporated by reference in their entirety.
The present disclosure relates to an image sensor. More specifically, the present disclosure relates to an image sensor including a photodiode and a charge storage region formed in a substrate.
In general, an image sensor is a semiconductor device that converts an optical image into electrical signals and may be classified or categorized as a Charge Coupled Device (CCD) or a Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS). The CIS may include unit pixels, each including a photodiode and MOS transistors. The CIS sequentially detects the electrical signals of the unit pixels using a switching method, thereby forming an image.
The photodiode may include a charge accumulation region in which charges generated by the incident light are accumulated. For example, the photodiode may include an N-type impurity region in which electrons are accumulated, and a P-type impurity region serving as a pinning region for reducing dark current may be formed on the N-type impurity region.
As an example, the image sensor may include a transfer gate electrode formed on a substrate, and the electrons may be transferred from the charge accumulation region to a charge detection region, for example, a floating diffusion region, through a channel region below the transfer gate electrode. As another example, an image sensor using a global shutter method may include a charge storage region for storing the electrons between the charge accumulation region and the floating diffusion region. In such case, transfer gate electrodes may be formed on surface portions of the substrate among the charge accumulation region, the charge storage region and the floating diffusion region.
However, when light enters the charge storage region or a region below the charge storage region, electrons may be generated in the charge storage region or below the charge storage region. In particular, when the electrons generated below the charge storage region move to the charge storage region, operating characteristics of the image sensor may be deteriorated by the electrons.
The present disclosure provides an image sensor capable of inhibiting charges generated below a charge storage region from moving to the charge storage region.
In accordance with an aspect of the present disclosure, an image sensor may include a charge accumulation region having a first conductivity type and disposed in a substrate, a charge storage region having the first conductivity type and disposed in the substrate to be laterally spaced apart from the charge accumulation region, a transfer gate electrode disposed on a channel region between the charge accumulation region and the charge storage region to transfer a charge from the charge accumulation region to the charge storage region, a first well region having a second conductivity type and disposed below the charge storage region to inhibit a charge generated below the charge storage region from being moved to the charge storage region, and a second well region having the second conductivity type and disposed below a portion of one side of the first well region adjacent to a neighboring image cell.
In accordance with some embodiments of the present disclosure, the second well region may have an impurity concentration lower than that of the first well region.
In accordance with some embodiments of the present disclosure, the substrate may have the second conductivity type and may have an impurity concentration lower than that of the second well region.
In accordance with some embodiments of the present disclosure, the image sensor may further include a third well region having the first conductivity type and disposed below the first well region.
In accordance with some embodiments of the present disclosure, the third well region may be electrically connected to the charge accumulation region.
In accordance with some embodiments of the present disclosure, the third well region may have an impurity concentration lower than that of the charge accumulation region.
In accordance with some embodiments of the present disclosure, the image sensor may further include a first dummy pattern disposed on a surface portion of the substrate between the charge storage region and a charge accumulation region of the neighboring image cell and configured to inhibit light from entering the charge storage region from the neighboring image cell.
In accordance with some embodiments of the present disclosure, the first dummy pattern may be made of a same material as the transfer gate electrode.
In accordance with some embodiments of the present disclosure, the image sensor may further include an insulating layer disposed on the substrate, the transfer gate electrode and the first dummy pattern, and a light shield layer disposed on the insulating layer and configured to inhibit light from entering the charge storage region.
In accordance with some embodiments of the present disclosure, the image sensor may further include a first light shield pattern disposed between the first dummy pattern and the light shield layer and configured to pass through the insulating layer.
In accordance with some embodiments of the present disclosure, the image sensor may further include a second light shield pattern extending from a first edge portion of the light shield layer adjacent to the neighboring image cell toward the substrate.
In accordance with some embodiments of the present disclosure, the image sensor may further include a third light shield pattern extending from a second edge portion of the light shield layer adjacent to the charge accumulation region toward the substrate.
In accordance with some embodiments of the present disclosure, the image sensor may further include a second insulating layer disposed on the insulating layer and the light shield layer, interlayer insulating layers disposed on the second insulating layer, metal wiring layers disposed among the interlayer insulating layers, and a light guide pattern configured to pass through the interlayer insulating layers and to correspond to the charge accumulation region.
In accordance with some embodiments of the present disclosure, the image sensor may further include a cell isolation region disposed in the surface portion of the substrate between the charge storage region and the charge accumulation region of the neighboring image cell. In such case, the first dummy pattern may be disposed on the cell isolation region.
In accordance with some embodiments of the present disclosure, the image sensor may further include a second dummy pattern disposed on the charge storage region and configured to inhibit light from entering the charge storage region, and an insulating layer disposed between the charge storage region and the second dummy pattern and configured to electrically insulate the charge storage region from the second dummy pattern.
In accordance with another aspect of the present disclosure, an image sensor may include a charge accumulation region having a first conductivity type and disposed in a substrate, a charge storage region having the first conductivity type and disposed in the substrate to be laterally spaced apart from the charge accumulation region, a transfer gate electrode disposed on a channel region between the charge accumulation region and the charge storage region to transfer a charge from the charge accumulation region to the charge storage region, a first well region having a second conductivity type and disposed below the charge storage region to inhibit a charge generated below the charge storage region from being moved to the charge storage region, and a second well region having the second conductivity type and disposed below a portion of one side of the first well region adjacent to the charge accumulation region.
In accordance with some embodiments of the present disclosure, the second well region may have an impurity concentration lower than that of the first well region, and the substrate may have the second conductivity type and an impurity concentration lower than that of the second well region.
In accordance with some embodiments of the present disclosure, the image sensor may further include a third well region having the first conductivity type and disposed below the first well region.
In accordance with some embodiments of the present disclosure, the third well region may be electrically connected to a charge accumulation region of a neighboring image cell.
In accordance with some embodiments of the present disclosure, the third well region may have an impurity concentration lower than that of the charge accumulation region of the neighboring image cell.
In accordance with the embodiments of the present disclosure as described above, charges generated below the charge storage region may move to the charge accumulation region or the charge accumulation region of the neighboring image cell, and thus, image lag, parasitic light sensitivity, dynamic range, and crosstalk of the image sensor may be significantly improved.
The above summary of the present disclosure is not intended to describe each illustrated embodiment or every implementation of the present disclosure. The detailed description and claims that follow more particularly exemplify these embodiments.
Embodiments can be understood in more detail from the following description taken in conjunction with the accompanying drawings, in which:
While various embodiments are amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the claimed inventions to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the subject matter as defined by the claims.
Hereinafter, embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments described below and is implemented in various other forms. Embodiments below are not provided to fully complete the present disclosure but rather are provided to fully convey the range of the present disclosure to those skilled in the art.
In the specification, when one component is referred to as being on or connected to another component or layer, it can be directly on or connected to the other component or layer, or an intervening component or layer may also be present. Unlike this, it will be understood that when one component is referred to as directly being on or directly connected to another component or layer, it means that no intervening component is present. Also, though terms like a first, a second, and a third are used to describe various regions and layers in various embodiments of the present disclosure, the regions and the layers are not limited to these terms.
Terminologies used below are used to merely describe specific embodiments, but do not limit the present disclosure. Additionally, unless otherwise defined here, all the terms including technical or scientific terms, may have the same meaning that is generally understood by those skilled in the art.
Embodiments of the present disclosure are described with reference to schematic drawings of ideal embodiments. Accordingly, changes in manufacturing methods and/or allowable errors may be expected from the forms of the drawings. Accordingly, embodiments of the present disclosure are not described being limited to the specific forms or areas in the drawings, and include the deviations of the forms. The areas may be entirely schematic, and their forms may not describe or depict accurate forms or structures in any given area, and are not intended to limit the scope of the present disclosure.
Referring to
The charge accumulation region 110 may have a first conductivity type, and the substrate 102 may have a second conductivity type. For example, an N-type impurity diffusion region may be used as the charge accumulation region 110, and a P-type substrate may be used as the substrate 102. The charge storage region 114 may have the first conductivity type. For example, an N-type impurity diffusion region may be used as the charge storage region 114. Alternatively, a P-type epitaxial layer (not shown) may be formed on the substrate 102. In such case, the charge accumulation region 110 and the charge storage region 114 may be formed in the P-type epitaxial layer.
A pinning layer 112 having the second conductivity type may be formed on the charge accumulation region 110. For example, a P-type impurity diffusion region may be used as the pinning layer 112. That is, the image sensor 100 may include a pinned photodiode (PD) including the charge accumulation region 110 and the pinning layer 112.
Although not shown in figures, the image sensor 100 may include a floating diffusion region (not shown) laterally spaced apart from the charge storage region 114, and a second transfer gate electrode may be formed on a second channel region between the charge storage region 114 and the floating diffusion region. In addition, the image sensor 100 may include a reset gate electrode, a source follower gate electrode, and a selection gate electrode, and impurity diffusion regions serving as source/drain regions may be formed in surface portions of the substrate 102 adjacent to the reset gate electrode, the source follower gate electrode, and the selection gate electrode. Further, gate insulating layers made of silicon oxide may be formed between the electrodes and the substrate 102.
In accordance with an embodiment of the present disclosure, a first well region 120 may be disposed below the charge storage region 114 in order to inhibit charges generated below the charge storage region 114 from being moved to the charge storage region 114. The first well region 120 may have the second conductivity type. For example, the first well region 120 may be a P-type impurity diffusion region and may be formed by an ion implantation process. In particular, a second well region 122 may be formed below the first well region 120. For example, the second well region 122 may be formed below a portion of one side of the first well region 120 adjacent to a neighboring image cell 106A and may have a width narrower than that of the first well region 120. In addition, the second well region 122 may have the second conductivity type. For example, the second well region 122 may be a P-type impurity diffusion region having an impurity concentration lower than that of the first well region 120. In such case, the substrate 102 may have an impurity concentration lower than the second well region 122.
The neighboring image cell 106A may include a pinned photodiode including a charge accumulation region 110A and a pinning layer 112A. The first well region 120 and the second well region 122 may function as isolation regions for electrically isolating between the image cell 106 and the neighboring image cell 106A. Particularly, electrons generated below the charge storage region 114 may move to the charge accumulation region 110 of the image cell 106 by internal potential differences among the first and second well region 120 and 122 and the substrate 102, and between the charge accumulation region 110 and the substrate 102.
In accordance with an embodiment of the present disclosure, a third well region 124 having the first conductivity type may be formed below the first well region 120. The third well region 124 may be electrically connected to the charge accumulation region 110 and may be used to move the electrons to the charge accumulation region 110. For example, the third well region 124 may be an N-type impurity diffusion region formed by an ion implantation process and may have an impurity concentration lower than that of the charge accumulation region 110 for the movement of electrons. In addition, one side of the third well region 124 may be formed adjacent to one side of the second well region 122, and another side of the third well region 124 may be connected to the charge accumulation region 110.
As a result, the electrons generated below the charge storage region 114 may be inhibited from moving to the charge storage region 114 and may move to the charge accumulation region 110 through the third well region 124. Accordingly, image lag, parasitic light sensitivity, dynamic range, and crosstalk of the image sensor 100 may be significantly improved.
In accordance with an embodiment of the present disclosure, the image sensor 100 may include a first dummy pattern 130 disposed on a surface portion of the substrate 102 between the charge storage region 114 and the charge accumulation region 110A of the neighboring image cell 106A so as to inhibit light from entering the charge storage region 114 from the neighboring image cell 106A.
The first dummy pattern 130 may be formed of the same material as the transfer gate electrode 116 and simultaneously with the transfer gate electrode 116. For example, the first dummy pattern 130 and the transfer gate electrode 116 may be made of polysilicon doped with impurities, and the light from the neighboring image cell 106A toward the charge storage region 114 may be absorbed by the first dummy pattern 130. That is, the first dummy pattern 130 may function as a light absorption pattern for absorbing the light, thereby inhibiting the light from being introduced into the charge storage region 114 from the neighboring image cell 106A. For example, after forming a silicon oxide layer and an impurity-doped polysilicon layer on the substrate 102, the transfer gate electrode 116 and the dummy pattern 130 may be formed by patterning the polysilicon layer and the silicon oxide layer.
Further, a second dummy pattern 132 for inhibiting light from being introduced into the charge storage region 114 may be formed on the charge storage region 114. For example, the second dummy pattern 132 may be formed of the same material as the transfer gate electrode 116 and simultaneously with the transfer gate electrode 116. As shown in
An insulating layer 140 may be formed on the substrate 102, the transfer gate electrode 116, and the first and second dummy patterns 130 and 132. The insulating layer 140 may include a first oxide layer 142 formed on the substrate 102, the transfer gate electrode 114, and the first and second dummy patterns 130 and 132, a nitride layer 144 formed on the first oxide layer 142, and a second oxide layer 146 formed on the nitride layer 144. For example, the insulating layer 140 may include a first silicon oxide layer 142 formed on the substrate 102, the transfer gate electrode 116, and the first and the second dummy patterns 130 and 132, a silicon nitride layer 144 formed on the first silicon oxide layer 142, and a second silicon oxide layer 146 formed on the silicon nitride layer 144. Further, an anti-reflective layer 148 may be formed between the substrate 102 and the insulating layer 140. For example, the anti-reflective layer 148 may be formed of silicon nitride.
A light shield layer 150 for inhibiting light from entering the charge storage region 114 may be formed on the insulating layer 140. The light shield layer 150 may be made of a metal, for example, aluminum. In particular, a first light shield pattern 152 penetrating the insulating layer 140 may be formed between the first dummy pattern 130 and the light shield layer 150. The first light shield pattern 152 may be formed of a metal, for example, tungsten or copper. Accordingly, the light from the neighboring image cell 106A toward the charge storage region 114 may be reflected by the first light shield pattern 152. That is, the first light shield pattern 152 may function as a light reflection pattern. For example, a cell isolation region 104 may be formed between the charge storage region 114 and the charge accumulation region 110A of the neighboring image cell 106A, and the first dummy pattern 130 may be formed on the cell isolation region 104. Further, the first light shield pattern 152 may be formed on the first dummy pattern 130, and the light shield layer 150 may be formed on the insulating layer 140 and the light shield pattern 152.
In accordance with an embodiment of the present disclosure, as shown in
A second insulating layer 160 may be formed on the insulating layer 140 and the light shield layer 150. For example, a silicon oxide layer may be used as the second insulating layer 160. Further, a plurality of metal wiring layers 162, 166 and 170, and interlayer insulating layers 164, 168 and 172 may be formed on the second insulating layer 160. For example, a first metal wiring layer 162 may be formed on the second insulating layer 160, and a first interlayer insulating layer 164 may be formed on the second insulating layer 160 and the first metal wiring layer 162. A second metal wiring layer 166 may be formed on the first interlayer insulating layer 164, and a second interlayer insulating layer 168 may be formed on the first interlayer insulating layer 164 and the second metal wiring layer 166. A third metal wiring layer 170 may be formed on the second interlayer insulating layer 168, and a third interlayer insulating layer 172 may be formed on the second interlayer insulating layer 168 and the third metal wiring layer 170.
In accordance with an embodiment of the present disclosure, the image sensor 100 may include a light guide pattern layer 174 passing through the interlayer insulating layers 164, 168 and 172. Specifically, the light guide pattern layer 174 may include light guide patterns 176 passing through the interlayer insulating layers 164, 168 and 172, and a planarization layer 178 formed on the third interlayer insulating layer 172 and the light guide patterns 176. For example, the light guide pattern layer 174 may be formed of a dielectric material having a refractive index greater than that of silicon oxide forming the interlayer insulating layers 164, 168 and 172.
An etch stop layer 180 made of silicon nitride may be formed on the second insulating layer 160, as shown in
Alternatively, although not shown, the light guide patterns 176 may extend to the silicon nitride layer 144. That is, in an anisotropic etching process for forming the light guide patterns 176, the interlayer insulating layers 164, 168 and 172, the second insulating layer 160, and the second silicon oxide layer 146 may be partially removed until the silicon nitride layer 144 is exposed, and the silicon nitride layer 144 may be used as an etch stop layer. In such case, the light guide patterns 176 may be formed on the silicon nitride layer 144 through the interlayer insulating layers 164, 168 and 172, the second insulating layer 160, and the second silicon oxide layer 146, and the etch stop layer 180 may be omitted. Accordingly, a distance between the pinned photodiodes and the light guide patterns 176 may be greatly shortened.
The light guide patterns 176 may be arranged to correspond to the charge accumulation regions 110, and a color filter layer 182 including a plurality of color filters may be formed on the light guide pattern layer 174. A second planarization layer 184 may be formed on the color filter layer 182, and a microlens array 186 may be formed on the second planarization layer 184.
In accordance with the embodiment of the present disclosure as described above, the light from the neighboring image cell 106A toward the charge storage region 114 may be blocked by the second light shield pattern 154. Further, the light directed to the charge storage region 114 through between the second light shield pattern 154 and the substrate 102 may be blocked by the first dummy pattern 130 and the first light shield pattern 152. Accordingly, the light entering the charge storage region 114 may be significantly reduced, and thus, the dynamic range, crosstalk, and parasitic light sensitivity of the image sensor 100 may be greatly improved.
Referring to
In accordance with another embodiment of the present disclosure, a third well region 128 having the first conductivity type may be formed below the first well region 120. The third well region 128 may be electrically connected to a charge accumulation region 110A of a neighboring image cell 106A and may be used to move electrons generated below the charge storage region 114 to the charge accumulation region 110A of the neighboring image cell 106A. For example, the third well region 128 may be an N-type impurity diffusion region formed by an ion implantation process and may have an impurity concentration lower than that of the charge accumulation region 110A of the neighboring image cell 106A for the movement of electrons. In addition, one side of the third well region 128 may be formed adjacent to one side of the second well region 126, and another side of the third well region 128 may be connected to the charge accumulation region 110A of the neighboring image cell 106A.
As a result, the electrons generated below the charge storage region 114 may be inhibited from moving to the charge storage region 114 and may move to the charge accumulation region 110A of the neighboring image cell 106A through the third well region 128. Accordingly, image lag, parasitic light sensitivity, dynamic range, and crosstalk of the image sensor 100 may be significantly improved.
Meanwhile, since other components except for the second well region 126 and the third well region 128 are the same as those previously described with reference to
In accordance with the embodiments of the present disclosure as described above, charges generated below the charge storage region 114 may move to the charge accumulation region 110 through the third well region 124 or the charge accumulation region 110A of the neighboring image cell 106A through the third well region 128. Accordingly, image lag, parasitic light sensitivity, dynamic range, and crosstalk of the image sensor 100 may be significantly improved.
Although the example embodiments of the present disclosure have been described with reference to the specific embodiments, they are not limited thereto. Therefore, it will be readily understood by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the present disclosure defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0029487 | Mar 2022 | KR | national |
