Patent Application
20050274988
The present invention relates to the field of semiconductor devices, particularly to an imager pixel with improved quantum efficiency and reduced cross talk.
Typically, an image sensor array includes a focal plane array of pixels, each one of the pixels including a photo-conversion device such as, e.g., a photogate, photoconductor, or a photodiode.
The photodiode 21 converts photons to charge carriers, e.g., electrons, which are transferred to a floating diffusion region 15 by a transfer transistor 24. In addition, the illustrated pixel 10 typically includes a reset transistor 25, connected to a source/drain region 16, for resetting the floating diffusion region 15 to a predetermined charge level prior to charge transference. In operation, a source follower transistor (not shown) outputs a voltage representing the charge on the floating diffusion region 15 to a column line (not shown) when a row select transistor (not shown) for the row containing the pixel is activated.
Exemplary CMOS image sensor circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an image sensor circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are herein incorporated by reference in their entirety.
In the conventional pixel 10, when incident light strikes the surface of the photodiode 21, charge carriers (electrons), are generated in the depletion region of the p-n junction (between region 11 and region 12) of the photodiode 21. The carriers are collected in the region 11. Light having shorter wavelengths, e.g., 650 nanometers (nm) or shorter, (represented by arrows 18) is absorbed closer to the surface of the substrate 1, whereas light having longer wavelengths, e.g., 650-750 nm or longer, (represented by arrows 17) is absorbed deeper into the substrate 1. In the conventional pixel 10 of
Embodiments of the invention provide an imager pixel comprising a reflective layer formed over a substrate. There is a semiconductor layer over the reflective layer. A photo-conversion device is formed at a surface of the semiconductor layer. The reflective layer serves to reflect incident light, not initially absorbed into the photo-conversion device, back to the photo-conversion device. Thereby, the quantum efficiency of the pixel can be improved. Also, cross talk can be reduced as reflected light will not travel to adjacent pixels.
The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments provided below with reference to the accompanying drawings in which:
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate specific embodiments in which the invention may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.
The terms “wafer” and “substrate” are to be understood as including silicon, silicon-on-insulator (SOI), or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium-arsenide.
The term “pixel” refers to a picture element unit cell containing a photo-conversion device for converting electromagnetic radiation to an electrical signal. For purposes of illustration, a representative pixel is illustrated in the figures and description herein, and typically fabrication of all pixels in an image sensor will proceed concurrently in a similar fashion.
Referring to the drawings,
It should be noted that the configuration of pixel 200 is only exemplary and that various changes may be made as are known in the art and pixel 200 may have other configurations. Although the invention is described in connection with a four-transistor (4T) pixel, the invention may also be incorporated into other pixel circuits having different numbers of transistors. Without being limiting, such a circuit may include a three-transistor (3T) pixel, a five-transistor (5T) pixel, and a six-transistor (6T) pixel. A 3T cell omits the transfer transistor, but may have a reset transistor adjacent to a photodiode. A 5T pixel differs from the 4T pixel by the addition of a transistor, such as a shutter transistor or a CMOS photogate transistor, and a 6T pixel further includes an additional transistor, such as an anti-blooming transistor.
A readout circuit 230 is connected to the floating diffusion region 215. The readout circuit 230 includes a source follower transistor 226, the gate of which is connected to the floating diffusion region 215. The readout circuit also includes a row select transistor 227 for selecting the pixel 200 for readout in response to a signal received at the gate of the row select transistor 227.
A reset transistor 225 is provided adjacent to the floating diffusion region 215. In response to a signal received at the reset transistor 225 gate, the reset transistor 225 resets the floating diffusion region 215 to a predetermined voltage, which is, for example, an array voltage Vaa. The source/drain region 216 of the reset transistor 225 is connected to Vaa and is adjacent to an STI region 203.
As shown in
The Si layer 202 overlies a reflective layer 204, which in turn overlies a substrate 201. As shown in
In the exemplary embodiment of
Each set of sub-layers which makes up the structural pattern of reflective layer 204 has a thickness T. For example, as shown in
Light of a targeted wavelength (represented by dashed arrows) incident on photodiode 221, which is not initially absorbed into photodiode 221, is reflected by the reflective layer 204, as shown in
The number of sub-layers in layer 204 and the materials used to form the sub-layers can be optimized to produce a highly reflective DBR mirror at a targeted wavelength. At the targeted wavelength, the optimal number of sub-layers will depend on the difference in the refractive indexes of the chosen materials.
Exemplary embodiments for the fabrication of the pixel 200 are described below with reference to
As shown in
Alternatively, in another exemplary embodiment, layer 204 can be formed having an SiO2/Si structure. In such a case sub-layers 204a, 204c, and 204m are SiO2 sub-layers and sub-layers 204b and 204n are Si sub-layers. The SiO2/Si structure can be formed using known SOI techniques, such as, for example, wafer bonding techniques, where two oxidized Si wafers are bonded and the excess Si from one of the wafers is removed; or implantation techniques, where oxygen is implanted into a Si wafer, to achieve the structure shown in
The isolation regions 203 are formed in the Si layer 202 and filled with a dielectric material. The dielectric material may be an oxide material, for example a silicon oxide, such as SiO or SiO2; oxynitride; a nitride material, such as silicon nitride; silicon carbide; a high temperature polymer; or other suitable dielectric material. As shown in
To form the transfer and reset transistor 224, 225 gate stacks, as shown in
The layers 220a, 220b, and 220c, may be formed by conventional deposition methods, such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD), among others. The layers 220a, 220b, and 220c are then patterned and etched to form the transfer and reset transistor 224, 225 multilayer gate stack structures shown in
The invention is not limited to the structure of the gate stacks described above. Additional layers may be added or the gate stacks may be altered as is desired and known in the art. For example, a silicide layer (not shown) may be formed between the gate electrodes 220b and the second insulating layers 220c. The silicide layer may be included in the transfer and reset transistor 224, 225 gate stacks, or in all of the transistor gate structures in an image sensor circuit, and may be titanium silicide, tungsten silicide, cobalt silicide, molybdenum silicide, or tantalum silicide. This additional conductive layer may also be a barrier layer/refractor metal, such as TiN/W or W/Nx/W, or it could be formed entirely of WNx.
A well 218 of the first conductivity type, illustratively a p-well, is implanted into the Si layer 202 as shown in
As depicted in
As shown in
The floating diffusion region 215 and the reset transistor 225 source/drain region 216 may be implanted by known methods to achieve the structure shown in
The doped surface layer 212 for the photodiode 221 is implanted, as illustrated in
The p+ surface layer 212 may be formed by known techniques. For example, layer 212 may be formed by implanting p-type ions through openings in a layer of photoresist. Alternatively, layer 212 may be formed by a gas source plasma doping process, or by diffusing a p-type dopant into the Si layer 202 from an in-situ doped layer or a doped oxide layer deposited over the area where layer 212 is to be formed.
Also, as shown in
Conventional processing methods may be used to complete the pixel 200. For example, insulating, shielding, and metallization layers to connect gate lines, and other connections to the pixel 200 may be formed. Also, the entire surface may be covered with a passivation layer (not shown) of, for example, silicon dioxide, BSG, PSG, or BPSG, which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts. Conventional layers of conductors and insulators may also be used to interconnect the structures and to connect pixel 200 to peripheral circuitry.
While the above embodiments are described in connection with the formation of pnp-type photodiodes the invention is not limited to these embodiments. The invention also has applicability to other types of photo-conversion devices, such as a photodiode formed from np or npn regions in a substrate, a photogate, or a photoconductor. If an npn-type photodiode is formed the dopant and conductivity types of all structures would change accordingly.
A typical single chip CMOS image sensor 1100 is illustrated by the block diagram of
The pixels of each row in array 1111 are all turned on at the same time by a row select line, and the pixel signals of each column are selectively output by respective column select lines. The row lines are selectively activated by a row driver 1151 in response to row address decoder 1150. The column select lines are selectively activated by a column driver 1153 in response to column address decoder 1154. The pixel array is operated by the timing and control circuit 1152, which controls address decoders 1150, 1154 for selecting the appropriate row and column lines for pixel signal readout.
The signals on the column readout lines typically include a pixel reset signal (Vrst) and a pixel image signal (Vphoto) for each pixel. Both signals are read into a sample and hold circuit (S/H) 1155 associated with the column driver 1153. A differential signal (Vrst−Vphoto) is produced by differential amplifier (AMP) 1156 for each pixel, and each pixel's differential signal is amplified and digitized by analog to digital converter (ADC) 1157. The analog to digital converter 1157 supplies the digitized pixel signals to an image processor 1158 which performs appropriate image processing before providing digital signals defining an image.
Although the invention is described in connection with a CMOS image sensor 1100, the invention is also applicable to analogous structures of a charge coupled device (CCD) image sensor.
The processor-based system 1200, for example a computer system, generally comprises a central processing unit (CPU) 1207, such as a microprocessor, that communicates with an input/output (I/O) device 1201 over a bus 1204. Image sensor 1100 also communicates with the CPU 1207 over bus 1204. The processor-based system 1200 also includes random access memory (RAM) 1206, and may include peripheral devices, such as a floppy disk drive 1202 and a compact disk (CD) ROM drive 1203, which also communicate with CPU 1207 over the bus 1204. Image sensor 1100 may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor.
It is again noted that the above description and drawings are exemplary and illustrate preferred embodiments that achieve the objects, features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Any modification of the present invention which comes within the spirit and scope of the following claims should be considered part of the present invention.
