1. Field of the Invention
The present invention relates to an imaging apparatus and an imaging system.
2. Description of the Related Art
In Japanese Patent Application Laid-Open Nos. 2007-243744 and 2013-172210, there are proposed imaging apparatus each having both a global electronic shutter function and a focus detection function by using a phase difference method on an imaging plane. Those imaging apparatus include a plurality of photoelectric converters configured to output signal charges used for image signals and signal charges used for focus detection, and a plurality of charge holding portions configured to hold the signal charges transferred from the photoelectric converters.
In the imaging apparatus disclosed in Japanese Patent Application Laid-Open Nos. 2007-243744 and 2013-172210, when at least one of the plurality of charge holding portions is saturated, the charges originally required to be held by the saturated charge holding portion may leak to the charge holding portion in an adjacent pixel. Further, the charges originally required to be held by the saturated charge holding portion may not be transferred from the photoelectric converter but remain in the photoelectric converter. For those reasons, when at least one of the plurality of charge holding portions is saturated, image quality may deteriorate even if the other charge holding portions are not saturated.
The present invention has been made in view of the above-mentioned problem, and has an object to improve image quality in an imaging apparatus having both a global electronic shutter function and a focus detection function by using a phase difference method on an imaging plane.
According to one embodiment of the present invention, there is provided an imaging apparatus, including a pixel region in which a plurality of pixels are arranged, the plurality of pixels each including: a plurality of photoelectric converters configured to generate charges corresponding to an amount of incident light; a plurality of charge holding portions arranged correspondingly to the plurality of photoelectric converters and configured to hold charges generated by the plurality of photoelectric converters respectively; and a light condensing portion arranged so as to be shared by the plurality of photoelectric converters and configured to guide the incident light to the plurality of photoelectric converters, in which a height Vb of a first potential barrier between two of the plurality of charge holding portions included in a same pixel is lower than a height Va of a second potential barrier between two of the plurality of charge holding portions included in different pixels.
According to another embodiment of the present invention, there is provided an imaging apparatus, including: a pixel region in which a plurality of pixels are arranged, the plurality of pixels each including: a plurality of photoelectric converters configured to generate charges corresponding to an amount of incident light; a plurality of charge holding portions arranged correspondingly to the plurality of photoelectric converters and configured to hold charges generated by the plurality of photoelectric converters respectively; and a light condensing portion arranged so as to be shared by the plurality of photoelectric converters and configured to guide the incident light to the plurality of photoelectric converters; a first isolation portion formed between adjacent ones of the plurality of charge holding portions included in a same pixel, the first isolation portion being formed of a semiconductor region having a conductivity type that is different from a conductivity type of a semiconductor region forming the plurality of charge holding portions; and a second isolation portion formed between adjacent ones of the plurality of charge holding portions included in different pixels, the second isolation portion being formed of an insulating material.
According to another embodiment of the present invention, there is provided an imaging apparatus, including: a pixel region in which a plurality of pixels are arranged, the plurality of pixels each including: a plurality of photoelectric converters configured to generate charges corresponding to an amount of incident light; a plurality of charge holding portions arranged correspondingly to the plurality of photoelectric converters and configured to hold charges generated by the plurality of photoelectric converters respectively; and a light condensing portion arranged so as to be shared by the plurality of photoelectric converters and configured to guide the incident light to the plurality of photoelectric converters; a first isolation portion formed between adjacent ones of the plurality of charge holding portions included in a same pixel, the first isolation portion being formed of a first semiconductor region having a conductivity type that is different from a conductivity type of a semiconductor region forming the plurality of charge holding portions; and a second isolation portion formed between adjacent ones of the plurality of charge holding portions included in different pixels, the second isolation portion being formed of a second semiconductor region having the conductivity type that is different from the conductivity type of the semiconductor region forming the plurality of charge holding portions, and in which an impurity concentration of the first semiconductor region is lower than an impurity concentration of the second semiconductor region.
According to another embodiment of the present invention, there is provided an imaging apparatus, including a pixel region in which a plurality of pixels are arranged, the plurality of pixels each including: a plurality of photoelectric converters configured to generate charges corresponding to an amount of incident light; a plurality of charge holding portions arranged correspondingly to the plurality of photoelectric converters and configured to hold charges generated by the plurality of photoelectric converters respectively; and a light condensing portion arranged so as to be shared by the plurality of photoelectric converters and configured to guide the incident light to the plurality of photoelectric converters, in which a height Vb of a first potential barrier between two of the plurality of charge holding portions included in a same pixel is lower than a difference ΔVdep between a depletion voltage of one of the plurality of photoelectric converters and a depletion voltage of corresponding one of the plurality of charge holding portions.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
Preferred embodiments of the present invention will now be described in detail in accordance with the accompanying drawings. In the drawings of each of the embodiments, components having the same functions are denoted by the same reference symbols, and overlapping descriptions thereof are sometimes omitted.
The pixel 100 is an element configured to convert incident light into an electrical signal and output the converted electrical signal. The respective pixels 100 are connected to vertical signal lines 14 arranged for respective columns of the imaging apparatus 10. A signal from the pixel 100 is output to the column amplifier portion 16 by a current supplied from a current source 15 connected to each vertical signal line 14. The column amplifier portion 16 includes an amplifier circuit and the like. The column amplifier portion 16 performs processing such amplification on the input signal, and outputs the resultant signal to the column signal holding portion 17. The column signal holding portion 17 is a circuit configured to temporarily hold the signal input from the column amplifier portion 16. The horizontal scanning circuit 18 transmits a control signal for column select and the like to the column signal holding portion 17. Based on the control signal from the horizontal scanning circuit 18, the column signal holding portion 17 sequentially outputs the signals from the respective pixel columns to the output circuit 20 via an output signal line 19. The output circuit 20 performs processing such as amplification on the input signal, and outputs the resultant signal to a signal processing unit or the like connected at the subsequent stage of the imaging apparatus 10. The above-mentioned configuration of the imaging apparatus 10 is merely an example, and another circuit or the like may be added as appropriate.
The pixel 100 further includes first transfer transistors 206 and 207 configured to transfer the charges from the PDs 201 and 202 to the MEMs 203 and 204, respectively, and second transfer transistors 208 and 209 configured to transfer the charges from the MEMs 203 and 204 to the FD 205, respectively. The first transfer transistors 206 and 207 are controlled to be turned on or off based on a control signal PTX1. The second transfer transistor 208 is controlled to be turned on or off based on a control signal PTX21, and the second transfer transistor 209 is controlled to be turned on or off based on a control signal PTX22.
The pixel 100 further includes a reset transistor 210, an amplifier transistor 211, and a select transistor 212. A drain of the reset transistor 210 is supplied with a reset voltage, and a source of the reset transistor 210 is connected to the FD 205. When the reset transistor 210 is turned on, the charges transferred to the FD 205 are reset. The FD 205 is a gate node of the amplifier transistor 211. The amplifier transistor 211 amplifies and outputs a signal corresponding to the amount of charges transferred to the FD 205. A source of the amplifier transistor 211 is connected to a drain of the select transistor 212, and a source of the select transistor 212 is connected to the vertical signal line 14. When the select transistor 212 is turned on, a pixel row to be read is selected, and the signal from the amplifier transistor 211 is output to the vertical signal line 14. The reset transistor 210 is controlled to be turned on or off based on a control signal PRES, and the select transistor 212 is controlled to be turned on or off based on a control signal PSEL.
The pixel 100 further includes overflow drains (OFDs) and OFD control transistors 213 and 214. The OFD control transistor 213 is connected between the photoelectric converter 201 and the OFD, and the control transistor 214 is connected between the photoelectric converter 202 and the OFD. The OFD control transistors 213 and 214 are controlled to be turned on or off based on a control signal POFD. When the OFD control transistors 213 and 214 are turned on, the PDs 201 and 202 are reset, respectively.
The pixel 100 further includes a microlens 215 (light condensing portion) configured to guide incident light into the PDs 201 and 202. The PDs 201 and 202 share the single microlens 215.
Referring to
At a time t301, signals of the previous frame are held by the MEMs 203 and 204. In the period from the time t301 to a time t303, the signals of the previous frame are sequentially read (“MEM READ” in
In parallel to the reading of the signals of the previous frame, in the period from the time t301 to a time t305, the PDs 201 and 202 are reset and the charges are accumulated into the PDs 201 and 202 for the frame concerned (“PD RESET” and “PD ACCUMULATION” in
At the time t302, the control signal POFD becomes Low level. The OFD control transistors 213 and 214 are turned off, and the signal charges start to be accumulated in the PDs 201 and 202 for all the pixels simultaneously.
In the period from a time t304 to the time t305, the control signal PTX1 becomes High level, and the first transfer transistors 206 and 207 are turned on. Then, the signal charges accumulated in the PDs 201 and 202 are transferred to the MEMs 203 and 204, respectively, for all the pixels simultaneously.
At the time t305, the control signal PTX1 becomes Low level, and the first transfer transistors 206 and 207 are turned off. Then, the accumulation of the signal charges for all the pixels is finished simultaneously. In this manner, the charge accumulation period for the PDs 201 and 202 is set to occur simultaneously for all the pixels, to thereby realize a global electronic shutter. Note that, in
In the period from the time t305 to a time t306, the control signal POFD becomes High level, and the OFD control transistors 213 and 214 are turned on. Then, the charges of the PDs 201 and 202 are discharged to the OFDs, and the PDs 201 and 202 are reset. At the time t306, the control signal POFD becomes Low level, and the OFD control transistors 213 and 214 are turned off. After the time t306, signals for the next frame start to be accumulated into the PDs 201 and 202.
In the period from the time t305 to a time t307, the signal charges for the frame concerned accumulated in the MEMs 203 and 204 are sequentially read. The signal charges are read in accordance with the timing chart of
Next, referring to
At a time t312, the control signal PSEL becomes High level, and the select transistors 212 of the pixels in the row to be read are turned on.
At a time t313, the control signal PRES becomes Low level, and the reset transistor 210 is turned off. Then, the reset of the FD 205 is canceled, and a signal corresponding to the reset level of the FD 205 is amplified by the amplifier transistor 211 to be output to the vertical signal line 14.
In the period from the time t313 to a time t314, the signal corresponding to the reset level of the FD 205 is obtained by a read circuit (column amplifier portion 16, column signal holding portion 17, etc.) (hereinafter referred to as “Reading N”).
In the period from the time t314 to a time t315, the control signal PTX21 becomes High level, and the second transfer transistor 208 is turned on. Then, the signal charges held by the MEM 203 are transferred to the FD 205. Then, a signal corresponding to the amount of charges held by the MEM 203 is amplified by the amplifier transistor 211 to be output to the vertical signal line 14.
In the period from the time t315 to a time t316, the signal corresponding to the amount of charges held by the MEM 203 is obtained by the read circuit (hereinafter referred to as “Reading A”).
In the period from the time t316 to a time t317, the control signals PTX21 and PTX22 become High level, and the signal charges held by the MEMs 203 and 204 are both transferred to the FD 205. Then, a signal corresponding to the sum of the amounts of charges held by the MEMs 203 and 204 is amplified by the amplifier transistor 211 to be output to the vertical signal line 14.
In the period from the time t317 to a time t318, the signal corresponding to the sum of the amounts of charges held by the MEMs 203 and 204 is obtained by the read circuit (hereinafter referred to as “Reading A+B”).
At the time t318, the control signal PRES becomes High level, and the reset transistor 210 is turned on. Then, the FD 205 is reset again.
At a time t319, the control signal PSEL becomes Low level, and the select transistor 212 is turned off. Then, the select of the pixel row is canceled.
In the period from the time t311 to a time t320, the reading of the signals from one row of the pixels 100 arranged in rows and columns in the pixel region 11 is completed. The reading rows are scanned to perform the above-mentioned operation sequentially for the respective rows, to thereby read the signals from all the pixels. When the time period required for the processing from the time t311 to the time t320 is represented by Th, the time period (Th×number of rows) corresponding to the reading time period for all the rows corresponds to the time period required from the time t301 to the time t303 or from the time t305 to the time t307 of
A difference between the signal obtained by Reading A and a signal obtained by Reading N is obtained, to thereby obtain a signal SA corresponding to the charges held by the MEM 203 in which noise such as reset noise has been removed. Similarly, a difference between the signal obtained by Reading A+B and the signal obtained by Reading A is obtained, to thereby obtain a signal SB corresponding to the charges held by the MEM 204. The use of the signal SA and the signal SB enables phase difference focus detection.
Based on a difference between the signal obtained by Reading A+B and the signal obtained by Reading N, a signal SAB corresponding to the sum of the charges held by the MEMs 203 and 204 is obtained. The signal SAB is used as a pixel signal for imaging. The signal SAB and the signals SA and SB are used for different purposes, and are therefore different in required accuracy. The accuracy of the signal SAB affects the image quality, and hence the signal SAB is required to have a high S/N ratio. On the other hand, the signals SA and SB are used only for focus detection, and hence may be allowed to be lower in accuracy than the signal SAB.
Note that, the timing charts illustrated in
V(OFD)≧V(FD205)
V(FD205)>V(MEM203)
V(MEM203)=V(MEM204)
V(MEM203)>V(PD201)
V(PD201)=V(PD202)
The above-mentioned relationships of the potential depths at the respective portions enable the charges to be completely transferred from the PDs 201 and 202 to the MEMs 203 and 204 and the charges to be completely transferred from the MEMs 203 to 204 to the FD 205. In this embodiment, a height Vb of a potential barrier between the MEM 203 and the MEM 204 is lower than a height Va of a potential barrier between the MEM 203 or the MEM 204 of the pixel concerned and the MEM of an adjacent pixel. The height of the potential barrier refers to potential energy required for signal charges in a region concerned to migrate to the outside of the region concerned.
Note that, the difference (V(MEM 203)−V(PD 201)) in potential depth between the PD 201 and the MEM 203 is a difference ΔVdep between a depletion voltage of the PD 201 and a depletion voltage of the MEM 203. The height Vb in this case may be higher or lower than the difference ΔVdep. In the configuration according to this embodiment illustrated in
A height Vd of a potential barrier between the PD 201 and the PD 202 and a height Vc of a potential barrier between the PD 201 or the PD 202 and the PD of an adjacent pixel have the relationship of Vd≦Vc. When Vd<Vc is established as illustrated in
In addition, in the period from the time t303 to the time t304, which is the signal accumulation period for the PDs 201 and 202, it is preferred to set the potential barrier between the PD 201 and the MEM 203 to be lower than the potential barrier between the PD 201 and the OFD. Consequently, the charges overflowing out of the PD 201 can be accumulated in the MEM 203 without being discarded to the OFD. In the period from the time t302 to the time t303, on the other hand, it is preferred to set the potential barrier between the PD 201 and the MEM 203 to be higher than the potential barrier between the PD 201 and the OFD. This is because this setting can reduce image quality degradation caused when the charges accumulated in the PD 201 in the frame concerned are mixed into the MEM 203 in which the signal for the previous frame is held.
When the number of electrons generated by the PD 201 is larger than the number of electrons that can be held by the MEM 203 without exceeding the height Vb of the potential barrier, in
Note that, as described above, when the number of electrons generated by the PD 201 exceeds the height Vb of the potential barrier, the electrons overflowing out of the MEM 203 are held by the MEM 204. In other words, the electrons originally required to be held by the MEM 203 migrate to the MEM 204, and hence the accuracy of the signals SA and SB for focus detection may deteriorate. In other words, the accuracy of the signals SA and SB for focus detection and the accuracy of the signal SAB for imaging may have a tradeoff relationship. However, because the signals SA and SB are the signals used for focus detection as described above, the accuracy of the signals SA and SB may be allowed to be lower than the accuracy of the signal SAB for imaging depending on the cases. In such a case, the accuracy of the signal SAB for imaging required to have a high S/N ratio can be enhanced without causing a problem of the degradation of the signals SA and SB for focus detection.
The migration of electrons to the MEM 204 illustrated in
In
In the p-type semiconductor regions 709 to 711, the p-type impurity concentration becomes higher as the depth in the substrate becomes larger. Accordingly, a potential gradient occurs in the depth direction of the substrate, and signal electrons generated at the deep part in the substrate are collected in the PD 201. The p-type semiconductor region 717 has an impurity concentration higher than that in the p-type semiconductor region 709, to thereby prevent the electrons generated at the deep part in the substrate from flowing into the MEM 203. Further, the electrostatic capacitance of the MEM 203 can be increased through an increase in electrostatic capacitance of the PN junction formed between the n-type semiconductor region 702 and the p-type semiconductor region 717. The p-type semiconductor region 712 has an impurity concentration higher than that in the p-type semiconductor region 710, to thereby have a function of electrically isolating the pixels.
In
The p-type semiconductor region 720 serves as a potential barrier for preventing the electrons generated at a part deeper than the p-type semiconductor region 720 from flowing into the PD 201 by keeping the electrons generated at a part shallower than the p-type semiconductor region 720 in the PD 201. Accordingly, the depth of the PD 201 is determined by the depth of the p-type semiconductor region 720. The p-type semiconductor region 721 is a region for isolating the n-type semiconductor regions 702 to 704 from the n-type semiconductor region 722. The p-type semiconductor region 716 of
The n-type semiconductor region 801 corresponds to the n-type semiconductor region 702 of
In
In
In
Note that, in
The difference between a second embodiment of the present invention and the first embodiment resides in that the height Vb of the potential barrier between the MEM 203 and the MEM 204 is lower than ΔVdep. In this embodiment, a circuit diagram of a pixel 100 is the same as that of
In the first embodiment, when the amount of charges generated by the PD 201 is larger than the number of electrons that can be held by the MEM 203 without exceeding the depletion voltage difference ΔVdep, the electrons of the PD 201 are not completely transferred to the MEM 203, but a part of the charges remain in the PD 201. The charges remaining in the PD 201 are not read as a signal, and hence the linearity of the output with respect to the amount of incident light is not maintained, which may be a cause of image quality degradation. According to this embodiment, the amount of charges remaining in the PD 201 can be reduced to further improve the image quality.
When the amount of light entering the pixel 100 falls within the range of from I0 to I1, the charges held by the MEM 203 do not exceed the height Vb of the potential barrier between the MEM 203 and the MEM 204. When the amount of light is I1, the maximum amount of charges that can be held without exceeding the height Vb of the potential barrier between the MEM 203 and the MEM 204 are generated by the PD 201.
When the amount of incident light falls within the range of from I1 to I2, some of the electrons generated by the PD 201 exceeding the height Vb of the potential barrier overflow to the MEM 204. When the amount of light is I2, the charges are accumulated in the MEM 203 and the MEM 204 until the potentials of the MEM 203 and the MEM 204 reach the potentials of the height Vb of the potential barrier.
When the amount of incident light falls within the range of from I2 to I3, the charges generated by the PD 201 and the PD 202 are held by both of the MEM 203 and the MEM 204. In this case, the amounts of charges transferred to the MEM 203 and the MEM 204 are equal to each other.
When the amount of incident light exceeds I3, an increase in potential due to the transferred charges exceeds ΔVdep, and hence the charges of the PD 201 or the PD 202 cannot be completely transferred but remain in the PD 201 or the PD 202 after the charges are transferred to the MEM 203 and the MEM 204. Thus, a part of the generated charges are not read, and hence the linearity between the amount of incident light and the output of “MEM 203+MEM 204” is not maintained as illustrated in
According to this embodiment, the height Vb of the potential barrier between the MEM 203 and the MEM 204 is set to be lower than the difference ΔVdep between the depletion voltage of the PD 201 and the depletion voltage of the MEM 203. Consequently, the linearity between the amount of incident light and the output of “MEM 203+MEM 204” is maintained in the range where the amount of incident light is equal to or smaller than I3, that is, in the range where the amount of incident light is equal to or smaller than such an amount of incident light that the charges corresponding to ΔVdep are held by both of the MEM 203 and the MEM 204.
The difference between a third embodiment of the present invention and the first and second embodiments resides in that the signal charges are accumulated in the MEMs 203 and 204 rather in the PDs 201 and 202.
At a time t1101, reading of signals for the previous frame is finished. At this time, the control signal PTX1 is at Low level and the control signal POFD is at High level. In other words, the first transfer transistors 206 and 207 are off, the OFD control transistors 213 and 214 are on, and the PDs 201 and 202 are reset.
At a time t1102, the control signal POFD becomes Low level, and the OFD control transistors 213 and 214 are turned off. At the same time, the control signal PTX1 becomes High level, and the first transfer transistors 206 and 207 are turned on. Then, the signal charges start to be accumulated for all the pixels simultaneously. In the period from the time t1102 to a time t1103, because the first transfer transistors 206 and 207 are on, the signal charges generated by the PDs 201 and 202 are immediately transferred and accumulated in the MEMs 203 and 204.
At the time t1103, the control signal PTX1 becomes Low level. Then, the first transfer transistors 206 and 207 are turned off, and the accumulation of the signals is finished for all the pixels simultaneously. At the same time, the control signal POFD becomes High level, and the OFD control transistors 213 and 214 are turned on. Then, the PDs 201 and 202 are reset again. After that, in the period from the time t1103 to a time t1104, the signal charges held by the MEMs 203 and 204 are sequentially read.
The imaging apparatus 10 including the pixel 100 illustrated in
According to this embodiment, when the signal charges are generated by the PDs 201 and 202, the signal charges are immediately transferred and accumulated in the MEMs 203 and 204. Accordingly, it is preferred to set the height Vb of the potential barrier between the MEM 203 and the MEM 204, which are included in the same pixel and adjacent to each other, to be higher than the height Vd of the potential barrier between the PD 201 and the PD 202, which are included in the same pixel and adjacent to each other.
According to the configuration in this embodiment, the dynamic range can be enlarged in addition to the effects of the first and second embodiments.
The difference between a fourth embodiment of the present invention and the first to third embodiments resides in that the pixel operates so that the signal charges generated in the signal read period for the previous frame are accumulated in the PDs 201 and 202 and the signal charges generated in periods other than the signal read period are accumulated in the MEMs 203 and 204. A top view, a potential diagram, and cross-sectional structures of the pixel 100 in this embodiment are the same as those in the first to third embodiments. Specifically, the top view in this embodiment is the same as that of
At the time t1203, the control signal PTX1 becomes High level, and the first transfer transistors 206 and 207 are turned on. Then, the charges accumulated in the PDs 201 and 202 in the period from the time t1202 to the time t1203 are transferred to the MEMs 203 and 204.
In the period from the time t1203 to the time t1204, the control signal PTX1 is maintained at High level, and hence the first transfer transistors 206 and 207 are maintained to be on. Accordingly, the charges generated by the PDs 201 and 202 are immediately transferred and accumulated in the MEMs 203 and 204. At the time t1204, the control signal PTX1 becomes Low level, and the first transfer transistors 206 and 207 are turned off. Then, all the pixels finish the signal accumulation simultaneously. Driving in the subsequent period from the time t1204 to a time t1206 is the same as the driving in the period from the time t305 to the time t307 of
According to the driving method in the third embodiment, the electrons generated by the PDs 201 and 202 are not accumulated in the period from the time t1103 to the time t1104, which is the signal read period. According to the driving method in this embodiment, on the other hand, the signal charges generated in the signal read period for the previous frame can also be accumulated. In addition, the period of accumulating the electrons in the PDs 201 and 202 is shorter than that in the example illustrated in
Note that, in
Also in this embodiment, it is preferred to set the height Vb of the potential barrier between the MEM 203 and the MEM 204, which are included in the same pixel and adjacent to each other, to be higher than the height Vd of the potential barrier between the plurality of PDs 201 and 202, which are included in the same pixel and adjacent to each other.
According to the configuration in this embodiment, the dynamic range can be enlarged in addition to the effects of the first and second embodiments.
The difference between a fifth embodiment of the present invention and the first to fourth embodiments resides in that signals of a plurality of PDs in the same pixel are read with use of a plurality of different FDs.
Drive timings in one frame period according to this embodiment may be the same as those in any one of the first, third, and fourth embodiments. In other words, the timing chart of any one of
Operations of the control signals PTX21 and PTX22 of
In the period from the time t1411 to the time t1412, the control signal PTX22 becomes High level, and the second transfer transistors 209 and 1309 are turned on. Then, the charges held by the MEMs 204 and 1304 are transferred to the FDs 205 and 1305, respectively. After that, signals amplified by the amplifier transistors 211 and 1311 are output to the vertical signal lines 14 in the period from the time t1412 to the time t1413. In other words, the signals of the PDs in the same pixel (PD 201 and PD 1301, or PD 202 and PD 1302) are read with use of different FDs (FD 205 and FD 1305). After that, Reading S of the signals corresponding to the amounts of the charges held by the MEMs 204 and 1304 is performed.
Note that, in
The difference between a sixth embodiment of the present invention and the first to fifth embodiments resides in that each pixel includes at least three PDs and at least three MEMs corresponding to the at least three PDs.
Drive timings in one frame period according to this embodiment may be the same as those in any one of the first, third, and fourth embodiments. In other words, the timing chart of any one of
In
In
As a seventh embodiment of the present invention, an imaging system using the imaging apparatus according to the first to sixth embodiments is described. Examples of the imaging system include a digital still camera, a digital camcorder, a camera head, a copying machine, a facsimile machine, a mobile phone, an on-board camera, and an observation satellite.
In
The imaging system further includes a signal processing unit 1007, a timing generation unit 1008, a general control/operation unit 1009, a memory unit 1010, a recording medium control interface (I/F) unit 1011, a recording medium 1012, and an external I/F unit 1013. The signal processing unit 1007 performs various kinds of processing, such as noise correction and data compression, on imaging data output from the imaging apparatus 10. The timing generation unit 1008 outputs various kinds of timing signals to the imaging apparatus 10 and the signal processing unit 1007. The general control/operation unit 1009 controls the entire digital still camera. The memory unit 1010 temporarily stores the image data. The recording medium control I/F unit 1011 is an I/F unit configured to record or read data to or from the recording medium 1012. The recording medium 1012 is a removable recording medium such as a semiconductor memory or a recording medium built in the imaging system, which is configured to record or read the imaging data. Then, the external I/F unit 1013 is an interface unit configured to communicate to and from an external computer and the like.
The timing signals may be input from the outside of the imaging system. The imaging system only needs to include at least the imaging apparatus 10 and the signal processing unit (signal processing device) 1007 configured to process an imaging signal output from the imaging apparatus 10.
Further, the signal processing unit 1007 may be configured to process a signal based on the charges generated by the first PD 201 and a signal based on the charges generated by the second PD 202, to thereby obtain distance information from the imaging apparatus 10 to an object.
The imaging system according to this embodiment includes the imaging apparatus according to the first to sixth embodiments as the imaging apparatus 10. Consequently, according to this embodiment, the imaging system with improved image quality can be provided.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. For example, any configurations described in the different embodiments may be combined in various ways.
This application claims the benefit of Japanese Patent Application No. 2014-206281, filed Oct. 7, 2014, which is hereby incorporated by reference herein in its entirety.
Number | Date | Country | Kind |
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2014-206281 | Oct 2014 | JP | national |