Patent Application
20060001753
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-197333, filed in Month July, 2004, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an imaging technology, more particularly to a technology capable of being effectively applied to imaging devices, such as a complementary metal oxide semiconductor (CMOS) image sensor and the like.
2. Description of the Related Art
For example, compared with a charge coupled device (CCD) image sensor, a CMOS image sensor is well matched with peripheral image processing circuits in a manufacturing process, operating voltage and the like, and in the CMOS image sensor, an imaging device, an image processing circuit, a controller and the like can be easily integrated on one chip.
Since in this CMOS image sensor, not only an optical/electrical conversion device but a conversion signal can also be amplified at each pixel level, the CMOS image sensor has an advantage of being resistant to noise in the transmission process of an optically/electrically converted signal. However, the CMOS image sensor has fixed pattern noise due to the uneven characteristic of an amplifier at each pixel level, which is a problem.
In this case, as the countermeasure, a configuration in which the same number of correlation double sampling (CDS) circuits and analog/digital conversion (ADC) circuits as that of columns are arrayed in parallel for each set of pixels in the column direction of a plurality of pixels two-dimensionally arrayed in the orthogonal row and column directions, that is, a configuration for reducing the fixed pattern noise by a so-called column ADC method, is known.
However, in this column ADC method, an output image takes a vertical striped pattern due to unevenness (column offset) in an ADC circuit and the like among columns, which is another problem.
In order to kill the column offset, it can be considered to duplicate the circuit configuration of a column ADC to kill the unevenness between the two systems. However, even in this case, the unevenness of the original main signal system, due to unevenness among devices composing each pixel cannot be killed.
As to the CMOS image sensor, for example, Patent Reference 1 discloses a technology for diagnosing/managing the operation of the entire image sensor using a state machine and solving the problem of a column CDS by digitizing a processing signal.
Patent Reference 1: Japanese Patent Application Laid-open No. 11-331883
It is an object of the present invention to provide a technology capable of preventing the degradation of an output image due to an uneven characteristic among the reading processing circuits in an imaging device in which the reading processing circuit of an optically/electrically converted signal is disposed for each row or column of a plurality of two-dimensionally arrayed pixels.
The first aspect of the present invention is an imaging device provided with a read circuit in which a light-shielding region is formed in a part of an image region where a plurality of optical/electrical conversion devices is two-dimensionally arrayed in the row and column directions and which converts an optically detected signal outputted from each of the optical/electrical conversion devices for each of the column into a digital signal, comprises a storage device for storing the outputted digital signal in relation with the optical/electrical conversion device in the light-shielding region and a difference calculation device for calculating a difference between the outputted digital signal and a value stored in the storage device in relation with the optical/electrical conversion device in a light-receiving region except the light-shielding region.
The second aspect of the present invention is the control method of an imaging device provided with a read circuit in which a light-shielding region is formed in a part of an image region where a plurality of optical/electrical conversion devices is two-dimensionally arrayed in the row and column directions and which converts an optically detected signal outputted from each of the optical/electrical conversion devices for each of the column into a digital signal, comprises a first step of storing the outputted digital signal in relation with the optical/electrical conversion device in the light-shielding region and a second step of calculating a difference between the outputted digital signal and a value stored in the first step in relation with the optical/electrical conversion device in the light-receiving region except the light-shielding region.
In the present invention, a read value inputted through each read circuit of an optical black line composed of one row of optical/electrical conversion devices in the row direction of the light-shielding region is stored as digital data, and later when reading data from an optical/electrical conversion device in the light-receiving region, a difference obtained by subtracting data for each column, stored in the storage device from the pure read value at that time is designated to be image data. The read value in the light-shielding region stored in the storage device includes column offset, which is unevenness among the read circuits, and the read value of an optical/electrical conversion device in the light-receiving region also includes column offset. Therefore, by outputting both the differences, column offset can be killed.
Thus, no noise, such as a vertically striped pattern, due to column offset occurs in an outputted image, and accordingly, the degradation of image quality can be prevented.
For example, there is no need to duplicate each read circuit provided for each column of a pixel, and accordingly, circuit scale does not increase.
The preferred embodiments of the present invention are described in detail below with reference to the drawings.
As shown in
As shown in
Therefore, one row in the row direction of the light-shielding region 20b is called an optical black line 21, and all pixels in the optical black line 21 become light-shielding pixels 21a to which light is never applied.
However, one row in the row direction of the light-receiving region 20a is called a light-receiving line 22, and all pixels in the light-receiving line 22 (except for those at each end of the light-shielding region 20b) become light-receiving pixel 22a which contribute to imaging.
Each two-dimensionally arrayed pixel unit (a light-shielding pixel 21a and a light-receiving pixel 22a) includes a photo-diode for converting inputted light into an electrical signal and a transistor for amplifying the output of the photo-diode, which are both manufactured in the CMOS process.
Each of the plurality of column read circuits 40 provided for each column of the plurality of pixels includes a column CDS 41 and a column ADC 42 which are both arrayed in the processing order of an optically/electrically converted signal outputted from the light-shielding pixel 21a or light-receiving pixel 22a included in the column.
The column CDS 41 comprises an amplifier 41a on the input side of the optically/electrically converted signal, an amplifier 41b on the output side, a clamp capacitor 41c provided between them and a control switch 41d for controlling the connection of the clamp capacitor 41c to a reference potential, which is not shown in
Specifically, by switching the control switch 41d off in synchronization with the reset of each pixel in the pixel array 20, offset voltage at the time of reset is stored in the clamp capacitor 41c, and by switching the control switch on at the time of the input of an optically/electrically converted signal, the optically/electrically converted signal is offset by the offset voltage and the killed optically/electrically converted signal is inputted to the column ADC 42 disposed after it through the amplifier 41b.
The column ADC 42 comprises a comparator 42a for converting the optically/electrically converted signal into digital data, using the optically/electrically converted signal outputted from the column CDS 41, a ramp waveform signal 42b and a clock signal 42c as input.
Specifically, in the comparator 42a, the clock signal 42c counts time until both levels intersect with each other after the optically/electrically converted signal and the inclined ramp waveform signal 42b which gradually decreases or increases as time elapses are synchronized and inputted, and this count value is serially outputted as digital output 42d with a prescribed bit width, indicating the size of the level (pixel luminance) of the optically/electrically converted signal.
In the latch array 50 disposed after the column read circuit 40, the same number of sets of a counter 50a which counts in synchronization with the digital output 42d serially outputted from the column ADC 42, and a black line latch 50b and a regular line latch 50c both for taking in one bit of the digital output 42d in synchronization with the count value of the counter 50a, as the bit width of the digital output 42d are provided.
Then, each bit of a digital output 42d corresponding to the light-shielding pixel 21a that belongs to the optical black line 21 is stored in the black line latch 50b, and each bit of a digital output 42d corresponding to the light -receiving pixel 22a that belongs to the light-receiving line 22 is stored in the regular line latch 50c.
The black line latch 50b and the regular line latch 50c are connected to the subtracter 51 through the bus 52. By outputting a bit string stored in a plurality of black line latches 50b and a bit string stored in a plurality of regular line latches 50c to the subtracter 51 through the bus 52 and subtracting the latter from the former in this subtracter 51, the data of the light-shielding pixel 21a stored in the black line latch 50b is subtracted from the data of the light-receiving pixel 22a stored in the regular line latch 50c, and the uneven characteristic (column offset) of each of the plurality of column read circuits 40 disposed for each column of the plurality of pixels in the pixel array 20 is killed. Then, the result of the subtraction is outputted to the image processor 90 disposed after the subtracter 51 as digital output 42e.
The image processor 90 is provided with a function to control the entire operation of the imaging device 10 to kill the column offset of the column read circuit 40 in this preferred embodiment and is further provided with a function to convert the digital output 42e outputted from the subtracter 51 into an image signal with an arbitrary rating, such as YUV, YCbCr, RGB or the like, and to output the signal.
One example of the function of the latch array 50 in this preferred embodiment is described below with reference to the drawings shown in
In the imaging operation of the pixel array 20, both scanning for each row from top to down in order by the horizontal synchronization scan circuit 32 synchronous with a vertical synchronization signal VSYNC and the scanning (transfer process) in the column direction by the horizontal synchronization scan circuit 32 of a plurality of segments of pixel data to be processed for each row by the column read circuit 40 are performed. The operation of outputting the result of both the scanning for one screen (one frame) is repeated in a prescribed cycle.
As shown in
Each pixel is reset while the horizontal synchronization signal is off, and as shown in the upper section of
Then, as shown in the flowchart of
As described above, in this preferred embodiment, by calculating the difference between the optically/electrically converted signal of the light-shielding pixel 21a in the optical black line 21 and the optically/electrically converted signal of the light-receiving pixel 22a in the light-receiving line 22 in both the latch array 50 and the subtracter 51 and outputting the difference to the image processor 90 in a configuration provided with a column read circuit 40 for each column in the pixel array 20, the influence of an uneven operational characteristic (column offset) in each column read circuit 40 can be eliminated from the optically/electrically converted signal of the light-receiving pixel 22a.
Specifically, since in each column, each optically/electrically converted signal of the light-shielding pixel 21a and light-receiving pixel 22a is outputted in a state including offset due to an uneven operational characteristic peculiar to the column read circuit 40 of the column, by calculating the difference between them using the latch array 50 and the subtracter 51, the column offset included the optically/electrically converted signal of the light-receiving pixel 22a can be eliminated and accordingly, the degradation of image quality, such as the occurrence of vertical stripes in an image outputted from the imaging device 10 and the like, can be surely prevented.
Since the digital output 42d of the light-shielding pixel 21a in the black line latch 50b is updated every time a frame is switched, the change with the lapse of time, of temperature and the like can be reflected in both the light-shielding pixel 21a and light-receiving pixel 22a which both are references. Therefore, the respective fixed pattern noise and column offset due to the temperature change of the light-shielding pixel 21a and light-receiving pixel 22a can be killed, and accordingly, the degradation of an output image due to an uneven characteristic among the column read circuits 40 can be prevented without being affected by the change with the lapse of time of environment and the like.
Therefore, there in no need to provide a plurality of column CDS circuits 40 in parallel in order to kill column offset, and circuit scale does not increase.
Next, the second preferred embodiment of the present invention is described with reference to
This second preferred embodiment differs from the above-mentioned first preferred embodiment only in that the data of the optically/electrically converted signal of the light-shielding pixel 21a of the optical black line 21 is stored in a storage device 70, and when processing the light-receiving pixel 22a, the data is read and the data is subtracted from the data of the light-receiving pixel 22a in a subtracter 71.
In the following description, only different components from the first preferred embodiment are described. The same reference numerals are attached to the same components, and their duplicate descriptions are omitted.
Specifically, this second preferred embodiment comprises a latch array 60 disposed after the column read circuit 40, a storage device 70 comprised of random-access memory (RAM) or the like that is composed of semiconductor memory, a subtracter 71 and a bus 63 for connecting the latch array 60, the storage device 70 and the subtracter 71 to each other.
As to the capacity of the storage device 70, it is passable if the capacity is N bits×H words when the number of pixels of the pixel array 20 is H and H dots in the horizontal and vertical directions, respectively, and the bit width of the digital value of one pixel of optically/electrically converted signal is N bits.
In the latch array 60, the same number of a pair of a first-stage latch 61 with one bit and a second-stage latch 62 with one bit, as the number of bits of the digital output 42d in the column read circuit 40 are provided in order to store the data of the optically/electrically converted signals of the current pixels in a row in the storage device 70 and to function as a buffer for consecutively processing pixels in subsequent rows in parallel.
Then, the bit string of the digital output 42d is taken in by each of the first-stage latch 61 according to count signal, count 0 through count n−1, synchronous with the clock signal 42c. The bit data of this first-stage latch 61 is shifted to the second-stage latch 62 according to a latch signal (latch) synchronous with the clock signal 42c and is collectively transferred to the storage device 70 or the subtracter 71 through the bus 63 in synchronization with the horizontal shift register signal HSR of the horizontal synchronization scan circuit 32.
The function of the second preferred embodiment is described below. As shown as an example in the flowchart of
Then, in synchronization with the horizontal synchronization signal AVH, the optically/electrically converted signal of the light-receiving pixel 22a in each column of the light-receiving line 22 is inputted to and processed in the column read circuit 40 in each column, and is transferred to the subtracter 71 through the latch array 60 and the bus 63 as digital output 42d (pixel data A) (step 214). Then, in synchronization with this transfer, the data (RAMO) of the light-shielding pixel 21a in the same column is read into the subtracter 71 from the storage device 70, and their difference (A-B) is calculated (step 215). Then, the operation of outputting the digital output 42e from which column offset is eliminated, to the image processor disposed after the subtracter 71 as the result of the calculation, is repeated for one frame while the horizontal synchronization signal AVH is on.
As described above, in this second preferred embodiment, since a storage device 70 is provided separately from the column read circuit 40 to store the data of the light-shielding pixel 21a, the scale of the latch array 60 linked to the column read circuit 40 can be reduced.
Specifically, in the first preferred embodiment, since the column read circuit 40 is arrayed for each column, the width of disposition region of circuits, such as the column read circuit, latch array 60 and the like is restricted. However, in this second preferred embodiment, since the circuit scale of the latch array 60 and the like is reduced, the disposition width of circuit components, such as the column read circuit 40, latch array 60 and the like does not increase, and accordingly, the number of pixels can be easily increased thanks to the reduction of a pixel pitch.
Next, the third preferred embodiment of the present invention is described with reference to
This third preferred embodiment differs from the above-mentioned second preferred embodiment only in that an offset calculation circuit 80 for processing the digital output 42d of the optically/electrically converted signal of the light-shielding pixel 21a is provided between the bus 63 and the storage device 70.
Specifically, in this third preferred embodiment, the digital output 42d of the light-shielding pixel 21a is not stored in the storage device 70 without any process, but the difference between the relevant digital output 42d and its maximum or minimum value is calculated using the offset calculation circuit 80. By doing so, the amount of data is reduced. Then, the reduced data is stored in the storage device 70, and is restored to the original value when reading the data.
The offset calculation circuit 80 comprises a storage device 81 composed of flip-flops with the bit width of the digital output 42d and the like, a comparator for comparing the digital output 42d coming from the bus 63 with the value stored in the storage device 81, a subtracter 83 for calculating the difference between the digital output 42d coming from the bus 63 and the value stored in the storage device 81, and an adder 84 for reproducing the original value of the digital output 42d by summing the data read from the storage device 70 and the value stored in the storage device 81.
In the process of reading the first light-shielding pixel 21a in order to search for a maximum/minimum value, which is described later, the output of each light-shielding pixel 21a included in the optical black line 21 is read in order in the array direction and is stored in the storage device 81. Then, the comparator 82 determines which is larger, the value stored in the storage device 81 or the output of a subsequent light-shielding pixel 21a. If the value stored in the storage device 81 is smaller than the output of the subsequent light-shielding pixel 21a, the contents of the storage device 81 are overwritten by the output of the subsequent light-shielding pixel 21a, and finally, the maximum value remains in the storage device 81. If the size determination is reversed, the minimum value can remain in the storage device 81.
As described above, in this third preferred embodiment, the optical black line 21 must be read in order to search for the maximum or minimum value before storing the data of the light-shielding pixel 21a in the storage device 70.
Specifically, as shown in
Such a series of processes are described below with reference to the flowchart shown in
Then, the digital output 42d of each light-receiving pixel 22a of the regular light-receiving line 22 (pixel data A) is processed (step 226). Simultaneously, in the offset calculation circuit 80, the value (ΔB) of a corresponding light-shielding pixel 21a is read from the storage device 70, and by summing the value (ΔB) and the value of the storage device 81, the original pixel data B of the light-shielding pixel 21a is reproduced (step 227). Then, the difference (A−B) is calculated by the subtracter 71, and the column offset of the pixel data A of the light-receiving pixel 22a is killed (step 228). Then, the pixel data A whose column offset is killed is outputted to the image processor disposed after the subtracter 71 as digital output 42e.
As described above, in this third preferred embodiment, the maximum or minimum value of the respective digital outputs 42d of a plurality of light-shielding pixels 21a is calculated as a reference value, and the difference between the value of the digital output 42d of the light-shielding pixel 21a and the reference value is stored in the storage device 70. Therefore, the capacity of the storage device 70, for storing the data of the digital output 42d of the light-shielding pixels 21a can be reduced.
Therefore, the degradation of an output image due to an uneven characteristic among the column read circuits 40 can be prevented without the increase of the circuit scale of the imaging device 10.
Although in the above-mentioned preferred embodiments, the maximum or minimum value is used as a reference value, the median of the maximum and minimum values can also be used as a reference value and is stored in the storage device 81.
The present invention is not limited to the configurations shown in the above-mentioned preferred embodiments, and any variations and any modifications are possible as long as the subject matter of the present invention is not deviated.
According to the present invention, in an imaging device with a configuration in which the read processing circuit of optically/electrically converted signals are disposed for each row or column of a plurality of two-dimensionally arrayed pixels, the degradation of an output image due to an uneven characteristic among the read processing circuits can be prevented.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-197333 | Jul 2004 | JP | national |
