Claims
- 1. A high speed image forming system for creating a digitally defined image on a photoreceptor surface, comprising:
- 1) an array including a plurality of pixel generators each capable of selectively generating a light beam of dot-like configuration and arranged in adjacent positions such that the light beams therefrom can be focused to illuminate uniformly sized adjacent pixel areas within an image area on the photoreceptor surface to produce an image;
- 2) means for producing relative motion through a range of velocities between said array and the photoreceptor surface;
- 3) a latch pulse generator for producing latch pulses synchronized to the relative motion between said array and the photoreceptor;
- 4) driving circuits connected to each of said pixel generators to cause the generators to illuminate;
- 5) data register means receiving said latch pulses including separate registers, one register for each of said driving circuits for holding data for said driving circuits to determine pixel areas to be illuminated by said pixel generators, said registers being organized into distinct groups;
- 6) memory means for storing compensation information based on differences in optical output power of individual pixel generators in the array;
- 7) a plurality of data input channels connected in parallel, one for each of said groups of data register means,
- (a) said data input channels supplying pixel writing data to said memory means;
- (b) said memory means supplying compensated pixel driving data, in response to said writing data, to said data register means;
- 8) clock means for controlling transfer of writing data from said data input channels;
- 9) means for generating timebase pulses;
- 10) comparator means controlled by said timebase pulses to transfer a compensated pixel driving data to said driving circuits, wherein said timebase pulses vary the length of on-time of the pixel generators depending upon the compensation information, said comparator means synchronising the timebase pulses to the latch pulses from said latch pulse generator so that there are a same number of timebase pulses centered between successive latch pulses, wherein said latch pulses control a rate of transfer of data from said data register means.
- 2. A system as defined in claim 1, including
- a bit-mapped memory adapted to store lines of pixel writing information for an image to be reproduced,
- means for transferring data from said bit-mapped memory to said data input channels including means controlled by said clock means for scanning simultaneously different selected portions of a line of said bit-mapped memory and for applying the data information in parallel to said data input channels to transfer a line of pixel writing information in parallel paths of data information each applied simultaneously in serial fashion to all data storage registers of all the modules.
- 3. A system as defined in claim 1, wherein said
- memory means has memory locations for each potential pixel in an image area, further including
- a raster image processor for creating bit-mapped image information and placing such image information in said memory means, and
- means for reading image information one line at a time from said memory means and transmitting such information to said data input channels for placing such information in said data storage registers.
RELATED APPLICATION
This application is a division of application Ser. No. 07/457,433 filed 27 Dec. 1989, U.S. Pat. No. 5,121,146.
US Referenced Citations (15)
Divisions (1)
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Number |
Date |
Country |
Parent |
457433 |
Dec 1989 |
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