Patent Application
20220385846
The present disclosure relates to an imaging element and an imaging apparatus.
A configuration is known in which driving power for driving light receiving elements is supplied to, using a charge pump, a pixel array in which the light receiving elements (for example, photodiodes) are arranged in a matrix. As one of the configurations of the charge pump, there is known a charge pump in which a switching signal that is switched on/off according to a clock is applied to a capacitor to accumulate electric charges in the capacitor and, for example, a high voltage is output with respect to an input voltage.
In the above-described pixel array, when a driving operation is simultaneously executed in all the light receiving elements effective for imaging, a large potential fluctuation occurs in the driving power for driving the light receiving elements. As an example, when a global shutter scheme is adopted as an imaging scheme, for example, a reset operation for the light receiving elements or a transfer operation for transferring electric charges accumulated in the light receiving elements by exposure to a capacitor is simultaneously executed in all the light receiving elements effective for imaging included in the pixel array. A large potential fluctuation occurs in the driving power. When the charge pump is configured according to the peak of the potential fluctuation, unnecessary power is consumed in a period other than a period in which the potential fluctuation occurs.
An object of the present disclosure is to provide an imaging element and an imaging apparatus capable of reducing power consumption in a charge pump that supplies driving power to a pixel array.
For solving the problem described above, an imaging element according to one aspect of the present disclosure has an imaging unit in which pixels including a light receiving element are arrayed; a drive unit that generates a drive signal for driving the pixels; a charge pump circuit that generates electric power for driving the drive unit; and a control unit that controls, according to an operation of the imaging unit, a driving capability of the charge pump circuit to drive the drive unit.
Embodiments of the present disclosure are explained in detail below with reference to the drawings. Note that, in the embodiments explained below, redundant explanation is omitted by denoting the same parts with the same reference numerals and signs.
Embodiments of the present disclosure are explained in detail below according to the following order.
First, a technique applicable to the embodiments is explained.
Here, as the electronic equipment 1, a digital still camera, a digital video camera, a cellular phone with an imaging function, a smartphone, and the like can be applied. A monitoring camera, a vehicle-mounted camera, a medical camera, and the like can also be applied as the electronic equipment 1.
The imaging element 4 includes, for example, a plurality of photoelectric conversion elements arranged in a matrix array. The photoelectric conversion element converts received light into electric charges with photoelectric conversion. The imaging element 4 includes a drive circuit that drives the plurality of photoelectric conversion elements, a signal processing circuit that reads electric charges respectively from the plurality of photoelectric conversion elements and generates image data based on the read electric charges, and a power supply circuit for supplying power to the drive circuit.
The optical system 2 includes a main lens by a combination of one or a plurality of lenses and a mechanism for driving the main lens and forms an image of image light (incident light) from an object on a light receiving surface of the imaging element 4 via the main lens. The optical system 2 includes an autofocus mechanism that adjusts a focus according to a control signal and a zoom mechanism that changes a zoom ratio according to a control signal. The electronic equipment 1 may be configured such that the optical system 2 is detachably attachable and can be replaced with another optical system 2.
The image processing unit 5 executes predetermined image processing on image data output from the imaging element 4. For example, the image processing unit 5 is connected to the memory 6 by a frame memory or the like and writes the image data output from the imaging element 4 in the memory 6. The image processing unit 5 executes predetermined image processing on the image data written in the memory 6 and writes the image data subjected to the image processing in the memory 6 again.
The storing unit 7 is a nonvolatile memory such as a flash memory or a hard disk drive and stores the image data output from the image processing unit 5 in a nonvolatile manner. The display unit 8 includes a display device such as a liquid crystal display (LCD) and a drive circuit that drives the display device and can display an image based on the image data output by the image processing unit 5. The I/F unit 9 is an interface for transmitting the image data output from the image processing unit 5 to the outside. For example, a universal serial bus (USB) can be applied as the I/F unit 9. Not only this, but the I/F unit 9 may be an interface connectable to a network by wired communication or wireless communication.
The input device 12 includes an operator for receiving a user input. If the electronic equipment 1 is, for example, a digital still camera, a digital video camera, a cellular phone with an imaging function, or a smartphone, the input device 12 can include a shutter button for instructing imaging by the imaging element 4 or an operator for realizing the function of the shutter button.
The control unit 3 includes, for example, a processor such as a central processing unit (CPU), a read only memory (ROM), and a random access memory (RAM) and controls the entire operation of the electronic equipment 1 using the RAM as a work memory according to a program stored in the ROM in advance. For example, the control unit 3 can control the operation of the electronic equipment 1 according to the user input received by the input device 12. The control unit 3 can control the autofocus mechanism in the optical system 2 based on an image processing result of the image processing unit 5.
Note that the imaging element 4 according to the first embodiment is a CMOS image sensor (CIS) in which the pixel array unit 100, the vertical scanning unit 110, the column processing unit 114, the horizontal scanning unit 115, the drive signal scanning unit 120, and the charge pump 122 are formed by a complementary metal oxide semiconductor (CMOS). In the imaging element 4 according to the first embodiment, the pixel array unit 100, the vertical scanning unit 110, the column processing unit 114, the horizontal scanning unit 115, the drive signal scanning unit 120, and the charge pump 122 are formed on one chip.
In the pixel array unit 100, pixels 10 including one or more photoelectric conversion elements are arranged in a matrix array. That is, the pixel array unit 100 is configured as an imaging unit in which the pixels 10 including photoelectric conversion elements as light receiving elements are arranged. Note that, in
The vertical scanning unit 110 includes a vertical address setting unit 111 and a vertical drive unit 112. The vertical address setting unit 111 selects the pixel signal line 11 to be driven from the pixel signal lines 11 according to a control signal supplied from the drive signal scanning unit 120 explained below. The vertical drive unit 112 includes amplifiers 113 for supplying a drive signal to the pixel signal lines 11 to correspond to the pixel signal lines 11. The amplifiers 113 are driven by a positive potential power supply VDD and a negative potential power supply VRL. The pixels 10 are driven row by row by a plurality of drive signals supplied from the vertical drive unit 112 via the amplifiers 113 and the pixel signal lines 11.
For example, the pixels 10 perform exposure for generating and accumulating electric charges corresponding to received light according to the drive signals. The pixels 10 output the electric charges accumulated by the exposure as pixel signals, which are electric signals, according to the drive signals. The vertical scanning unit 110 can simultaneously drive all the pixels 10 included in the pixel array unit 100 to an exposure state.
Vertical signal lines VSL are respectively connected to the pixels 10 for each of columns. The vertical signal lines VSL are connected to the column processing unit 114. The pixel signal read from the pixels 10 are supplied to the column processing unit 114 via the vertical signal lines VSL for each of columns.
The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120 explained below. The column processing unit 114 includes a signal processing circuit that applies predetermined signal processing such as correlated double sampling (CDS) processing for removing a noise component to the pixel signals supplied from the vertical signal lines VSL.
For example, as an AD converter, a single-slope AD converter that compares a pixel signal supplied from the pixel 10 via the vertical signal line VSL with a signal (referred to as a ramp signal RAMP), a voltage of which increases or decreases stepwise based on a straight line and performs AD conversion for the pixel signal can be applied. The AD converter generates two digital values by P-phase reading and D-phase reading explained below through AD conversion processing and executes the CDS processing explained above based on the two digital values. For example, the AD converter applies filter processing by a filter (referred to as a CDS filter) having a predetermined cutoff frequency to the two digital values and executes the CDS processing explained above.
The horizontal scanning unit 115 scans, in a row direction, the pixel signals processed by AD converters and signal processing circuits in the column processing unit 114 according to the control by the drive signal scanning unit 120. The scanned pixel signals are supplied to a bus and output from the bus to the outside of the imaging element 4 via a terminal 130 as an imaging signal via a buffer amplifier 116.
The drive signal scanning unit 120 includes a sequencer 121. The drive signal scanning unit 120 is supplied with a master clock MCLK and various data from the outside respectively via terminals 132 and 133. The sequencer 121 generates mode signals MODE each indicating an operation mode corresponding to each of the operations of the pixel array unit 100 based on the master clock MCLK and the data supplied to the drive signal scanning unit 120. The pixel array unit 100 is driven, based on a period indicated by an operation mode, to execute an operation corresponding to the operation mode.
The drive signal scanning unit 120 generates, based on the master clock MCLK and the operation mode, a control signal for controlling timing for the vertical address setting unit 111 to output the drive signals. The drive signal scanning unit 120 supplies the generated control signal to the vertical address setting unit 111.
The drive signal scanning unit 120 generates an operation clock CPCLK for driving the charge pump 122 explained below based on the master clock MCLK and supplies the generated operation clock CPCLK to the charge pump 122. The drive signal scanning unit 120 supplies mode signals MODE generated by the sequencer 121 to the charge pump 122.
As explained in detail below, the charge pump 122 includes a pumping capacitor and a switch circuit. The charge pump 122 schematically charges and boosts the pumping capacitor with a pumping operation corresponding to control of the switch circuit based on the operation clock CPCLK and outputs a boosted voltage VCP. The voltage VCP is once output from the imaging element 4 via a terminal 134, smoothed by a capacitor 123, and supplied from the terminal 131 to the imaging element 4 as the negative potential power supply VRL for driving the vertical drive unit 112 explained above.
As explained above, the vertical drive unit 112 functions as a drive unit that generates a drive signal for driving the pixels 10 included in the pixel array unit 100. The charge pump 122 generates electric power for driving the vertical drive unit 112. The drive signal scanning unit 120 functions as a control unit that controls, according to the operation of the pixel array unit 100, a driving capability of the charge pump 122 to drive the vertical drive unit 112.
Subsequently, a configuration of the pixel 10 applicable to the first embodiment is explained.
In
Note that, although not illustrated in
The pixel 10 includes, for example, a PN-junction photodiode PD as the photoelectric conversion element. The pixel 10 is configured by a complementary metal oxide semiconductor (CMOS) circuit and includes an overflow gate (OFG) transistor TR0, transfer transistors TR1 and TR2, a reset transistor TR3, an amplification transistor TR4, and a read path selection transistor TR5, which are respectively N-type metal oxide semiconductor (MOS) transistors.
In the pixel 10, a cathode of the photodiode PD is connected to a connection point where a source of the overflow gate (OFG) transistor TR0 and a source of the transfer transistor TR1 are connected. A drain of the OFG transistor TR0 is connected to a power supply line of the positive voltage power supply VDD. A drain of the transfer transistor TR1 is connected to a connection point where a capacitor MEM and a source of the transfer transistor TR2 are connected.
The drive signal TRG1, which is, for example, a pulse, is supplied to a gate of the transfer transistor TR1 from the vertical drive unit 112 via the signal line 112. The drive signal OFG, which is, for example, a pulse, is supplied to a gate of the OFG transistor TR0 from the vertical drive unit 112 via the signal line 111. The transfer transistor TR1 and the OFG transistor TR0 are respectively turned on when the drive signals TRG1 and OFG are in a high state and are turned off when the transfer pulse TG is in a low state.
The drive signal TRG2, which is, for example, a pulse, is supplied to a gate of the transfer transistor TR2 via the signal line 113. The transfer transistor TR2 is turned on when the drive signal TRG2 is in the high state and is turned off when the drive signal TRG2 is in the low state.
Note that the drive signals OFG and TRG1 are simultaneously supplied to all the rows of the pixels 10 included in the pixel array unit 100. On the other hand, the transfer pulse TRG2 supplied to the transfer transistor TR2 is sequentially supplied for the rows.
A floating diffusion layer FD is connected to a connection point where a drain of the transfer transistor TR2 and a source of the reset transistor TR3 are connected. The power supply line of the positive voltage power supply VDD is connected to a drain of the reset transistor TR3. A drive signal RST, which is a pulse, is supplied to a gate of the reset transistor TR3 via a not-illustrated signal line. The reset transistor TR3 is turned on when the drive signal RST is in the high state and is turned off when the drive signal RST is in the low state.
A gate of the amplification transistor TR4 is connected to the floating diffusion layer FD. The power supply line of the power supply VDD is connected to a drain of the amplification transistor TR4 and a drain of the read path selection transistor TR5 is connected to a source of the amplification transistor TR4. A source of the read path selection transistor TR5 is connected to the vertical signal line VSL. The drive signal SEL is supplied to a gate of the read path selection transistor TR5 via the signal line 114. The read path selection transistor TR5 is turned on when the drive signal SEL is in the high state and is turned off when the drive signal SEL is in the low state.
In the configuration of the pixel 10 illustrated in
At timing immediately before the exposure at the start of one frame period, the vertical scanning unit 110 simultaneously sets the drive signals OFG of the rows to the high state according to the control signal supplied from the drive signal scanning unit 120 and sets the OFG transistors TR0 included in all the pixels 10 in the pixel array unit 100 to an ON state. At this time, the drive signal TRG1 is set in the low state and the transfer transistor TR1 is set to an OFF state. Accordingly, in the pixels 10, electric charges accumulated in the photodiode PD are absorbed into the power supply line of the power supply VDD and the photodiode PD is initialized. When the drive signal OFG changes to the low state and the OFG transistor TR0 changes to the OFF state, exposure of the photodiode PD for one frame is started.
According to a control signal supplied from the drive signal scanning unit 120, the vertical scanning unit 110 sets the drive signal OFG to the low state and maintains the low state of the drive signal TRG1 during exposure. According to the control signal supplied from the drive signal scanning unit 120, the vertical scanning unit 110 sets the drive signal TRG2 to the low state and sets the drive signal RST to the high state during exposure, sets the transfer transistor TR2 to the OFF state, and sets the reset transistor TR3 to the ON state, and sucks out the electric charges of the floating diffusion layer FD to the power supply line of the power supply VDD to initialize the floating diffusion layer FD. Further, by setting the drive signal SEL to the high state, a signal by a voltage in a reset level of the floating diffusion layer FD is output to the vertical signal line VSL. This signal is a signal including offset noise. Reading of this signal from the floating diffusion layer FD is referred to as P-phase (Pre-Charge) reading and a period in which the P-phase reading is performed is referred to as a P-phase period.
Thereafter, according to a control signal supplied from the drive signal scanning unit 120, the vertical scanning unit 110 sets the drive signal RST to the low state to set the reset transistor TR3 to the OFF state and sets the drive signal TRG2 to the high state to set the transfer transistor TR2 to the ON state. The vertical scanning unit 110 sets the drive signal TRG1 to the low state to set the transfer transistor TR1 to the OFF state and separates the capacitor MEM and the photodiode PD. Accordingly, for example, reading processing for the electric charges accumulated in the capacitor MEM in the immediately preceding frame period is executed. The electric charges read from the capacitor MEM are accumulated in the floating diffusion layer FD.
According to a control signal supplied from the drive signal scanning unit 120, the vertical scanning unit 110 sets the drive signal TRG2 to the low state, sets the drive signal SEL to the high state, sets the transfer transistor TR2 to the OFF state, and sets the read path selection transistor TR5 to the ON state at timing when the accumulation of the electric charges in the floating diffusion layer FD is completed. Accordingly, a signal obtained by converting the electric charges accumulated from the floating diffusion layer FD into a voltage is read out, amplified by the amplification transistor TR4, and output to the vertical signal line VSL via the read path selection transistor TR5. This signal is a signal including offset noise and a pixel signal. Reading of this signal is referred to as D-phase (Data Phase) reading and a period in which the D-phase reading is performed is referred to as a D-phase period.
The reading processing for all the rows of the pixel array unit 100 is completed within one frame period.
When the exposure of the photodiode PD ends, the vertical scanning unit 110 sets the drive signal TRG2 to the low state to set the transfer transistor TR2 to the OFF state and sets the drive signal TRG1 to the high state to set the transfer transistor TR1 to the ON state according to a control signal supplied from the drive signal scanning unit 120. Accordingly, the electric charges accumulated in the photodiode PD by the exposure are transferred to the capacitor MEM. The transferred electric charges are accumulated in the capacitor MEM. According to a control signal supplied from the drive signal scanning unit 120, the vertical scanning unit 110 sets the drive signal TRG1 to the low state at timing when the accumulation of the electric charges in the capacitor MEM is completed.
In the next frame period, the vertical scanning unit 110 sets the drive signal OFG to the high state and sets the drive signal TRG1 to the low state according to a control signal supplied from the drive signal scanning unit 120 and executes initialization processing for the electric charges accumulated in the photodiode PD by the exposure in the immediately preceding frame. According to a control signal supplied from the drive signal scanning unit 120, the vertical scanning unit 110 sets the drive signal OFG to the low state at timing when the initialization processing ends and exposure is started. The drive signal TRG1 is maintained in the low state during the exposure.
As explained above, by using the OFG transistor TR0, the transfer transistor TR1, and the capacitor MEM, it is possible to realize a global shutter that executes exposure in the pixels 10 included in the pixel array unit 100 all at once.
Subsequently, a first embodiment of the present disclosure is explained. In the first embodiment, a frequency of a clock signal for controlling the pumping operation in the charge pump 122 is switched based on an operation mode of the pixel array unit 100. This makes it possible to suppress power consumption in the charge pump 122.
The frequency divider 200 divides a clock signal CPCLK supplied from the drive signal scanning unit 120 and generates a plurality of clock signals having different frequencies. Note that, instead of the frequency divider 200, a multiplier that outputs a signal having a frequency of, for example, an integral multiple of the frequency of the input signal may be used. The plurality of clock signals output from the frequency divider 200 is input to the selector 201.
Mode signals MODE output from the sequencer 121 of the drive signal scanning unit 120 is input to the frequency switching control unit 202. The frequency switching control unit 202 generates a frequency switching signal FSEL based on a combination of the mode signals. According to the frequency switching signal FSEL, the selector 201 selects one clock signal from a plurality of clock signals input from the frequency divider 200 and outputs the selected clock signal as a clock signal PPCLK for controlling the pumping operation in the charge pump 122 and driving the charge pump 122.
A frequency of the clock signal PPCLK greatly affects a driving capability of the charge pump 122 to drive the vertical drive unit 112. For example, as the frequency of the clock signal PPCLK is higher, charging and discharging for the capacitor Cfly are performed at higher speed and the driving capability by the charge pump 122 increases.
On the other hand, in
An output voltage Vout of the charge pump 122 is extracted from the other end of the switch circuit 212a. One end of the switch circuit 211b is connected to the power supply line of the positive voltage power supply VDD and the other end is connected to one end of the switch circuit 212b. The other end of the switch circuit 212b is connected to the output of the amplifier 204.
A reference voltage Vref0 generated by the reference voltage generation unit 203 is input to a (+) input end of the amplifier 204. A voltage (referred to as a divided voltage) obtained by dividing a reference voltage Vrefout generated by the reference voltage generation unit 205 by the voltage-dividing resistors R1 and R2 with respect to the output voltage Vout is input to the (−) input end of the amplifier 204. The amplifier 204 outputs a difference between the reference voltage Vref0 input to the (+) input end and the divided voltage input to the (−) input end.
One end of the capacitor Cfly functioning as a pumping capacitor is connected to a connection point where the other end of the switch circuit 211a and one end of the switch circuit 212a are connected. The other end of the capacitor Cfly is connected to a connection point CB where the other end of the switch circuit 211b and one end of the switch circuit 212b are connected.
The switch circuits 211a and 211b and the switch circuits 212a and 212b are respectively controlled to open and close according to the clock signal PPCLK output from the selector 201. Open and close states of the switch circuits 211a and 211b are controlled to be the same according to the clock signal PPCLK before being input to the inverter 213. Open and close states of the switch circuits 212a and 212b are controlled to be the same according to the clock signal PPCLK input via the inverter 213. That is, the operations of the switch circuits 211a and 211b and the switch circuits 212a and 212b are controlled exclusively from each other. For example, when the clock signal PPCLK is in the high state, the switch circuits 211a and 211b are in the ON state and the switch circuits 212a and 212b are in the OFF state and, when the clock signal PPCLK is in the low state, the switch circuits 211a and 211b are in the OFF state and the switch circuits 212a and 212b are in the ON state.
With the switch circuits 211a and 211b are in the ON state and the switch circuits 212a and 212b in the OFF state, electric charges are charged in the capacitor Cfly. When the switch circuits 211a and 211b are in the OFF state and the switch circuits 212a and 212b are in the ON state, a voltage corresponding to the electric charges charged in the capacitor Cfly is extracted from the other end of the switch circuit 212a. By repeating this operation, electric charges are accumulated in the capacitor Cfly, a voltage across the capacitor Cfly is boosted, and the voltage VCP is generated. The voltage VCP is smoothed by the capacitor 123 and output as the output voltage Vout of the charge pump 122.
A difference between the output voltage Vout of the charge pump 122 and the reference voltage Vrefout generated by the reference voltage generation unit 205 is divided by the voltage-dividing resistors R1 and R2 and input to the (−) input end of the amplifier 204. In the charge pump 122 illustrated in
Further, the charge pump 122 illustrated in
In the period of the operation mode in which large power is instantaneously required, the electric charges accumulated in the capacitor Cfly are suddenly discharged. Therefore, by setting the frequency of the clock signal PPCLK to a higher frequency in this period, the state of the capacitor Cfly can be restored in a shorter time.
The configuration of the frequency divider 200 is not particularly limited if the configuration is a configuration for digitally performing frequency division. However, for example, a configuration including a general flip-flop circuit or a configuration including a counter circuit can be applied.
Note that, in the following explanation, when it is unnecessary to distinguish the clock signals DCLK(L), DCLK(M), and DCLK(H), these clock signals DCLK(L), DCLK(M), and DCLK(H) are collectively described as a clock signal DCLK as appropriate.
The frequency switching control unit 202 outputs the frequency switching signal FSEL for selecting one clock signal DCLK from the three clock signals DCLK(L), DCLK(M), and DCLK(H) according to the mode signals MODE explained below. The frequency switching control unit 202 includes four-input AND circuits 2020a, 2020b, and 2020c, a three-input NOR circuit 2021, and a two-input OR circuit 2022. In the example illustrated in
The mode signals MODE supplied to the frequency switching control unit 202 are four kinds, that is, a mode signal MODE(bk), a mode signal MODE(rd), a mode signal MODE (gr/ts), and a mode signal MODE(gs). The mode signal MODE(bk) indicates an operation mode in a blank period. The mode signal MODE(rd) indicates an operation mode in a read period. The mode signal MODE(gr/ts) indicates an operation mode in a global reset and transfer period. The mode signal MODE(gs) indicates an operation mode in a global shutter period. Details of the operation modes are explained below.
In
An output of the AND circuit 2020a is supplied to the selector 201 as a frequency switching signal FSEL #0 for selecting the clock signal DCLK(L) and is input to a first input end of the three-input NOR circuit 2021. An output of the AND circuit 2020b is input to a first input end of the two-input OR circuit 2022 and is input to a second input end of the NOR circuit 2021. An output of the AND circuit 2020c is supplied to the selector 201 as a frequency switching signal FSEL #2 for selecting the clock signal DCLK(H) and is input to a third input end of the three-input NOR circuit 2021. An output of the NOR circuit 2021 is input to a second input end of the OR circuit 2022. An output of the OR circuit 2022 is supplied to the selector 201 as a frequency switching signal FSEL #1 for selecting the clock signal DCLK(M).
Table 1 illustrates an example of a truth table in the frequency switching control unit 202 illustrated in
In Table 1, rows correspond to the operation modes of the pixel array unit 100 and indicate the operation modes of blank, read, global reset and transfer, and global shutter from the top.
A period in which the operation mode is blank (hereinafter referred to as blank period) is, for example, an operation mode period in which the AD converter included in the column processing unit 114 is not operating. Processing such as transfer of an imaging signal to the outside of the imaging element 4 is allocated to the operation mode period. In the blank period, read processing from the pixels 10 and the like are not performed and access to transistors included in the pixels 10 is not performed.
A period in which the operation mode is read (hereinafter referred to as read period) is an operation mode period in which read processing for reading a pixel signal from the pixels 10 is executed and access to the transistors included in the pixels 10 is performed. More specifically, in the read period, the transfer transistor TR2 set to the ON state and the transfer transistor TR1 is set to the OFF state and electric charges are transferred from the capacitor MEM to the floating diffusion layer FD. The electric charges transferred to the floating diffusion layer FD are converted into a voltage by the amplification transistor TR4. Further, in the read period, the read path selection transistor TR5 is set to the ON state. The voltage obtained by converting the electric charges with the amplification transistor TR4 is output to the vertical signal line VSL as a pixel signal. Furthermore, in the read period, the column processing unit 114 converts the pixel signal for each row supplied via the vertical signal line VSL into an imaging signal.
A period (hereinafter referred to as global reset and transfer period) in which the operation mode is the global reset and transfer is an operation mode period in which a reset operation for the floating diffusion layer FD, the capacitor MEM, and the photodiode PD for the pixels 10 is executed. Access to the transistors included in the pixels 10 is performed. More specifically, in the global reset and transfer period, the transfer transistor TR2 and the reset transistor TR3 are set to the ON state and the transfer transistor TR1 is set to the OFF state and the capacitor MEM and the floating diffusion layer FD are reset. Thereafter, the transfer transistor TR2 and the reset transistor TR3 are switched from an OFF normal state to the ON state, the transfer transistor TR1 is switched from the OFF state to the ON state. The electric charges accumulated in the photodiode PD by exposure are transferred to the capacitor MEM. Thereafter, the OFG transistor TR0 is switched from the OFF state to the ON state to reset the photodiode PD (close the shutter).
A period (hereinafter referred to as global shutter period) in which the operation mode is the global shutter is an operation mode period in which the exposure is started (the shutter is opened) in the pixels 10 included in the pixel array unit 100 all at once. Access to the transistors included in the pixel 10 is performed. More specifically, in the global shutter period, the OFG transistor TR0 is switched from the ON state to the OFF state to start exposure.
Referring back to Table 1, in Table 1, first to fourth columns from the left respectively indicate states of the mode signals MODE(br), MODE(rd), MODE(gr/ts), and MODE(gs) for the respective operation modes. In Table 1, “L” indicates a low state of a signal and “H” indicates a high state of the signal. Fifth to seventh columns from the left respectively indicate states of the frequency switching signals FSEL #2, FSEL #1, and FSEL #0 for switching to the clock signals DCLK(H), DCLK(M), and DCLK(L).
In the blank period, as explained above, there is no access to the transistors included in the pixel 10. Therefore, power consumption in the pixels 10 is small and power consumption of the pixel array unit 100 as a whole is also small. Therefore, logic is configured such that the charge pump 122 can be driven at the low frequency and a frequency of the clock signal PPCLK for controlling the pumping operation in the charge pump 122 is the low frequency.
For example, in Table 1, in the blank period, the mode signals MODE(bk), MODE(rd), MODE(gr/ts), and MODE(gs) are respectively set to the states of “H”, “L”, “L”, and “L”. In the states of the mode signals MODE(bk), MODE(rd), MODE(gr/ts), and MODE(gs), logic is configured such that the frequency switching signals FSEL #2, FSEL #1, and FSEL #0 respectively become “L”, “L”, and “H”, the frequency switching signal FSEL #0 is enabled, and the clock signal DCLK(L) having the lowest frequency is selected.
In the read period, access to the transistors included in the pixel 10 is included. However, the access is by an operation for outputting a pixel signal read in the pixels 10 to the vertical signal line VSL. Therefore, the access is performed for each row and does not occur at the same time in the pixels 10 included in the pixel array unit 100. Therefore, the power consumption of the entire pixel array unit 100 does not increase at certain timing. Therefore, logic is configured such that the charge pump 122 can be driven at a normal (medium) frequency and a frequency of the clock signal PPCLK for controlling the pumping operation in the charge pump 122 is the normal (medium) frequency.
For example, in Table 1, during the read period, the mode signals MODE(bk), MODE(rd), MODE(gr/ts), and MODE(gs) are respectively set to the states of “L”, “H”, “L”, and “L”. In the states of the mode signals MODE(bk), MODE(rd), MODE(gr/ts), and MODE(gs), logic is configured such that the frequency switching signals FSEL #0, FSEL #1, and FSEL #2 respectively become “L”, “H”, and “L”, the frequency switching signal FSEL #1 is enabled, and the clock signal DCLK(M) having the medium frequency is selected.
In the global reset and transfer period and the global shutter period, access to the transistors included in the pixel 10 is included. In these periods, access to the transistors included in the pixel 10 is included. The access includes access simultaneously executed in the pixels 10 included in the pixel array unit 100. Therefore, the power consumption of the entire pixel array unit 100 instantaneously increases at timing of the access. In this case, it is desirable that the electric charges accumulated in the capacitor Cfly of the charge pump 122 are instantaneously discharged, and a charge amount of the capacitor Cfly is recovered in a short time. Therefore, in this global reset and transfer period, logic is configured such that a frequency of the clock signal PPCLK for controlling the pumping operation in the charge pump 122 is the high frequency.
For example, in Table 1, in the global reset and transfer period, the mode signals MODE(bk), MODE(rd), MODE(gr/ts), and MODE(gs) are respectively set to the states of “L”, “L”, “H”, and “L”. In the states of the mode signals MODE(bk), MODE(rd), MODE(gr/ts), and MODE(gs), logic is configured such that the frequency switching signals FSEL #0, FSEL #1, and FSEL #2 respectively become “H”, “L”, and “L”, the frequency switching signal FSEL #2 is enabled, and the clock signal DCLK(H) having the highest frequency is selected.
Similarly, when the operation mode is the global shutter period, the mode signals MODE(bk), MODE(rd), MODE(gr/ts), and MODE(gs) are respectively set to the states of “L”, “H”, “L”, and “H”. In the states of the mode signals MODE(bk), MODE(rd), MODE(gr/ts), and MODE(gs), logic is configured such that the frequency switching signals FSEL #0, FSEL #1, and FSEL #2 respectively become “H”, “L”, and “L”, the frequency switching signal FSEL #2 is enabled, and the clock signal DCLK(H) having the highest frequency is selected.
Note that, when the operation mode is other than the operation modes explained above and a combination of the mode signals MODE(bk), MODE(rd), MODE(gr/ts), and MODE(gs) is other than the combinations explained above, the frequency of the clock signal PPCLK is set to the low frequency. In the example illustrated in Table 1, in this case, logic is configured such that the frequency switching signals FSEL #2, FSEL #1, and FSEL #0 respectively become “L”, “L”, and “H”, the frequency switching signal FSEL #0 is enabled, and the clock signal DCLK(L) having the lowest frequency is selected.
The logic by the frequency switching control unit 202 illustrated in
Note that the truth table illustrated in Table 1 is an example and is not limited to this example.
In the above explanation, three stages of the low frequency, the medium frequency, and the high frequency can be selected as the clock signal PPCLK. However, this is an example. The clock signal PPCLK is not limited to this example. For example, the frequency of the clock signal PPCLK can be finely controlled by four or more stages of resolution.
Returning back to
The synchronization circuit 2010 is a circuit that synchronizes the clock signals DCLK(L), DCLK(M), and DCLK(H) supplied from the frequency divider 200 and the frequency switching signals FSEL #0, #1, and #2 supplied from the frequency switching control unit 202. The synchronization circuit 2010 includes three synchronization circuits corresponding to the clock signals DCLK(L), DCLK(M), and DCLK(H).
In the example illustrated in
Since these three synchronization circuits exhibit similar operations, the synchronization circuit corresponding to the clock signal DCLK(L) is explained as an example. The clock signal DCLK(L) is input to clock input ends of the flip-flop circuits 2011a and 2012a and one input end of the AND circuit 2013a. The frequency switching signal FSEL #0 is input to a data input end of the flip-flop circuit 2011a. An output from a non-inverting output end of the flip-flop circuit 2011a is input to a data input end of the flip-flop circuit 2012a. An output from the non-inverting output end of the flip-flop circuit 2012a is input to the other input end of the AND circuit 2013a.
With such a configuration, in the flip-flop circuit 2011a, a rising edge of the frequency switching signal FSEL #0 is synchronized with a rising edge of the clock signal DCLK(L). An output of the flip-flop circuit 2011a is further synchronized with the clock signal DCLK(L) by the next flip-flop circuit 2012a. As explained above, by using the flip-flop circuits 2011a and 2012a connected in series, the reliability of synchronization can be further improved.
The AND circuit 2013a calculates AND of the output of the flip-flop circuit 2012a and the clock signal DCLK(L), whereby the clock signal DCLK(L) synchronized with the frequency switching signal FSEL #0 is output from the AND circuit 2013a.
About the clock signals DCLK(M) and DCLK(H), similarly to the clock signal DCLK(L) explained above, the clock signals DCLK(M) and DCLK(H) synchronized with the frequency switching signals FSEL #1 and #2 are respectively output from the AND circuits 2013b and 2013c.
The clock signals DCLK(L), DCLK(M), and DCLK(H) output from the AND circuits 2013a, 2013b, and 2013c are respectively input to the switch circuits 2014a, 2014b, and 2014c. Outputs of the switch circuits 2014a, 2014b, and 2014c are connected to be a common output. The switch circuits 2014a, 2014b, and 2014c are respectively controlled to be opened and closed by the frequency switching signals FSEL #0, #1, and #2. Therefore, the clock signals DCLK(L), DCLK(M), and DCLK(H) are output from the selector 201 when the frequency switching signals FSEL #0, #1, and #2 are in the high state.
According to Table 1 explained above, in the operation modes, only one of the frequency switching signals FSEL #0, #1, and #2 is set to the high state. For example, in a period of the operation mode in which the operation mode is blank, only the frequency switching signal FSEL #0 of the frequency switching signals FSEL #0 to #2 is in set to the high state, only the switch circuit 2014a is set to the closed (ON) state, and the switch circuits 2014b and 2014c are set to the open (OFF) state. Accordingly, only the clock signal DCLK(L) among the clock signals DCLK(L), DCLK(M), and DCLK(H) is output from the selector 201 as the clock signal PPCLK.
Note that, in
Among these, the operation mode indicates operation mode periods of the blank, the read, the global reset and transfer, and the global shutter explained above. The operation modes are defined according to the mode signals MODE(br), MODE(rd), MODE(gr/ts), and MODE(gs) or a combination thereof in an operation period of the pixel array unit 100.
The shutter instruction is, for example, a signal that changes to the high state at timing corresponding to shutter operation on the input device 12 by a user. At this time, the shutter instruction is issued, for example, at a point in time when a state of the shutter button included in the input device 12 changes from a half-pressed state to a full-pressed state. Not only this, but the shutter instruction may be issued with a slight delay with respect to the shutter operation on the input device 12. In the case of moving image imaging, the shutter instruction is, for example, a signal that changes to the high state at predetermined timing of a frame period.
The exposure period is a period in which electric charges are accumulated by photoelectric conversion in the photodiode PD and is, for example, a period in which the OFG transistor TR0 and the transfer transistor TR1 are in the OFF state after the initialization of the photodiode PD.
As explained above, the mode signal MODE(br) is a signal indicating the blank period and is, more specifically, a flag signal indicating the blank period. In the example illustrated in
As explained above, the mode signal MODE(gr/ts) is a signal indicating the global reset and the transfer period and is, more specifically, a flag signal indicating the global reset and transfer period. In the example illustrated in
As explained above, the mode signal MODE(gs) is a signal indicating the global shutter period and is, more specifically, a flag signal indicating the global shutter period. The mode signal MODE(gs) indicates a negative potential stabilization waiting period for waiting for stabilization of the output voltage Vout of the negative potential of the charge pump 122 that has fluctuated because of the global shutter operation.
The global reset trigger is a trigger generated by, for example, the drive signal scanning unit 120 in order to execute initialization of the capacitors MEM and the floating diffusion layers FD included in the pixels 10 in the entire pixel array unit 100 all at once. The vertical drive unit 112 causes states of the drive signals TRG2 and RST to transition according to the global reset trigger.
The global transfer trigger is, for example, a trigger generated by the drive signal scanning unit 120 in order to execute transfer of electric charges accumulated in the photodiodes PD by the exposure in the pixels 10 to the capacitors MEM in the entire pixel array unit 100 all at once. The vertical drive unit 112 causes a state of the drive signal TRG1 to transition according to the global transfer trigger. The global shutter trigger is, for example, a trigger generated by the drive signal scanning unit 120 in order to instruct a start of exposure in the photodiodes PD. The vertical drive unit 112 causes a state of the drive signal OFG to transition according to the global shutter trigger.
The output voltage Vout is an output voltage output from the charge pump 122. A signal by the output voltage Vout is a signal obtained by smoothing, with the capacitor 123, a signal including a frequency component corresponding to the pumping operation output from the capacitor Cfly. Here, the voltage CB at the connection point CB to which the other end of the capacitor Cfly is connected is the signal including the frequency component corresponding to the pumping operation of the capacitor Cfly. In
In the frequency switching signal FSEL, the frequency switching signal FSEL #0 corresponding to the clock signal DCLK(L) having the low frequency, the frequency switching signal FSEL #1 corresponding to the clock signal DCLK(M) having the medium frequency, and the frequency switching signal FSEL #2 corresponding to the clock signal DCLK(H) having the high frequency are illustrated to correspond to periods in which the frequency switching signal FSEL #0, the frequency switching signal FSEL #1, and the frequency switching signal FSEL #2 are effective during the operation period of the pixel array unit 100.
In
The drive signal scanning unit 120 causes the mode signal MODE(gs) to transition from the low state to the high state at time t1 immediately before a shutter instruction is issued at time t2. For example, the drive signal scanning unit 120 sets timing when the full-press operation of the shutter is performed in the input device 12 as the time t1 and starts exposure at the time t2 after a predetermined time from the time t1.
At the time t1, when the mode signal MODE(gs) transitions to the high state, the frequency switching control unit 202 switches the frequency switching signal from the frequency switching signal FSEL #1 to the frequency switching signal FSEL #2 according to the truth table of Table 1. Accordingly, the clock signal DCLK(H) having a higher frequency is selected as the clock signal PPCLK.
At the time t2, the vertical scanning unit 110 sets the global shutter trigger to the high state and sets the drive signal OFG to the high state according to control of the drive signal scanning unit 120. At this time, since the global transfer trigger is in the low state and the drive signal TRG1 is in the low state, the electric charges accumulated in the photodiode PD are extracted to the power supply line of the power supply VDD and the photodiode PD is initialized. The drive signal scanning unit 120 causes the global shutter trigger to transition from the high state to the low state at time t3 in a state in which the low state of the drive signal TRG1 is maintained. The vertical drive unit 112 causes the drive signal OFG to transition from the high state to the low state according to the state transition of the global shutter trigger. Accordingly, accumulation of electric charges by photoelectric conversion is started in the photodiode PD and exposure is performed.
The transition of the drive signal OFG from the low state to the high state at the time t2 is executed in the pixels 10 included in the pixel array unit 100 all at once. The potential of the output voltage Vout of the charge pump 122 suddenly changes. By increasing the frequency of the clock signal PPCLK for operating the charge pump 122, the pumping operation in the charge pump 122 is executed at high speed and the capacitor Cfly is rapidly charged.
The drive signal scanning unit 120 causes the mode signal MODE(gs) to transition from the high state to the low state at time t4 after a predetermined time from the time t1. Note that, as the length from the time t1 to the time t4, a time in which it is predicted that the charging of the capacitor Cfly is completed in the charge pump 122 and the output voltage Vout of the charge pump 122 stabilizes is set in advance for the drive signal scanning unit 120.
The mode signal MODE(gs) is caused to transition from the high state to the low state at the time t4, whereby the frequency switching control unit 202 switches the frequency switching signal from the frequency switching signal FSEL #2 to the frequency switching signal FSEL #1 according to the truth table in Table 1. Accordingly, the clock signal DCLK(M) having a frequency lower than that of the clock signal DCLK(H) is selected as the clock signal PPCLK for operating the charge pump 122.
The drive signal scanning unit 120 causes the mode signal MODE(bk) to transition from the low state to the high state at time t5 after a predetermined time from the time t4 and causes the mode signal MODE(rd) to transition from the high state to the low state. Accordingly, the frequency switching control unit 202 switches the frequency switching signal from the frequency switching signal FSEL #1 to the frequency switching signal FSEL #0 according to the truth table of Table 1. The clock signal DCLK(L) having the lowest frequency is selected as the clock signal PPCLK.
The operation mode of the pixel array unit 100 is caused to transition from read to blank at the time t5. Processing such as transfer of an imaging signal to the outside of the imaging element 4 is executed in the pixel array unit 100. As explained above, in the period in which the operation mode is blank, the read processing from the pixels 10 and the like are not performed and access to the transistors included in the pixel 10 is not performed. Therefore, the power consumption in the vertical drive unit 112 of the pixel array unit 100 is also small. There is no rapid fluctuation in a charge amount in the capacitor Cfly in the charge pump 122. Therefore, the charge pump 122 can operate with the clock signal PPCLK having the low frequency.
At time t6 after a predetermined time elapses from the time t5, the drive signal scanning unit 120 causes the mode signal MODE(bk) to transition from the high state to the low state and ends the blank period. The drive signal scanning unit 120 causes the mode signal MODE(gr/ts) to transition from the low state to the high state at the time t6. Accordingly, the operation mode of the pixel array unit 100 is switched to the global reset and transfer mode.
The drive signal scanning unit 120 causes the global reset trigger to transition from the low state to the high state at time t7. The vertical drive unit 112 causes the drive signals TRG2 and RST to transition from the low state to the high state according to the state transition of the global reset trigger of the drive signal scanning unit 120 and sets the transfer transistor TR2 and the reset transistor TR3 to the ON state. Accordingly, the electric charges of the capacitor MEM and the floating diffusion layer FD are extracted to the power supply line of the power supply VDD and the capacitor MEM and the floating diffusion layer FD are reset.
The drive signal scanning unit 120 causes the global shutter trigger to transition from the high state to the low state at time t8 immediately after the time t7. The vertical drive unit 112 sets the drive signals TRG2 and RST to the low state and sets the transfer transistor TR2 and the reset transistor TR3 to the OFF state according to the state transition of the global shutter trigger.
The drive signal scanning unit 120 causes the global transfer trigger to transition from the low state to the high state at the time t8. The vertical drive unit 112 causes the drive signal TRG1 to transition to the high state according to the state transition of the global transfer trigger and sets the transfer transistor TR1 to the ON state. Accordingly, the electric charges accumulated in the photodiode PD in the exposure period are transferred from the photodiode PD to the capacitor MEM. Note that the drive signal scanning unit 120 causes the global transfer trigger to transition from the high state to the low state at time t9 immediately after the time t8. The transfer transistor TR1 is set to the OFF state by control of the vertical drive unit 112 involved in the transition.
Here, the transfer of the electric charges accumulated in the photodiode PD to the capacitor MEM at the time t8 is executed in the pixels 10 included in the pixel array unit 100 all at once. Therefore, as at the time t2 explained above, the potential of the output voltage Vout of the charge pump 122 suddenly changes. By increasing the frequency of the clock signal PPCLK for operating the charge pump 122, the pumping operation in the charge pump 122 is executed at high speed and the capacitor Cfly is rapidly charged.
At time t10 after elapse of a predetermined time from the time t6, the drive signal scanning unit 120 causes the mode signal MODE(rd) to transition from the low state to the high state and causes the mode signal MODE(gr/ts) to transition from the high state to the low state. Accordingly, the frequency switching signal is switched from the frequency switching signal FSEL #2 to the frequency switching signal FSEL #1 in the frequency switching control unit 202 according to the truth table of Table 1. The clock signal DCLK(M) having a lower frequency than the clock signal DCLK(H) is selected as the clock signal PPCLK. The processing shifts to the read period of the pixel array unit 100.
As explained above, the frequency of the clock signal PPCLK for driving the charge pump 122 is increased in a period until the pixels 10 included in the pixel array unit 100 are driven all at once and the output voltage Vout of the charge pump 122 stabilizes. The frequency of the clock signal PPCLK is lowered in a period in which there is no access to the transistors included in the pixels 10 in the pixel array unit 100 or there is little access. Accordingly, it is possible to suppress power consumption when driving the charge pump 122.
By increasing the frequency of the clock signal PPCLK in a period until the pixels 10 included in the pixel array unit 100 are driven all at once and the output voltage Vout of the charge pump 122 stabilizes, it is possible to reduce the time required for stabilizing the output voltage Vout of the charge pump 122. Accordingly, the frame rate can be increased.
In the example illustrated in
For example, the drive signal scanning unit 120 can increase and reduce a feedback voltage in a feedback loop by controlling the reference voltage Vref0 generated by the reference voltage generation unit 203, thereby controlling the amplitude of the voltage CB. In the example illustrated in
As explained above, by controlling not only the frequency of the clock signal PPCLK but also the amplitude of the voltage CB, the time required for stabilizing the output voltage Vout of the charge pump 122 can be further reduced.
Note that, in the example illustrated in
Note that, in the above explanation, the frequency of the clock signal PPCLK for driving the charge pump 122 is switched among the three types of the low frequency, the medium frequency, and the high frequency. An intention for the above is explained below.
In the blank period, the frequency of the clock signal PPCLK is switched to the low frequency. In the blank period, since access to the transistors in the pixel 10 is not performed, it seems as if a voltage value of the negative power supply does not change even if the voltage is not supplied from the charge pump 122. However, the voltage value of the negative power supply increases with a leakage current of the vertical drive unit 112 and a consumed current in natural discharge of the capacitor 123 connected to the output of the charge pump 122. It is necessary to suppress the increase. However, since the increase is very small, a driving capability is not so necessary as in the other operation modes.
Therefore, in the first embodiment, by setting the frequency of the clock signal PPCLK to a frequency lower than the frequency in the read period and performing pumping, the power consumption is reduced while suppressing the voltage increase.
In the read period, the frequency of the clock signal PPCLK is switched to the medium frequency. In the read period, a unit of reading pixel signals at a time is one row to several rows. Reading several rows at a time is sometimes adopted to increase reading speed in the read period. On the other hand, in the read period, reading is sequentially performed for all the rows included in the pixel array unit 100. It is necessary to suppress an increase in the consumption current with pumping of the charge pump 122 so that the voltage value of the negative power supply does not change within the read period of one row to several rows. Note that, actually, if there is no fluctuation in the voltage value of the negative power supply between the P-phase period and the D-phase period, the AD conversion result by the AD converter is not affected. One read period depends on the number of bits of the AD conversion, an AD conversion scheme, and the like. However, in the case of the AD conversion by the single slope scheme explained above, one read period is approximately several psec.
Therefore, considering a relation between the consumed current and the pumping capability, in the read period, a more driving capability is necessary compared to the blank period. However, it is unnecessary to perform pumping at the high frequency.
In the global reset and transfer period and the global shutter period, the frequency of the clock signal PPCLK is switched to the high frequency. In the global reset and transfer period, the reset operation and the transfer operation are executed in all the rows included in the pixel array unit 100 all at once. In the global shutter period, similarly, the shutter operation is executed in all the rows included in the pixel array unit 100 all at once. Therefore, in these periods, an instantaneous consumed current is large and the voltage value of the negative power supply greatly fluctuates. If the voltage of the negative power supply is not restored to the voltage value immediately before the global operation such as the global reset and transfer and the global shutter, the operation cannot be shifted to the next operation. A return time for restoring to the voltage value immediately before the global operation is included in a time in one frame. Therefore, by restoring the negative power supply at a higher speed, the time of one frame can be reduced and the frame rate can be increased.
Therefore, in the first embodiment, in the global reset and transfer period and the global shutter period, the pumping in the charge pump 122 is executed by the clock signal PPCLK having a frequency higher than the frequency in the read period to restore the negative power supply in a shorter time.
On the other hand, a chart 31 illustrates an example in a case where the frequency of the clock signal PPCLK for driving the charge pump 122 is fixed according to the existing technique. This corresponds to, for example, the technique disclosed in Patent Literature 1. Note that a configuration applied to the chart 31 is similar to the configuration illustrated in
In the chart 31, as in the chart 30, it is assumed that the mode signal MODE(gs) is caused to transition from the low state to the high state at the time t1. Further, it is assumed that the transition of the drive signal OFG from the low state to the high state is executed in the pixels 10 included in the pixel array unit 100 all at once at timing corresponding to the time t2. The potential of the output voltage Vout of the charge pump 122 rapidly changes according to the transition of the state of the drive signal OFG.
Here, it is assumed that displacement of the potential of the output voltage Vout of the charge pump 122 is recovered by a constant number of times of the pumping operation. In this case, in the example of the chart 31, since the frequency of the clock signal PPCLK for driving the charge pump 122 is constant, it takes a longer time until the output voltage Vout stabilizes compared with an example of the chart 30 in which the frequency is set higher. In the example illustrated in
Note that, in the first embodiment, a power saving function and the like are realized by controlling the frequency of the clock signal PPCLK. Here, by controlling the clock signal PPCLK to divide the clock signal CPCLK according to a band of a cutoff filter in the CDS processing, it is possible to suppress noise that is likely to be generated from the charge pump 122 and affect a pixel signal.
In the first embodiment, the feedback voltage of the feedback loop for controlling the amplitude of the voltage VCP is changed by controlling the reference voltage Vref0 generated by the reference voltage generation unit 203. Therefore, it is unnecessary to consider a time required for stable restoration of the voltage of the feedback loop relating to the amplitude control of the voltage VCP and output fluctuation at the time of restoration compared with a method of once disconnecting the feedback loop to switch the feedback loop to the boost voltage in Patent Literature 1.
For example, the drive signal scanning unit 120 can increase and reduce a feedback voltage in a feedback loop by controlling the reference voltage Vref0 generated by the reference voltage generation unit 203, thereby controlling the amplitude of the voltage CB. In the example illustrated in
As explained above, by controlling not only the frequency of the clock signal PPCLK but also the amplitude of the voltage CB, the time required for stabilizing the output voltage Vout of the charge pump 122 can be further reduced.
Here, the effects of the first embodiment are explained in more detail. As explained above, the pixel 10 applied to the first embodiment is configured by the CMOS circuit. However, power consumption of the CMOS circuit is mainly power consumption due to charging and discharging currents and a through-current. Note that it is assumed that power consumption due to a leakage current is smaller than these two consumed currents. When a frequency of a switching signal is represented as fc [Hz], a load capacity is represented as CL [F], a power supply voltage is represented as VDD [V], and a through-current flowing from a power supply to the ground is represented as idp(t) [A], power consumption Powcg by the charging and discharging currents and power consumption Powtc by the through-current are represented by the following expressions (1) and (2).
Pow
cg
=f
c
C
L
V
2
DD (1)
Pow
tc
=f
c
V
DD∫01/f
In a normal time, the voltage VDD (signal amplitude of the switching signal) is a voltage conforming to the feedback voltage. This is the same as, for example, the existing technique described in Patent Literature 1. Therefore, in the first embodiment in which the frequency fc can be varied and reduced, the power consumption can be reduced.
An electric current that can be output by the charge pump 122 in a certain period t [sec] is represented by the following expression (3) when a pumping capacity value (a capacity value of the capacitor Cfly) is represented as Cfly [Hz], a power supply voltage by the power supply VDD is represented as VDD [V], a negative potential output of the charge pump 122 is represented as VCP [V], and a frequency of the switching signal (the clock signal PPCLK) is represented as fc [Hz].
It is seen according Expression (3) that a large current can be obtained within a certain period by increasing the frequency fc.
As a method of switching a pumping frequency for driving a pumping operation, a method of using a voltage-controlled oscillator (VCO) at a feedback voltage is known (for example, Patent Literature 2). In the method using the VCO, the pumping frequency can be switched in an analog infinite stage. The power consumption and the driving capability can be controlled more finely and the system can be closed on the analog side.
On the other hand, in the method using the VCO for the switching of the pumping frequency, the frequency range to be controlled can be limited to some extent. However, since the frequency changes at any time, it is difficult for the system side to grasp which frequency is to be used. Therefore, the imaging element to which the method is applied is likely to cause noise in a frequency band used by radio or an interface (I/F) mounted in the system.
Since the imaging element 4 according to the first embodiment generates the clock signal PPCLK for driving the charge pump 122 by digitally dividing the clock signal PPCLK to predetermined frequencies with the frequency divider 200, these frequencies can be avoided. When a block affected by the clock signal PPCLK is operating in the system, the charge pump 122 included in the imaging element 4 according to the first embodiment can reduce the power or increase the driving capability as necessary while avoiding the block by changing the frequency band.
Further, the frequency used in the CIS can be divided and synchronized with the pumping frequency and the frequency used in the column processing unit 114. Accordingly, pumping can be performed at a frequency that can be removed by the filter used in the CDS processing. Noise to the column processing unit 114 by the charge pump 122 at the time of reading can be suppressed.
When the driving capability is increased by increasing the voltage amplitude of pumping, the switching noise also increases. When the driving capability of the charge pump 122 is increased by increasing the pumping frequency, this switching noise can be removed by the CDS filter if the pumping frequency is a multiple of the cutoff frequency of the CDS filter. Therefore, as the control of the driving capability by the charge pump 122, the frequency control is more advantageous than in the voltage control.
Note that, even when the voltage amplitude relating to the pumping is large, the switching noise can be removed by the CDS filter in the same manner if the pumping frequency is a multiple of the cutoff frequency of the CDS filter. However, since the noise cannot be completely removed by this method, the absolute amount of the noise is preferably small.
In the fast trigger mode in which the shutter is driven at an any timing among the operation modes of the shutter, the shutter is driven during the read period and the negative potential stabilization waiting period is not provided. Therefore, when noise occurs from the charge pump 122, there is a possibility that the AD conversion processing in the column processing unit 114 is affected. Therefore, for the reasons explained above, it is desirable to control the driving capability of the charge pump 122 by frequency control.
In the example explained above, the driving capability of the charge pump 122 is changed by changing the voltage amplitude with the feedback voltage in addition to the frequency control. However, the driving capability may be changed only by the frequency control not by the voltage amplitude according to necessity.
Next, a first modification of the first embodiment is explained. In the first embodiment explained above, the frequency of the clock signal PPCLK for driving the charge pump 122 is selected on an output side of the selector 201. In contrast, the first modification of the first embodiment is an example in which the frequency of the clock signal PPCLK is selected on an input side of the selector 201.
The frequency switching signal FSEL #0 output from the frequency switching control unit 202 is input to a first input end of the AND circuit 2030a. The clock signal DCLK(L) generated by dividing the clock signal CPCLK in the frequency divider 200 is input to a second input end of the AND circuit 2030a. An output of the AND circuit 2030a is input to the clock input ends of the flip-flop circuits 2011a and 2012a of the synchronization circuit 2010 and is input to a second input end of the AND circuit 2013a. The frequency switching signal FSEL #0 output from the frequency switching control unit 202 is input to the data input ends of the flip-flop circuits 2011a and 2012a. An output of the AND circuit 2013a is input to a first input end of the OR circuit 2031.
Thereafter, similarly, the frequency switching signal FSEL #1 is input to a first input end of the AND circuit 2030b, and the clock signal DCLK(M) is input to a second input end of the AND circuit 2030b. An output of the AND circuit 2030b is input to clock input ends of the flip-flop circuits 2011b and 2012b and is input to a second input end of the AND circuit 2013b. The frequency switching signal FSEL #1 is input to data input ends of the flip-flop circuits 2011b and 2012b. An output of the AND circuit 2013b is input to a second input end of the OR circuit 2031.
The frequency switching signal FSEL #2 is input to a first input end of the AND circuit 2030c and the clock signal DCLK(H) is input to a second input end of the AND circuit 2030c. An output of the AND circuit 2030c is input to the clock input ends of the flip-flop circuits 2011b and 2012b and is input to a second input end of the AND circuit 2013c. The frequency switching signal FSEL #2 is input to the data input ends of the flip-flop circuits 2011b and 2012b. An output of the AND circuit 2013c is input to a third input end of the OR circuit 2031.
An output of the OR circuit 2031 is output from the selector 201a as the clock signal PPCLK.
In such a configuration, as the clock signals DCLK(L), DCLK(M), and DCLK(H), the clock signal DCLK corresponding to the frequency switching signal FSEL in the high state among the frequency switching signals FSEL #0, FSEL #1, and FSEL #2 is selected by the AND circuits 2030a, 2030b, and 2030c. On the other hand, the clock signal DCLK corresponding to the frequency switching signal FSEL in the low state among the frequency switching signals FSEL #0, FSEL #1, and FSEL #2 is not selected.
For example, when the clock signal DCLK(L) is selected among the clock signals DCLK(L), DCLK(M), and DCLK(H), the flip-flop circuits 2011a and 2012a to which the clock signal DCLK(L) is input operate according to the input clock signal DCLK(L). On the other hand, since the clock signals DCLK(M) and DCLK(H) are not respectively input to the flip-flop circuits 2011b and 2012b and the flip-flop circuits 2011c and 2012c, the operations thereof are stopped. Therefore, power consumption by the flip-flop circuits 2011b and 2012b and the flip-flop circuits 2011c and 2012c can be suppressed.
As explained above, by selecting the frequency of the clock signal PPCLK on the input side of the selector 201, the charge pump 122 can be appropriately controlled according to the operation of the pixel array unit 100 and the power consumption can be suppressed.
Subsequently, a second modification of the first embodiment is explained. The second modification of the first embodiment is an example in which a plurality of clock signals DCLK to be selected as the frequency of the clock signal PPCLK is generated by individual frequency dividers and it is controlled which one of the frequency dividers is enabled.
In
The frequency switching signal FSEL #0 is input to a first input end of the AND circuit 2041a, the frequency switching signal FSEL #1 is input to a first input end of the AND circuit 2041b, and the frequency switching signal FSEL #2 is input to a first input end of the AND circuit 2041c. The clock signal CPCLK is input to second input ends of the AND circuits 2041a, 2041b, and 2041c in commonly.
An output of the AND circuit 2041a is input to the frequency divider DIV 2042a and an output of the frequency divider DIV 2042a is input to the clock input ends of the flip-flop circuits 2011a and 2012a included in the synchronization circuit 2010 and is input to the second input end of the AND circuit 2013a. Similarly, an output of the AND circuit 2041b is input to the frequency divider DIV 2042b and an output of the frequency divider DIV 2042 is input to the clock input ends of the flip-flop circuits 2011b and 2012b and is input to the second input end of the AND circuit 2013b. An output of the AND circuit 2041c is input to the frequency divider DIV 2042c and an output of the frequency divider DIV 2042c is input to the clock input ends of the flip-flop circuits 2011c and 2012c and is input to the second input end of the AND circuit 2013c.
In such a configuration, for example, the AND circuit 2041a outputs the clock signal CPCLK to the frequency divider DIV 2042a when the frequency switching signal FSEL #0 is in the high state. The frequency divider DIV 2042a divides the clock signal CPCLK supplied from the AND circuit 2041a to generate the clock signal DCLK(L). As explained above, the clock signal DCLK(L) is input to the clock input ends of the flip-flop circuits 2011a and 2012a and is input to the second input end of the AND circuit 2013a.
On the other hand, since the AND circuit 2041a does not output the clock signal CPCLK when the frequency switching signal FSEL #0 is in the low state, the frequency divider DIV 2042a does not perform the frequency dividing operation. Accordingly, the flip-flop circuits 2011a and 2012a do not operate either since the clock signal DCLK(L) is not input to the clock input end.
The above operation is similar in the AND circuit 2041b and the frequency divider DIV 2042b and in the AND circuit 2041c and the frequency divider DIV 2042c.
As explained above, in the second modification of the first embodiment, the clock signals DCLK(L), DCLK(M), and DCLK(H) of the respective frequencies are generated by the individual frequency dividers DIV 2042a, 2042b, and 2042c and the operations of the frequency dividers DIV 2042a, 2042b, and 2042c are controlled by the frequency switching signals FSEL #0, FSEL #1, and FSEL #2. Accordingly, in the second modification of the first embodiment, in addition to the first modification of the first embodiment explained above, the operation of a frequency divider corresponding to a clock frequency that is not selected among the frequency dividers DIV 2042a to 2042c can be further stopped. Lower power consumption can be realized.
Subsequently, a third modification of the first embodiment is explained. In the first embodiment explained above, the imaging is explained as being performed by the global shutter scheme in the pixel array unit 100. However, this is not limited to this example. The third modification of the first embodiment is an example in which the present disclosure is applied to a case where imaging is performed by a rolling shutter scheme.
In the pixel 10a, the vertical scanning unit 110 sets the transfer transistor TR6 to the OFF state with the drive signal TRG according to a control signal from the drive signal scanning unit 120 during exposure and causes the photodiode PD to accumulate electric charges generated according to light made incident by photoelectric conversion. After the exposure ends, the vertical scanning unit 110 sets the path selection transistor TR5 to the ON state with the drive signal SEL according to a control signal from the drive signal scanning unit 120 and connects the floating diffusion layer FD and the vertical signal line VSL.
The vertical scanning unit 110 sets the reset transistor TR3 to the ON state with the drive signal RST, connects the floating diffusion layer FD to the power supply line of the power supply VDD or a supply line of a black level voltage in a short period, and resets the floating diffusion layer FD. The voltage of the reset level of the floating diffusion layer FD by the P-phase reading is output to the vertical signal line VSL. Thereafter, the vertical scanning unit 110 sets the transfer transistor TR6 to the ON state with the drive signal TRG according to a control signal from the drive signal scanning unit 120, transfers the electric charges accumulated in the photodiode PD to the floating diffusion layer FD, and performs the D-phase reading. By this D-phase reading, a voltage corresponding to a charge amount of the floating diffusion layer FD is output to the vertical signal line VSL.
The read operation explained above is executed in the pixels 10a arranged in one row all at once. Further, the read operation of the rows is executed row by row. Accordingly, imaging by the rolling shutter scheme is realized.
Note that the processing explained with reference to
Note that, in
In
The drive signal scanning unit 120 causes the mode signal MODE(br) to transition from the low state to the high state and causes the mode signal MODE(rd) to transition from the high state to the high state at time t31 after a predetermined time (for example, after the lapse of a time corresponding to a frame rate) from the time t30 and sets the operation mode to a blank operation mode period (a blank period). In the blank period, the frequency switching control unit 202 outputs the frequency switching signal FSEL #0 according to the mode signals MODE(bk) and MODE (rd). In the selector 201, the clock signal DCLK(L) having the low frequency is selected as the clock signal PPCLK for driving the charge pump 122 according to the frequency switching signal FSEL #0.
In the pixel array unit 100, in the shutter and read period, the shutter operation and the read operation are sequentially executed for each one row or plurality of rows. Accordingly, in the pixel array unit 100, the read operation is sequentially performed for each one row or plurality of rows and the output voltage Vout of the charge pump 122 repeats fluctuation for each row. In the case of the rolling shutter scheme, since the reading is sequentially performed for each row or several rows, the fluctuation of the output voltage Vout of the charge pump 122 is small compared with the global shutter scheme explained with reference to
On the other hand, in the blank period, the frequency of the clock signal PPCLK is switched to, for example, the low frequency to reduce the driving capability by the charge pump 122. Accordingly, even in the rolling shutter scheme, it is possible to reduce the power consumption of the charge pump 122.
Subsequently, a fourth modification of the first embodiment is explained. The fourth modification of the first embodiment is an example in which a mechanical shutter scheme for controlling an exposure time in the photodiode PD with a shutter mechanism is applied to the shutter scheme. In the fourth modification of the first embodiment, since the configuration of the pixel 10a according to the third modification of the first embodiment explained with reference to
In the case of the mechanical shutter scheme, the vertical scanning unit 110 causes the transfer transistors TR6 and TR3 illustrated in
In the case of the mechanical shutter scheme, as explained above, since the pixels 10a included in the pixel array unit 100 are simultaneously driven, the load of the negative power supply instantaneously increases. Therefore, the frequency of the clock signal PPCLK is switched from the low frequency or the medium frequency to the high frequency for a predetermined period after the transfer transistors TR6 and TR3 are caused to simultaneously transition from the OFF state to the ON state in the pixel array unit 100 and the driving capability of the charge pump 122 is increased. Accordingly, the time until the negative potential of the negative power supply is restored after the reset operation of the photodiode PD can be reduced and the frame rate can be increased.
Note that, in the mechanical shutter scheme, in the read period and the blank period, the frequency of the clock signal PPCLK is set to the medium frequency and the low frequency, respectively, as in the global shutter scheme explained with reference to
Subsequently, a fifth modification of the first embodiment is explained. The fifth modification of the first embodiment is an example in which an FD holding scheme for performing global shutter scheme imaging in the pixel configuration illustrated in
In the FD holding scheme, the vertical scanning unit 110 causes the transfer transistors TR6 and TR3 to simultaneously transition from the OFF state to the ON state in the pixel array unit 100 according to a control signal from the drive signal scanning unit 120 and resets the photodiodes PD of all the pixels 10a all at once. Thereafter, the vertical scanning unit 110 causes the transfer transistors TR6 and TR3 to simultaneously transition from the ON state to the OFF state and starts exposure for the photodiode PD.
Thereafter, according to a control signal from the drive signal scanning unit 120, the vertical scanning unit 110 causes the transfer transistor TR6 to simultaneously transition from the OFF state to the ON state in the pixel array unit 100 and transfers the electric charges accumulated in the photodiode PD by exposure to the floating diffusion layer FD. When the transfer of the electric charges to the floating diffusion layer FD ends, the vertical scanning unit 110 causes the transfer transistor TR6 to transition to the OFF state according to a control signal from the drive signal scanning unit 120. Thereafter, a pixel signal is read by the rolling operation for each one row or several rows.
In this FD holding scheme as well, since the pixels 10a included in the pixel array unit 100 are simultaneously driven at the reset time of the photodiode PD and the transfer time of the electric charges accumulated in the photodiode PD to the floating diffusion layer FD, the load of the negative power supply instantaneously increases. Therefore, for example, at the reset time of the photodiode PD, the frequency of the clock signal PPCLK is switched from the low frequency or the medium frequency to the high frequency for a predetermined period after the transfer transistors TR6 and TR3 are caused to simultaneously transition from the OFF state to the ON state in the pixel array unit 100 and the driving capability of the charge pump 122 is increased. Accordingly, the time until the negative potential of the negative power supply is restored after the reset operation of the photodiode PD can be reduced and the frame rate can be increased. The same applies when the electric charges accumulated in the photodiode PD are transferred to the floating diffusion layer FD.
Note that, in the FD holding scheme as well, the frequency of the clock signal PPCLK is set to the medium frequency and the low frequency respectively in the read period and the blank period as in the global shutter scheme explained with reference to
Subsequently, a sixth modification of the first embodiment is explained. The sixth modification of the first embodiment is an example in which a pixel analog to digital converter (ADC) configuration including an AD converter for each pixel is applied as a pixel configuration.
The floating diffusion layer FD is connected to the sources of the transfer transistor TR6 and a reset transistor TR7 and is connected to a (−) side input end of a comparator CMP. The RAMP signal, the voltage of which based on the straight line increases or decreases stepwise, is input to a (+) side input end of the comparator CMP. An output of the comparator CMP is connected to a counter that counts a time from a predetermined position (for example, a start point) of a slope of the RAMP signal until when the RAMP signal and a voltage due to the electric charges accumulated in the floating diffusion layer FD coincide and calculates a digital value of a voltage value due to the electric charges.
Further, a drain of the reset transistor TR7 that controls the reset operation is connected to the power supply line of the power supply VDD. When the reset transistor TR7 is set to the ON state according to the drive signal RST, the floating diffusion layer FD is initialized by a positive potential power supply voltage of the comparator CMP.
In the configuration illustrated in
When the exposure is completed, the vertical drive unit 112 causes the transfer transistor TR6 to transition from the OFF state to the ON state in the pixels 10b of the pixel array unit 100 all at once while maintaining the OFF state of the OFG transistor TR8 according to a control signal from the drive signal scanning unit 120. Accordingly, a voltage corresponding to the electric charges accumulated in the floating diffusion layer FD is input to the (−) side input end of the comparator CMP (a read operation) and the AD conversion processing is performed.
In this pixel ADC scheme as well, at a reset time of the photodiode PD and at a transfer time of the electric charges accumulated in the photodiode PD to the floating diffusion layer FD, the pixels 10b included in the pixel array unit 100 are simultaneously driven. Therefore, the load of the negative power supply instantaneously increases. Therefore, for example, at the reset time of the photodiode PD, the frequency of the clock signal PPCLK is switched from the low frequency or the medium frequency to the high frequency for a predetermined period after the OFG transistor TR8 is simultaneously caused to transition from the OFF state to the ON state in the pixel array unit 100 and the driving capability by the charge pump 122 is increased. Accordingly, the time until the negative potential of the negative power supply is restored after the reset operation of the photodiode PD can be reduced and the frame rate can be increased. The same applies when the electric charges accumulated in the photodiode PD are transferred to the floating diffusion layer FD.
Note that, in the pixel ADC scheme as well, the frequency of the clock signal PPCLK is set to the medium frequency and the low frequency respectively in the read period and the blank period as in the global shutter scheme explained with reference to
Subsequently, a seventh modification of the first embodiment is explained. The seventh modification of the first embodiment is an example in a case where the imaging region is limited to a region of interest (ROI) for all the pixels of the pixel array unit 100 in the global shutter scheme. This imaging scheme is referred to as a ROI scheme for convenience. In this case, the configuration illustrated in
When a range in which a pixel signal is read (a read operation) is limited by the ROI scheme, the load of the negative power supply also varies depending on a limited region. Therefore, the frequency of the clock signal PPCLK is adaptively switched according to a region and the driving capability of the charge pump 122 is changed. For example, when the range of the read operation is narrow, since the load of the negative power supply is small, the frequency of the clock signal PPCLK can be set to the medium or low frequency and a reduction in the power consumption can be achieved.
Subsequently, a second embodiment of the present disclosure is explained. In the second embodiment of the present disclosure, a plurality of charge pumps is provided and a driving capability for driving the vertical drive unit 112 is changed by changing the number of charge pumps to be operated according to an operation mode.
For example, a configuration in which the frequency divider 200, the selector 201, and the frequency switching control unit 202 are removed from the charge pump 122 illustrated in
In
The standby switching control unit 1220 is supplied with the mode signals MODE from the drive signal scanning unit 120. The standby switching control unit 1220 generates standby signals STBY #1, STBY #2, . . . , and STBY #n respectively based on the periods indicated by the input mode signals MODE. The standby signals STBY #1, STBY #2, . . . , and STBY #n are respectively input to second input ends of the AND circuits 12211, 12212, . . . , and 1221n
The AND circuits 12211, 12212, . . . , and 1221n supply the clock signal CPCLK input to the first input ends respectively to the corresponding charge pumps 12221, 12222, . . . , and 1222n when the standby signals STBY #1, STBY #2, . . . , and STBY #n input to the second input ends are, for example, in a high state. When the clock signal CPCLK is input, the charge pumps 12221, 12222, . . . , and 1222n execute pumping operation and output the output voltage Vout.
In such a configuration, the standby switching control unit 1220 generates the standby signals STBY #1, STBY #2, . . . , and STBY #n according to the input mode signal MODE to control the number of charge pumps to be operated simultaneously among the charge pumps 12221, 12222, . . . , and 1222n.
Here, for explanation, it is assumed that n=3 and the charge pump 122a includes three charge pumps #1, #2, and #3. The AND circuits 12211, 12212, . . . corresponding to the three charge pumps #1, #2, and #3 are respectively referred to as an AND circuit #1, an AND circuit #2, and an AND circuit #3, respectively.
It is assumed that the pixel array unit 100 operates in the same manner as the operation illustrated in the sequence chart of
As a more specific example, the standby switching control unit 1220 sets the standby signal STBY #1 to the high state and sets the standby signals STBY #2 and STBY #3 to the low state in a period (for example, a blank period) of the frequency switching signal #0, which is a period in which a frequency is low in the frequency switching signal FSEL illustrated in
The standby switching control unit 1220 sets the standby signals STBY #1 and STBY #2 to the high state and sets the standby signal STBY #3 to the low state in a period of the frequency switching signal #1 (for example, a read period excluding a global shutter period), which is a period of the medium frequency in the frequency switching signal FSEL illustrated in
Further, the standby switching control unit 1220 sets all of the standby signals STBY #1, STBY #2, and STBY #3 to the high state in a period (a negative potential stabilization waiting period) of the frequency switching signal #2, which is a period of the high frequency in the frequency switching signal FSEL illustrated in
For example, in a large-sized imaging element 4 including a large number of pixels 10 included in the pixel array unit 100 and a large pixel region, a plurality of charge pumps 12221, 12222, . . . , and 1222n is sometimes mounted to drive a large number of pixels 10. In the second embodiment, the number of charge pumps to be operated by controlling the standby signals STBY #1, STBY #2, . . . , and STBY #n for the charge pumps 12221, 12222, . . . , and 1222n is changed by the mode signals MODE supplied from the drive signal scanning unit 120 explained above.
It is possible to suppress the power consumption of the charge pump 122a as a whole according to the number of charge pumps in the standby state among the charge pumps 12221, 12222, . . . , and 1222n. If the number of charge pumps to be operated is increased, the driving capability of the charge pump 122a as a whole can be increased.
Subsequently, a third embodiment of the present disclosure is explained. In the third embodiment of the present disclosure, a driving capability for driving the vertical drive unit 112 is changed by making a pumping capacitor in a charge pump variable. More specifically, the driving capability of the charge pump can be reduced by reducing a capacity value of the pumping capacitor and the driving capability of the charge pump can be increased by increasing the capacity value.
For example, when a capacity value of the capacitor Cfly, which is the pumping capacitor of the charge pump, is 100 [pF] in a system of the imaging element 4, the capacitor Cfly is operated with the capacity value set to 10 [pF] in a blank period to suppress power consumption. On the other hand, the capacitor Cfly is operated with the capacity value of the capacitor Cfly set to 50 [pF] in a read period and the capacitor Cfly is operated with the capacity value of the capacitor Cfly set to 100 [pF] in a negative potential stabilization waiting period such as global operation periods to increase the driving capability. By performing such control, it is possible to reduce the power consumption in the charge pump as a whole of the operation of the imaging element 4.
Based on the mode signals MODE supplied from the drive signal scanning unit 120, the capacity value switching control unit 220 generates a capacity value switching signal CSEL for controlling the capacity of a capacitor Cfly′, which is the pumping capacitor.
Note that the clock signal CPCLK for driving the charge pump 122b is directly input to the inverter 213. Opening and closing of the switch circuits 211a and 211b are controlled on an input side of the inverter 213 and opening and closing of the switch circuits 212a and 212b are controlled on an output side of the inverter 213. That is, the capacitor Cfly′ is pumped by the clock signal CPCLK having a constant frequency.
In such a configuration, for example, referring to
In the example explained above, since the capacity value of the capacitor Cfly′ is reduced in the blank period, a chargeable charge amount of the capacitor Cfly′ is small and power consumption can be suppressed. On the other hand, since the capacity value of the capacitor Cfly′ is increased in the negative potential stabilization waiting period, the chargeable charge amount of the capacitor Cfly′ increases and the driving capability of the charge pump 122b increases.
In
One end of the capacitor Cfly_1 is connected to a connection point where the other end of the switch circuit 2111 and one end of the switch circuit 2121 are connected. Similarly, in the switch circuits 2112 and 2122, . . . , and 211n and 212n, one ends of the capacitors Cfly_2, . . . , and Cfly_n are connected to connection points where the other ends and one ends of the switch circuits 2112 and 2122, . . . , and 211n and 212n, are connected.
On the other hand, one end of the switch circuit 223a is connected to the ground potential and the other end of the switch circuit 223a is connected to one end of the switch circuit 223b. The voltage VCP is output from the other end of the switch circuit 223b. The other ends of the capacitors Cfly_1, Cfly_2, . . . , and Cfly_n are connected in common to a connection point where the other end of the switch circuit 223a and one end of the switch circuit 223b are connected.
The clock signal CPCLK is input to the inverter 213 and is input to a driver amplifier 2211 and the first input ends of the AND circuits 2232, . . . , and 223n. An output of the inverter 213 is input to a driver amplifier 2221 and the first input ends of the respective AND circuits 2242, . . . , and 224n.
The capacity value switching control unit 220 generates capacity value switching signals CSEL #1, . . . , and CSEL #n. At this time, the capacity value switching control unit 220 controls the high state and the low state of the capacity value switching signals CSEL #1, . . . , and CSEL #n according to the mode signal MODE supplied from the drive signal scanning unit 120. The capacity value switching signals CSEL #1, . . . , and CSEL #n are respectively input to the second input ends of the AND circuits 2232 and 2242, . . . , and 223n and 224n.
Outputs of the AND circuits 2232, . . . , and 223n are respectively input to driver amplifiers 2212, . . . , and 221n. Similarly, outputs of the AND circuits 2242, . . . , and 224n are respectively input to driver amplifiers 2222, . . . , and 222n.
The switch circuits 2111, 2112, . . . , and 211n are respectively controlled to be opened and closed according to outputs of driver amplifiers 2211, 2212, . . . , and 221n. Similarly, the switch circuits 2121, 2122, . . . , and 212n are respectively controlled to be opened and closed according to outputs of driver amplifiers 2221, 2222, . . . , and 222n. Although a signal path is omitted, the switch circuit 223a is controlled to be opened and closed according to the clock signal CPCLK and the switch circuit 223b is controlled to be opened and closed according to the clock signal CPCLK inverted by the inverter 213.
That is, the switch circuit 223a and the switch circuits 2111, 2112, . . . , and 211n are respectively controlled to be opened and closed in synchronization with the clock signal CPCLK. The switch circuit 223b and the switch circuits 2121, 2122, . . . , and 212n are respectively controlled to be opened and closed in synchronization with the clock signal CPCLK and at timing inverted with respect to the switch circuit 223a and the switch circuits 2111, 2112, . . . , and 211n.
In such a configuration, based on the mode signal MODE, for example, in the blank period illustrated in
On the other hand, the capacity value switching control unit 220 sets a predetermined number (for example, n/2) of signals among the capacity switching signals CSEL #1, . . . , and #n to the high state and sets the other capacity switching signals CSEL to the low state based on the mode signal MODE, for example, in the read period excluding the negative potential stabilization waiting period (for example, the global shutter period) illustrated in
Further, based on the mode signal MODE, for example, in the negative potential stabilization waiting period illustrated in
As explained above, the power consumption of the charge pump 122b as a whole can be suppressed by changing the number of capacitors that perform the pumping operation based on the mode signal MODE. The driving capability of the charge pump 122b as a whole can be increased by increasing the number of capacitors that perform the pumping operation.
Since a charge amount accumulated in the capacitors Cfly_1, Cfly_2, . . . , and Cfly_n changes by a feedback voltage supplied from the amplifier 204, a charge supply amount does not change at least near a target negative potential irrespective of the number of capacitors Cfly that perform the pumping operation. However, driver amplifiers that drive the switch circuits 2111 and 2121, 2112 and 2122, . . . , and 211n and 212n for causing the capacitors Cfly_1, Cfly_2, . . . , and Cfly_n to perform the pumping operation are always operated. Therefore, it is meaningful to stop a set of switch circuits corresponding to the capacitors that do not perform the pumping operation among the capacitors Cfly_1, Cfly_2, . . . , and Cfly_n and the driver amplifier that drives the switch circuits.
Note that the control methods are independent from one another in the example in which the driving capability of the charge pump is controlled according to the frequency of the clock signal according to the first embodiment (and the modifications thereof) explained above, the example in which the driving capability of the charge pump is controlled according to the number of charge pumps to be operated simultaneously according to the second embodiment explained above, and the example in which the driving capability of the charge pump is controlled by making the pumping capacitor variable according to the third embodiment explained above. Therefore, two or more of the first embodiment (and the modifications thereof), the second embodiment, and the third embodiment can be implemented in combination.
It is possible to suppress the power consumption to the utmost limit by, in the blank period, minimizing the number of charge pumps to be simultaneously operated and the pumping capacitor while reducing the frequency of the clock signal for driving the charge pump with the method in the first embodiment (and the modifications thereof).
Subsequently, a fourth embodiment is explained. In the first embodiment and the modifications thereof and the second embodiment and the third embodiment explained above, the imaging element 4 is formed on one chip. This is not limited to this example. It is also possible to form the imaging element 4 to be divided into a plurality of chips and form the imaging element 4 as a stacked structure in which the plurality of chips is bonded together. The fourth embodiment is an example in which the imaging element 4 explained above is formed by being divided into two chips and the two chips are bonded together to form a stacked structure.
Through-electrode portions 4010a and 4010b in which one or more through-electrodes 4011 are respectively disposed are provided around the pixel region 410 of the first substrate 401. The through-electrodes 4011 are connected to signal lines and power supply lines of the pixel array unit 100 arranged in the pixel region 410. Similarly, through-electrode portions 4020a and 4020b in which one or more through-electrodes 4021 are respectively disposed are provided around the circuit region 420 of the second substrate 402. The through-electrodes 4021 disposed in the through-electrode portions 4020a and 4020b and the through-electrodes 4011 disposed on the first substrate 401 are disposed at positions corresponding to each other.
When the first substrate 401 and the second substrate 402 are bonded together, the through-electrode 4011 of the first substrate 401 and the through-electrode 4021 of the second substrate 402, the position of which corresponds to the through-electrode 4011, are connected via connecting portions 430. Parts included in the pixel region 410 and parts included in the circuit region 420 are electrically connected. Accordingly, the imaging element 4a is configured as one solid-state imaging element. A connection scheme of the connecting portion 430 is not particularly limited. However, for example, direct bonding using copper (Cu) can be applied.
In the example illustrated in
The signal lines led out from the vertical drive unit 112 of the vertical scanning unit 110 are connected to the through-electrodes 4021 included in the through-electrode portion 4020a and are connected to the pixel signal lines 11 of the pixel array unit 100 provided on the first substrate 401 from the through-electrodes 4021 via the connecting portions 430 and the through-electrode 4011 corresponding to the through-electrodes 4021. Similarly, the signal lines led out from the column processing unit 114 are connected to the through-electrodes 4021 included in the through-electrode portion 4020b and are connected to the vertical signal lines VSL of the pixel array unit 100 provided on the first substrate 401 from the through-electrodes 4021 via the connecting portions 430 and the through-electrodes 4011 corresponding to the through-electrodes 4021.
The terminals 130 to 134 are provided to perform electrical connection to the outside of the second substrate 402. That is, in the example illustrated in
The disposition of the units illustrated in
In the above explanation, an example in which the imaging element 4a is configured in a two-layer stacked structure is explained. However, this is not limited to this example. For example, the imaging element 4a may be configured in a stacked structure of three or more layers. In this case, for example, it is conceivable to provide the pixel region 410 and the circuit region 420 explained above respectively in a first layer and a second layer and provide a memory region including a memory that accumulates an imaging signal output from the buffer amplifier 116 in a third layer.
Subsequently, as a fifth embodiment, an application example of the imaging element 4 or the imaging element 4a according to the first embodiment and the modifications thereof and the second, third, and fourth embodiments of the present disclosure are explained.
The imaging elements 4 and 4a explained above can be used, for example, in various cases in which light such as visible light, infrared light, ultraviolet light, and X-rays is used for sensing as described below.
As an application example of the imaging elements 4 and 4a according to the present disclosure, a more specific example in a case where the imaging element 4 or 4a is mounted on a vehicle and used is explained.
A vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example illustrated in
The drive system control unit 12010 controls the operation of devices relating to a drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a driving force generation device for generating a driving force for the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting a steering angle of the vehicle, a braking device for generating a braking force for the vehicle, and the like.
The body system control unit 12020 controls operations of various devices mounted on a vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as a head lamp, a back lamp, a brake lamp, a blinker, or a fog lamp. In this case, radio waves transmitted from a portable device that substitutes for a key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals and controls a door lock device, a power window device, the lamps, and the like of the vehicle.
The vehicle exterior information detection unit 12030 detects information on the outside of the vehicle on which the vehicle control system 12000 is mounted. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing for a person, a vehicle, an obstacle, a sign, a character on a road surface, or the like based on the received image.
The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal corresponding to an amount of the received light. The imaging unit 12031 can output the electric signal as an image or can output the electric signal as distance measurement information. The light received by the imaging unit 12031 may be visible light or may be invisible light such as infrared rays.
The vehicle interior information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects a state of a driver is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on detection information input from the driver state detection unit 12041, the vehicle interior information detection unit 12040 may calculate a degree of fatigue or a degree of concentration of a driver or may determine whether the driver is dozing off.
The microcomputer 12051 can calculate a control target value of the driving force generation device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040 and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for the purpose of implementing functions of an advanced driver assistance system (ADAS) including collision avoidance or impact mitigation for the vehicle, following travel based on an inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, vehicle lane departure warning, or the like.
By controlling the driving force generation device, the steering mechanism, the braking device, or the like based on information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can perform cooperative control for the purpose of automatic driving or the like in which the vehicle autonomously travels without depending on the operation of the driver.
The microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control a head lamp according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030 and perform cooperative control for the purpose of preventing glare such as switching from a high beam to a low beam.
The sound and image output unit 12052 transmits an output signal of at least one of sound or an image to an output device capable of visually or audibly notifying an occupant of the vehicle or the outside of the vehicle of information. In the example illustrated in
The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, in positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper portion of a windshield in a vehicle interior of the vehicle 12100. The imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper portion of the windshield in the vehicle interior mainly acquire images in the front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100. Front images acquired by the imaging units 12101 and 12105 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
Note that
At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements or may be an imaging element including pixels for phase difference detection.
For example, the microcomputer 12051 can obtain distances to three-dimensional objects in the imaging ranges 12111 to 12114 and temporal changes of the distances (relative speed with respect to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104 to thereby extract, as a preceding vehicle, in particular, a closest three-dimensional object present on a traveling path of the vehicle 12100, the three-dimensional object traveling at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in the front of the preceding vehicle and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), and the like. As explained above, it is possible to perform cooperative control for the purpose of automatic driving or the like in which the vehicle autonomously travels without depending on the operation of the driver.
For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, extract the three-dimensional object data, and use the three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver to visually recognize. the microcomputer 12051 can determine a collision risk indicating a risk of collision with obstacles and, when the collision risk is a set value or more and there is a possibility of collision, perform driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062 or performing forced deceleration or avoidance steering via the drive system control unit 12010.
At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in captured images of the imaging units 12101 to 12104. Such pedestrian recognition is performed by, for example, a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 functioning as infrared cameras and a procedure for performing pattern matching processing on a series of feature points indicating the contour of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the sound and image output unit 12052 controls the display unit 12062 to superimpose and display a square contour line for emphasis on the recognized pedestrian. The sound and image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian in a desired position.
The example of the vehicle control system to which the technique according to the present disclosure can be applied is explained above. The technique according to the present disclosure can be applied to, for example, the imaging unit 12031 among the components explained above. Specifically, the imaging element 4 or 4a according to the first embodiment and the modifications thereof and the second, third, and fourth embodiments of the present disclosure can be applied to the imaging unit 12031. By applying the technique according to the present disclosure to the imaging unit 12031, it is possible to reduce power consumption in the imaging unit 12031. For example, when the imaging unit 12031 is driven by a battery, operation for a longer time is possible.
Note that the effects described in this specification are only illustrations and are not limited. Other effects may be present.
Note that this technique can also take the following configurations.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2019-207407 | Nov 2019 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/040159 | 10/27/2020 | WO |
