The present invention relates to an imaging panel and an X-ray imaging device including the same.
An X-ray imaging device has been known that picks up an X-ray image by using an imaging panel that includes a plurality of pixels. Patent Document 1 shown below discloses an X-ray sensor in which each pixel includes a thin film transistor (TFT) made of an oxide semiconductor, and a photodiode. To form the TFT of this X-ray sensor, an oxide semiconductor containing indium, gallium, zinc, and oxygen is used.
Incidentally, the source and the drain of the TFT in which an oxide semiconductor containing indium, gallium, zinc, and oxygen is used are formed by forming a film of a metal such as aluminum on the oxide semiconductor and subjecting the metal film to dry-etching. An oxide semiconductor containing indium, gallium, zinc, and oxygen has a low acid etching resistance, and hence, it is difficult to carry out wet etching using an acid etching solution suitable for etching aluminum o the like. Dry etching is therefore often used for forming a source and a drain. When, however, etching damage occurs due to dry etching on the surface of the oxide semiconductor, defect levels are formed at an interface between the oxide semiconductor and an insulating film such as a silicon nitride film formed on the oxide semiconductor. Defect levels cause the threshold value of the TFT to shift toward the negative direction, thereby making it difficult to cause the TFT to stably operate.
Besides, though the oxide semiconductor containing indium, gallium, zinc, and oxygen has a high electron mobility as compared with an amorphous semiconductor, it is desirable to use an oxide semiconductor that has a further higher electron mobility, in order to further reduce the amount of X-ray irradiated on an object.
It is an object of the present invention to provide an imaging panel and an imaging device with which the amount of irradiated X-ray can be reduced, and at the same time, the threshold voltage of the TFT during X-ray irradiation can be prevented from shifting.
An imaging panel according to the present invention includes: an imaging part that includes a pixel that receives X-ray and outputs charges corresponding to the received X-ray; and a thin film transistor for reading out the charges at the pixel. The thin film transistor includes: a gate; an oxide semiconductor layer; and a source and a drain formed on a part of the oxide semiconductor layer, the source and the drain being formed by wet etching with respect to a metal film formed on the oxide semiconductor layer, wherein the oxide semiconductor layer includes an ITZO layer that contains indium, tin, gallium, and oxygen.
With the configuration of the present invention, the amount of irradiated X-ray can be reduced, and at the same time, the threshold voltage of the TFT during X-ray irradiation can be prevented from shifting.
An imaging panel according to an embodiment of the present invention includes: an imaging part that includes a pixel that receives X-ray and outputs charges corresponding to the received X-ray; and a thin film transistor for reading out the charges at the pixel. The thin film transistor includes: a gate; an oxide semiconductor layer; and a source and a drain formed on a part of the oxide semiconductor layer, the source and the drain being formed by wet etching with respect to a metal film formed on the oxide semiconductor layer, wherein the oxide semiconductor layer includes an ITZO layer that contains indium, tin, gallium, and oxygen.
In the first configuration, the imaging panel includes an imaging part and a thin film transistor. The imaging part includes a pixel that outputs charges based on X-ray. Charges at the pixel are read out through the thin film transistor. The thin film transistor includes a gate and an oxide semiconductor layer, as well as a source and a drain that are formed on a part of the oxide semiconductor layer by wet etching with respect to a metal film formed on the oxide semiconductor layer. The oxide semiconductor layer includes an ITZO layer that contains indium, tin, gallium, and oxygen. With this configuration, the amount of irradiated X-ray can be reduced, since the ITZO layer has a high electron mobility. Besides, since the source and the drain are formed by using wet etching, it is less likely that etching damage would occur to the oxide semiconductor layer, as compared with a case where the source and the drain are formed by using dry etching. As a result, it is less likely that the threshold voltage of the thin film transistor would shift toward the negative direction, which makes it possible to reduce the amount of shift of the threshold voltage during X-ray irradiation.
The second configuration may be the first configuration further characterized in that the oxide semiconductor layer further includes a semiconductor layer that is provided on the ITZO layer and contains indium and oxygen, as well as at least one of tin, zinc, gallium, and tungsten.
According to the second configuration, the source and the drain are formed on a part of the semiconductor layer by carrying out wet etching with respect to the metal film formed on the semiconductor layer. This makes it possible that the channel area in the ITZO layer should be protected by the semiconductor layer from etching damage, and therefore, the shift amount of the threshold voltage of the thin film transistor can be reduced.
The third configuration may be the first configuration or the second configuration further characterized by further including an insulating film provided on the thin film transistor and a conductive part provided at a position opposed to the thin film transistor, in an upper layer above the insulating film, and the conductive part may be connected with the gate or the source through a contact hole formed in the insulating film.
In the third configuration, carriers (holes) trapped by defect levels formed between the insulating film and the oxide semiconductor layer are recombined with carriers (electrons) induced in the insulating film on the oxide semiconductor layer depending on the potential of the conductive part. As a result, carriers trapped at the interface between the insulating film and the oxide semiconductor layer are reduced, whereby the threshold voltage of the thin film transistor can be prevented from shifting toward the negative direction.
An imaging panel according to an embodiment of the present invention includes: an imaging part that includes a pixel that receives X-ray and outputs charges corresponding to the received X-ray; a thin film transistor for reading out the charges at the pixel; an insulating film provided on the thin film transistor; and a conductive part provided at a position opposed to the thin film transistor, in an upper layer above the insulating film. The thin film transistor includes: a gate; an oxide semiconductor layer; a source provided on the oxide semiconductor layer; and a drain provided on the oxide semiconductor layer. In the imaging panel, the oxide semiconductor layer includes an ITZO layer that contains indium, tin, gallium, and oxygen; and the conductive part is connected with the gate or the source through a contact hole formed in the insulating film (the fourth configuration).
In the fourth configuration, the imaging panel includes an imaging part, a thin film transistor, an insulating film, and a conductive part. The imaging part includes a pixel that outputs charges based on the X-ray, and the charges at the pixel are read out through the thin film transistor. The oxide semiconductor layer of the thin film transistor includes an ITZO layer that contains indium, tin, gallium, and oxygen. With this configuration, the amount of irradiated X-ray can be reduced, since the ITZO layer has a high electron mobility. Further, in the fourth configuration, the conductive part is provided at a position opposed to the oxide semiconductor layer of the thin film transistor, in an upper layer above the insulating film, and is connected with the gate or the source through a contact hole formed in the insulating film. With this configuration, therefore, carriers (holes) trapped by defect levels formed between the insulating film and the oxide semiconductor layer are recombined with carriers (electrons) induced in the insulating film on the oxide semiconductor layer depending on the potential of the conductive part. As a result, carriers trapped at the interface between the insulating film and the oxide semiconductor layer are reduced, whereby the threshold voltage of the thin film transistor can be prevented from shifting toward the negative direction.
The fifth configuration may be the fourth configuration further characterized in that the oxide semiconductor layer further includes a semiconductor layer that is provided on the ITZO layer and contains indium and oxygen, as well as at least one of tin, zinc, gallium, and tungsten.
According to the fifth configuration, a semiconductor layer is further provided on the ITZO layer. In a case where, therefore, the source and the drain are formed by dry etching or wet etching, the channel area in the oxide semiconductor layer can be protected from etching damage.
An X-ray imaging device according to an embodiment of the present invention includes: the imaging panel of any one of the first to fifth configurations; an X-ray source that projects X-ray to the imaging panel; and a control unit that controls a gate voltage of the thin film transistor in the imaging panel, and reads out a signal corresponding to charges generated at the pixel in the imaging panel (the sixth configuration).
The following description describes embodiments of the present invention in detail, while referring to the drawings. Identical or equivalent parts in the drawings are denoted by the same reference numerals, and the descriptions of the parts are not repeated.
Each pixel 13 is provided with a thin film transistor (TFT) 14 connected to the gate line 11 and the data line 12 and a photodiode 15 connected to the TFT 14. Further, though the illustration is omitted in
In each pixel 13, scintillation light obtained by converting X-ray having passed through the subject S is converted by the photodiode 15 into charges in accordance with the amount of the light.
The gate lines 11 in the imaging panel 10 are switched sequentially to a selected state one by one by a gate control part 20A, and the TFTs 14 connected to the gate line 11 in the selected state are turned ON. When the TFTs 14 shift to the ON state, data signals corresponding to charges obtained by conversion by the photodiode 15 are output via the data lines 12 to a signal reading part 20B.
Next, the following description describes a specific configuration of the pixel 13.
As illustrated in
The TFT 14 includes a gate electrode 141, an oxide semiconductor layer 142 arranged on the gate electrode 141 with a gate insulating film 41 being interposed therebetween, and a source electrode 143S as well as a drain electrode 143D connected to the oxide semiconductor layer 142.
The gate electrode 141 is formed in contact with one of surfaces in the thickness direction of the substrate 40. The gate electrode 141 is composed of a branch of the gate line 11 that is branched in a direction in which the data line 12 extends, as illustrated in
As illustrated in
In order to prevent diffusion of impurities and the like from the substrate 40, the gate insulating film 41 may have a laminate structure. For example, silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x>y), or the like may be used in a lower layer; and silicon oxide (SiOx), silicon oxide nitride (SiOxNy) (x>y), or the like may be used in an upper layer. Further, in order that a fine gate insulating film that allows a smaller gate leakage current is formed at a low film forming temperature, a noble gas element such as argon may be contained in a reaction gas so as to be included in the insulating film.
As illustrated in
The source electrode 143S and the drain electrode 143D are formed in contact with the first oxide semiconductor layer 142 and the gate insulating film 41. As illustrated in
The source electrode 143S, and the drain electrode 143D are formed in an identical layer. The source electrode 143S and the drain electrode 143D are made of, for example, a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu) or the like, or an alloy of any of these, or nitride of any of these metals. Further, as a material for the source electrode 143S and the drain electrode 143D, the following may be used: a material having translucency such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide (ITSO) containing silicon oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), or titanium nitride; or an appropriate combination of any of these. The source electrode 143S and the drain electrode 143D may be obtained by, for example, laminating a plurality of metal films.
The interlayer insulating film 42 covers the oxide semiconductor layer 142, the source electrode 143S, and the drain electrode 143D. The interlayer insulating film 42 may have a single layer structure made of silicon oxide (SiO2) or silicon nitride (SiN), or a laminate structure obtained by laminating silicon nitride (SiN) and silicon oxide (SiO2) in this order. In the present embodiment, the interlayer insulating film 42 has a film thickness of, for example, about 0.5 μm.
The flattening film 43 is formed on the interlayer insulating film 42, so as to cover the interlayer insulating film 42. As a material for the flattening film 43, for example, an organic resin such as polyimide can be used. In the present embodiment, the flattening film 43 has a film thickness of, for example, about 2 to 3 μm.
The photodiode 15 covers the flattening film 4, and is formed in contact with the drain electrode 143D via the contact hole CH1 that passes through the organic film 43 and the interlayer insulating film 42. The photodiode 15 includes an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, and a p-type amorphous silicon layer (neither illustrated). The n-type amorphous silicon layer is made of amorphous silicon in which an n-type impurity (for example, phosphorus) is doped. The n-type amorphous silicon layer is formed in contact with the drain electrode 143D. The n-type amorphous silicon layer has a thickness of, for example, 20 to 100 nm. The intrinsic amorphous silicon layer is made of intrinsic amorphous silicon. The intrinsic amorphous silicon layer is formed in contact with the n-type amorphous silicon layer. The intrinsic amorphous silicon layer has a thickness of, for example, 200 to 2000 nm. The p-type amorphous silicon layer is made of amorphous silicon in which p-type an impurity (for example, boron) is doped. The p-type amorphous silicon layer is formed in contact with the intrinsic amorphous silicon layer. The p-type amorphous silicon layer has a thickness of, for example, 10 to 50 nm.
The electrode 44 is formed on the photodiode 15, and functions as an upper electrode of the photodiode 15. The electrode 44 supplies the voltage of the bias line 16 described below as a reference voltage (bias voltage) in the photoelectric conversion, to the photodiode 15. As a material for forming the electrode 44, for example, a transparent conductive film of indium tin oxide (ITO), indium zinc oxide (IZO), or the like can be used.
The bias line 16 is formed on the electrode 44, and as illustrated in
The protection film 45 is formed so as to cover the electrode 44 and the bias line 16. The protection film 45 may have a single layer structure made of silicon oxide (SiO2) or silicon nitride (SiN), or alternatively, may have a laminate structure obtained by laminating silicon nitride (SiN) and silicon oxide (SiO2) in this order.
Though the illustration is omitted in
Referring to
As illustrated in
As illustrated in
The image processing part 20C generates an X-ray image signal based on the image signals output from the reading part 20B.
The voltage control part 20D is connected to the bias lines 16 (see
The timing control part 20E controls timings of operations of the gate control part 20A, the signal reading part 20B, and the voltage control part 20D.
The gate control part 20A selects one gate line 11 from among a plurality of the gate lines 11, based on the control signal from the timing control part 20E. The gate control part 20A applies a predetermined gate voltage, through the selected gate line 11, to the TFTs 14 that are connected to the selected gate line 11.
The signal reading part 20B selects one data line 12 from among a plurality of the data lines 12 based on the control signal from the timing control part 20E. Through the selected data line 12, the signal reading part 20B reads out a data signal corresponding to charges obtained by conversion by the photodiode 15 in the pixel 13. The pixel 13 from which a data signal is read out is connected to the data line 12 selected by the signal reading part 20B, and is connected to the gate line 11 selected by the gate control part 20A.
The timing control part 20E, for example, outputs a control signal to the voltage control part 20D when X-ray is emitted from the X-ray source 30. Based on this control signal, the voltage control part 20D applies a predetermined bias voltage to the electrode 44.
First, X-ray is emitted by the X-ray source 30. Here, the timing control part 20E outputs a control signal to the voltage control part 20D. More specifically, for example, a signal that indicates that X-ray is emitted from the X-ray source 30 is output from the control device that controls operations of the X-ray source 30, to the timing control part 20E. When this signal is input to the timing control part 20E, the timing control part 20E outputs the control signal to the voltage control part 20D. The voltage control part 20D applies a bias voltage to the bias line 16 based on the control signal from the timing control part 20E.
The X-ray emitted from the X-ray source 30 passes through the subject S, and becomes incident on the scintillator 10A. The X-ray incident on the scintillator 10A is converted to scintillation light, and the scintillation light becomes incident on the imaging panel 10.
When the scintillation light becomes incident on the photodiode 15 provided in each pixel 13 in the imaging panel 10, the scintillation light is converted by the photodiode 15 into charges corresponding to the amount of the scintillation light.
A data signal corresponding to the charges obtained by conversion by the photodiode 15 is read out by the signal reading part 20B through the data line 12 when the TFT 14 is caused to be in an ON state in response to a gate voltage (positive voltage) that is output from the gate control part 20A through the gate line 11. An X-ray image corresponding to the data signal thus read out is generated by the image processing part 20C.
Next, the following describes a method for producing the imaging panel 10.
At the step illustrated in
After the gate electrode 141 is formed, the gate insulating film 41 made of silicon oxide (SiOx), silicon nitride (SiNx), or the like is formed on the substrate 40 by plasma CVD, sputtering, or the like, so as to cover the gate electrode 141. The gate insulating film 41 has a thickness of, for example, 20 to 150 nm.
Subsequently, at the step illustrated in
Next, after the first oxide semiconductor layer 142 is formed, for example, a metal film containing aluminum is formed on the gate insulating film 41, and on the oxide semiconductor layer 142, by sputtering or the like. Then, this metal film is patterned by photolithography, and is subjected to wet etching with use of an inorganic acid etching liquid containing phosphoric acid, nitric acid, acetic acid, or the like. Through this process, the source electrode 143S, the data line 12 and the drain electrode 143D are formed, whereby the bottom gate type TFT 14 is formed. The thickness of the source electrode 143S and the drain electrode 143D is, for example, 50 to 500 nm.
Next, at the step illustrated in
After the interlayer insulating film 42, at the step illustrated in
After the flattening film 43 is formed, at the step illustrated in
Subsequently, at the step illustrated in
After the electrode 44 is formed, at the step illustrated in
The first oxide semiconductor layer 142 in Embodiment 1 described above contains indium, tin, and gallium. The first oxide semiconductor layer 142 has a high acid etching resistance, as compared with an oxide semiconductor containing indium, gallium, and zinc. The source electrode 143S and the drain electrode 143D, therefore, can be formed by wet etching using an etching solution of an inorganic acid containing phosphoric acid, nitric acid, acetic acid, or the like. As a result, as compared with a case where dry etching is performed, etching damage with respect to a surface of the first oxide semiconductor layer 142 that is not in contact with the gate insulating film 41 (the surface on the back channel side) can be reduced.
Let the shift amount of the threshold voltage illustrated in
Embodiment 1 described above is described with reference to an exemplary case where the oxide semiconductor layer in the TFT 14 has a single layer structure composed of the first oxide semiconductor layer 142. The present embodiment is different from Embodiment 1 regarding the point that the oxide semiconductor layer has a laminate structure. Hereinafter, the point different from Embodiment 1 is described.
The first oxide semiconductor layer 142a is formed with an oxide semiconductor containing indium, tin, and gallium, as is the case with the first oxide semiconductor layer 142 in Embodiment 1.
The second oxide semiconductor layer 142b in this example is formed with, for example, an oxide semiconductor containing indium, gallium, and zinc.
On the second oxide semiconductor layer 142b, a source electrode 143S and a drain electrode 143D are provided.
In the present embodiment, as is the case with Embodiment 1, the source electrode 143S and the drain electrode 143D are formed by performing wet etching. More specifically, as illustrated in
The second oxide semiconductor layer 142b containing indium, gallium, and zinc has a low acid etching resistance, and hence, the second oxide semiconductor layer 142b, other than the portions thereof where the source electrode 143S and the drain electrode 143D, is dissolved by wet etching. On the other hand, the first oxide semiconductor layer 142a containing indium, tin, and gallium has a high acid etching resistance, and hence, is not dissolved by wet etching. As illustrated in
In Embodiment 2, the oxide semiconductor layer 1421 in the TFT 14A has a laminate structure composed of the first oxide semiconductor layer 142a and the second oxide semiconductor layer 142b. In a case where wet etching using the etching solution of an inorganic acid is performed in the step for forming the source electrode 143S and the drain electrode 143D in the TFT 14A, the second oxide semiconductor layer 142b in the area between the source electrode 143S and the drain electrode 143D is dissolved, but the first oxide semiconductor layer 142a is not dissolved, whereby the channel area can be protected by the second oxide semiconductor layer 142b.
Embodiment 2 described above is described with reference to an exemplary case where the second oxide semiconductor layer 142b is formed with an oxide semiconductor containing indium, gallium, and zinc, but the second oxide semiconductor layer 142b is not limited to this. The second oxide semiconductor layer 142b may be formed with, for example, any one of indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium zinc oxide (IZO), and indium tin oxide (ITO). In other words, the second oxide semiconductor layer 142b is formed with an oxide semiconductor that contains: indium (In); oxygen (O); and at least one of tin (Sn), zinc (Zn), gallium (Ga), and tungsten (W).
Embodiment 1 described above is described with reference to an exemplary case where the source electrode 143S and the drain electrode 143D are formed by carrying out wet etching, whereby etching damage with respect to the oxide semiconductor layer is reduced and the threshold voltage of the TFT 14 is prevented from shifting. Hereinafter, another configuration in which the threshold voltage of the TFT 14 can be prevented from shifting even if the source electrode 143S and the drain electrode 143D are formed by carrying out dry etching is described below as the present embodiment.
As illustrated in
The conductive film 46 may be formed with, for example, the same material as that of the gate electrode 141, or alternatively, may be formed with a transparent conductive film of indium tin oxide (ITO), indium zinc oxide (IZO), or the like.
As is the case with Embodiment 1, at the step illustrated in
Then, as is the case with the steps illustrated in
Subsequently, as illustrated in
In Embodiment 3 described above, dry etching is performed in order to form the source electrode 143S and the drain electrode 143D. The dry etching causes etching damage to the surface (on the back channel side) of the first oxide semiconductor layer 142, thereby causing defect levels to be formed on the back channel side, which causes the threshold value of the TFT 14 to tend to shift. In Embodiment 3, however, as illustrated in
Here,
Let the shift amount of the threshold voltage illustrated in
Further, the first oxide semiconductor layer 142 in the TFT 14 is formed with an oxide semiconductor that contains indium, tin, and gallium. Since the first oxide semiconductor layer 142 has a higher electron mobility, as compared with a case where it is formed with an oxide semiconductor containing indium, gallium, and zinc, the amount of irradiated X-ray can be reduced, as compared with the case where an oxide semiconductor containing indium, gallium, and zinc is used for forming the TFT 14.
Embodiment 3 described above is described with reference to an exemplary case where the oxide semiconductor layer in the TFT 14 has a single layer structure composed of the first oxide semiconductor layer 142. The present embodiment is different from Embodiment 3 regarding the point that the oxide semiconductor layer of the TFT 14 has a laminate structure composed of the first oxide semiconductor layer 142a and the second oxide semiconductor layer 142b as is the case with Embodiment 2. Hereinafter, the point different from Embodiment 3 is described.
In the present embodiment, the source electrode 143S and the drain electrode 143D formed by carrying out dry etching are provided on the second oxide semiconductor layer 142b. In the case where dry etching is used, the film thickness h of the oxide semiconductor layer 1422 in areas where the source electrode 143S and the drain electrode 143D are formed, and the film thickness h thereof where the source electrode 143S formed and the drain electrode 143D are not formed, are approximately the same, unlike Embodiment 2 in which the source electrode 143S and the drain electrode 143D are formed by using wet etching (see
Etching damage occurs to the surface of the second oxide semiconductor layer 142b when dry etching is carried out, but the first oxide semiconductor layer 142a is protected by the second oxide semiconductor layer 142b. The channel area of the TFT 14B, therefore, is not damaged by dry etching, and the threshold voltage of the TFT 14B during X-ray irradiation can be prevented from shifting.
Embodiments of the present invention are described above, but these embodiments described are merely examples for implementing the present invention. The present invention, therefore, is not limited by the embodiments described above at all, and the above-described embodiments can be appropriately changed and implemented within a range that is not deviated from the scope of the invention. The following description describes modification examples of the present invention.
(1) In Embodiment 1 or Embodiment 2 described above, a conductive film 46 identical to that in Embodiment 3 may be provided. With such a configuration, defect levels formed on the back channel side of the TFT 14 or 14A can be reduced, whereby the shift amount of the threshold of the TFT 14 or 14B can be reduced further, as compared with Embodiments 1 and 2.
(2) Embodiments 3 and 4 described above are described with reference to an exemplary case where dry etching is carried out when the source electrode 143S and the drain electrode 143D are formed, but wet etching may be carried out in place of dry etching for forming the source electrode 143S and the drain electrode 143D.
With such a configuration, in the case of Embodiment 3, that is, in the case where the oxide semiconductor layer of the TFT 14 has a single layer structure formed with the first oxide semiconductor layer 142, etching damage occurring on the surface of the first oxide semiconductor layer 142 is reduced as compared with the case where dry etching is carried out, and the shift amount of the threshold voltage of the TFT 14 during X-ray irradiation can be reduced further.
Still further, in the case of Embodiment 4, that is, in the case where the oxide semiconductor layer of the TFT 14B has a laminate structure composed of the first oxide semiconductor layer 142a and the second oxide semiconductor layer 142b, a part of the second oxide semiconductor layer 142b is dissolved by wet etching that uses an acid etching solution. The first oxide semiconductor layer 142a, however, is not dissolved by wet etching, and hence, the channel area can be protected by the second oxide semiconductor layer 142b. As a result, as compared with Embodiment 4, the shift amount of the threshold voltage of the TFT during X-ray irradiation can be reduced.
(3) Embodiments 3 and 4 described above are described with reference to an exemplary case where the conductive film 46 is formed with a material equivalent to that of the gate electrode 141, and is electrically connected with gate electrode 141. The configuration, however, may be such that the conductive film 46 is formed with a material equivalent to that of the source electrode 143S, and is electrically connected with the source electrode 143S. In the case of this configuration, the conductive film 46 has the same potential as that of the source electrode 143S. Carriers induced by the potential of the conductive film 46 at the interface between the flattening film 43 and the interlayer insulating film 42, and carriers trapped by the defect levels formed on the back channel side of the TFT 14, 14B are recombined, whereby the carriers trapped on the back channel side can be reduced.
(4) Still further, Embodiments 3 and 4 described above are described with reference to an exemplary case where the conductive film 46 is provided on the flattening film 43, but the configuration may be such that the flattening film 43 is not provided and the conductive film 46 is provided on the interlayer insulating film 42. This configuration makes the distance between the conductive film 46 and the oxide semiconductor layer 142 smaller. As a result, carriers (holes) trapped on the back channel side of the TFT 14, 14B, and carriers (electrons) induced at the interface of the interlayer insulating film 42 tend to be recombined, whereby the carriers trapped on the back channel side of the TFT 14, 14B can be reduced further.
Number | Date | Country | Kind |
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2015-084981 | Apr 2015 | JP | national |
Filing Document | Filing Date | Country | Kind |
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PCT/JP2016/061890 | 4/13/2016 | WO | 00 |