1. Field of the Invention
The present disclosure relates to the field of imaging, and specifically to imaging circuitry having an imaging pixel array with a programmable pixel aspect ratio for an optical code reader.
2. Description of the Related Art
CCD or CMOS-based imaging devices, such as barcode imagers, generally have a CCD array or other imaging pixel array having a plurality of photosensitive elements or pixels. Each pixel of the pixel array has a fixed aspect ratio (i.e., width-to-height). The aspect ratio of the pixels is generally determined by the type and/or density of the images, e.g., bar codes, to be read by the imaging device.
For reading lower density barcodes, or poorly printed lower density barcodes, pixels with large aspect ratios are more desirable. A pixel with a large aspect ratio provides the benefits of increasing the light collection area and reducing the noise produced by the pixel itself (increasing signal-to-noise (S/N) ratio), as well as filtering out or integrating small defects or voids found in the barcode.
This same large aspect ratio pixel, however, generally compromises the imaging device's performance on correctly reading higher density barcodes, such as PDF417 barcode symbols. In particular, the imaging device's tilt performance, or ability to correctly read a barcode when the imaging device is angularly positioned from the barcode, is compromised by the large pixel aspect ratio. To improve the tilt performance of the imaging device, the aspect ratio of each pixel of the imaging pixel array needs to be small so as to minimize smearing from adjacent elements of the barcode. Reducing the aspect ratio, however, reduces the signal-to-noise (S/N) ratio because the light collection area is reduced, and the noise contributed by each pixel is increased.
Furthermore, smaller pixels generally require more light for illumination and require longer shutter (exposure) time to improve the S/N ratio, resulting in a system which requires more power for illumination and longer processing times.
According to the above, there exists a need in the field of imaging for imaging circuitry that can be incorporated within an image-based one- or multi-dimensional barcode imager for imaging both low and high density indicia or symbols, including barcodes, labels, markings, pictures, etc., without compromising the performance of the optical code reader.
An aspect of the present disclosure is to provide imaging circuitry having a programmable imaging pixel array, such as a programmable CMOS imaging array, which improves the signal-to-noise (S/N) ratio by combining the signal outputs of two or more adjacent pixels of the imaging pixel array. This results in a summation of the generated charge carriers from the single pixels and reduces readout time (e.g., fewer pixels to read).
The imaging circuitry having a programmable imaging pixel array and barcode imager incorporating the same of the present disclosure achieve this and other aspects by allowing the aspect ratio of each pixel of the imaging pixel array to be changed to better match the type of barcode being imaged. For lower density barcodes that are far away from the barcode imager, for example, the aspect ratio of the imaging pixel array can be programmed on the fly to optimize the aspect ratio and thereby increase the signal-to-noise (S/N) ratio in the received signal. When reading high density barcodes, such as PDF417 barcode symbols, the aspect ratio of the imaging pixel array can also be programmed on the fly to obtain an aspect ratio which does not compromise the performance of the barcode imager.
Various embodiments of the present disclosure will be described herein below with reference to the figures wherein:
With reference to
It is preferred that the imaging circuitry 100, 200 or portions thereof are provided or packaged in the form of an imaging engine 303 as shown by
With reference to
Each pixel 108 generates a pixel signal corresponding to a portion of the image captured by the pixel 108. The pixel signals from each row of pixels 104, 106 are transmitted to corresponding processing circuits 112 where the pixel output data provided by each pixel signal are processed. The processing circuits 112 include conventional pixel processing circuits as known in the art for processing the pixel output data, for example, analog-to-digital converters (ADC).
The imaging circuitry 100 further includes a pixel processor 114 for obtaining the processed pixel output data corresponding to each pixel 108 from the processing circuits 112. It is contemplated that the processing circuits 112 can be integrated within the pixel processor 114. Preferably, the pixel processor 114 is a state machine that executes a series of programmable instructions for evaluating the processed pixel output data corresponding to each pixel 108 of the imaging pixel array 102. Based upon the evaluation, the pixel processor 114 determines whether or not to combine or add the pixel signals from any pixel in either row 104, 106, e.g., pixel A1-A18 and pixel B1-B18, thereby varying the aspect ratio of the imaging pixel array 102.
That is, the pixel processor 114 determines whether or not to combine or add the pixel signal corresponding to the leftmost pixel A1 of the first row 104 with the pixel signal corresponding to the leftmost pixel B1 of the second row 106; the pixel signal corresponding to the pixel adjacent to the leftmost pixel A2 of the first row 104 with the pixel signal corresponding to the pixel adjacent to the leftmost pixel B2 of the second row 106; and so on up to the pixel signal corresponding to the rightmost pixel A18 of the first row 104 with the pixel signal corresponding to the rightmost pixel B18 of the second row 106. Furthermore, the pixel processor 114 may combine any two pixels from either row to increase the S/N ratio. For example, under tilt conditions, the pixel processor may combine pixels A2 and B1 to compensate for rotation of the pixel array 102 using autocorrelation techniques as are known in the art. It is further contemplated that the pixels may be combined on a blind cycling scheme to deliver different pixel combinations on a scan by scan basis. For example, after a first scan, just pixels in the first row 104 are used; after a second scan, only pixels in the second row 106 are used; after a third scan, pixels in the first 104 and second 106 row may be combined; and any subsequent scan may combine any random combination of pixels from either the first or second row. It is to be appreciated that several hundreds or thousands of scans of a target will occur upon a single activation of the imaging circuitry without an appreciable delay to the user.
The determination entails determining whether or not the pixel signals as received from the processing circuits 112 and corresponding to the first and second rows 104, 106 would enable decoder 318 to correctly decode the pixel output data transmitted by the pixel signals. If the pixel output data corresponding to either the first or second row of pixels are determined to be decodeable, then the pixel processor 114 determines not to combine or add the pixel signals of corresponding columns 110 of the imaging pixel array 102. The pixel output data as received by the pixel processor 114 are then transmitted to the decoder 318 via channels 118, 119 corresponding to each row.
On the other hand, if the pixel output data corresponding to either the first and second row of pixels are determined to be non-decodeable, then the pixel processor 114 determines to combine or add the pixel signals of corresponding columns 110 of the imaging pixel array 102 in an effort to obtain and transmit a signal to the decoder 318 having decodeable output data. Hence, the imaging pixel array 102 is in effect programmable, since the pixel processor 114 can alter the aspect ratio of the imaging pixel array 102 on the fly to optimize aspect ratio, thereby increasing the signal-to-noise (S/N) ratio in the signal transmitted to the decoder 318.
The pixel processor 114, or the decoder 318, determines whether the pixel output data are decodeable by evaluating one or more of at least the following factors: whether the pixel output data corresponds to a low or high density barcode; the amount of ambient lighting as determined by the array of the barcode imager and/or by analyzing the contrast of the image; whether the imaging pixel array 102 of the barcode imager 302 is tilted or at an angle with respect to the optical code (e.g., barcode) or other indicia/target being imaged; the type of surface the optical code or other indicia/target being imaged is positioned on, such as, for example, a curved surface, a reflective surface (e.g., metallic surface), and/or an irregular (non-smooth) surface; and the distance the imaging pixel array 102 is positioned from the optical code or other indicia/target being imaged as determined by a distance determining assembly of the barcode imaging system 300. In one embodiment, the pixel processor 114 may be a state machine that could autonomously decide how to best combine pixels, or, if a more powerful decoder 318 is employed in the system 100, the pixel processor 114 could be commanded to enter a slave mode where the decoder 318 would then control and decide how to best combine pixels.
Using at least the above factors and/or the fact that by doubling the aspect ratio of the imaging pixel array 102 still resulted in non-decodeable output data, the pixel processor 114 can determine to combine or add the pixel signals of two or more consecutive columns to further increase the aspect ratio of the imaging pixel array 102. For example, the pixel processor 114 can determine to combine the pixel signals of a first column to obtain a first combined pixel signal and to also combine the pixel signals of an adjacent column to obtain a second combined pixel signal. The pixel processor 114 would then combine or add the first and second combined pixel signals. Accordingly, the aspect ratio of the imaging pixel array 102 is further increased as compared to only combining or adding the pixel signals of a single column of the imaging pixel array 102 in an effort to output decodeable output data to the decoder 318.
Alternatively or simultaneously, the pixel processor 114 could process the pixel signals of each row of pixels, i.e., rows 104 and 106, independently using signal processing techniques to obtain a digital signal output for each row. The pixel processor 114 would then send the output of each row to the decoder 318 via channels 118, 119, e.g., an analog or a digital interface, where additional signal processing would be provided. The decoder 318, for example, could use autocorrelation techniques to combine pixels across pixel columns to eliminate blur and smearing in the high tilt case to obtain a composite output signal with improved signal-to-noise (S/N) characteristics. By performing this methodology in the alternative or simultaneously with the methodology of increasing the aspect ratio of the imaging pixel array 102, the imaging circuitry 100 provides a high degree of confidence that the output data are decodeable.
The pixel processor 114 could also determine, or be instructed by the decoder 318, not to combine the signal outputs of each row, but rather transmit to the decoder 318 the output of one or both rows simultaneously, or staggered in time. This method is particularly applicable where the barcode imager 302 is positioned at an angle or is tilted with respect to the barcode or other indicia to be imaged and the pixel processor 114 determines that one row of the imaging pixel array 102 provides a better image (e.g., a better focused image) of the barcode than the other row. Furthermore, staggering the output signals increases the scan rate of the array to remove sensitivity to hand jitter or other movements, i.e., the sampling rate of the array is doubled.
With reference to
Each pixel 208 generates a pixel signal corresponding to a portion of the image captured by the pixel 208. Selective pixel signals are then processed by processing circuits 212, e.g., analog-to-digital converters (ADC). The processing circuits 212 process the pixel signals corresponding to the first row of pixels 204, the pixel signals corresponding to the second row of pixels 206, the pixel signals corresponding to the third row of pixels 207 and any combination thereof. The last processing methodology entails adding the pixel signals from the various rows to increase the aspect ratio of the imaging pixel array 202.
The processing circuits 212 may include a series of programmable instructions for determining whether to process the pixel signals corresponding to the first row of pixels 204, the pixel signals corresponding to the second row of pixels 206, the pixels signals corresponding to the third row of pixels 207 or the pixel signals corresponding to the first, second or third rows of pixels. The series of programmable instructions evaluates or analyzes the pixel signals of each row to determine if the pixel signals of at least one of the two rows includes decodeable pixel output data. The processing circuits 212 will select appropriate rows or pixels to be processed via switching circuitry 216, as will be described below.
The processing circuits 212 determine if the pixel signals include decodeable pixel output data by evaluating or analyzing the focus quality, contrast, sharpness, etc. of the image represented by the pixel output data. If the focus quality, contrast, sharpness and/or other characteristic of the image is determined, for example, to be greater or equal than a predetermined threshold, then the pixel output data are determined to be decodeable; if it is determined to be less than a predetermined threshold, then the pixel output data are determined to be non-decodeable.
To reduce processing time, the processing circuits 212 evaluate or analyze the pixel signals corresponding to the first row of pixels 204 to determine if these pixel signals include decodeable pixel output data using at least one or more of the factors described above for the first embodiment. If they do, the pixel output data corresponding to the first row of pixels 204 are transmitted to a pixel processor 214. The pixel processor 214 then determines whether the pixel output data corresponding to the first row of pixels 204 corresponds to a one-dimensional barcode. If it does, the pixel output data are transmitted to the decoder 318 where the pixel output data corresponding to the first row of pixels 204 are decoded.
If the pixel output data corresponding to the first row of pixels 204 do not correspond to a one-dimensional barcode, i.e., the pixel output data corresponds to a two-dimensional barcode, the pixel output data are stored in a memory of the decoder 318 while awaiting for subsequent pixel output data, in order for all the pixel output data corresponding to the two-dimensional barcode to be transmitted to the decoder 318 substantially simultaneously.
If it is determined by the processing circuits 212 that the pixel signals corresponding to the first row of pixels 204 does not include decodeable pixel output data, the processing circuits 212 evaluate or analyze the pixel signals corresponding to the second row of pixels 206 to determine if these pixel signals include decodeable pixel output data using at least one or more of the factors described above for the first embodiment. If they do, the pixel output data corresponding to the second row of pixels 206 are transmitted to a pixel processor 214. The pixel processor 214 then determines whether the pixel output data corresponding to the second row of pixels 206 corresponds to a one-dimensional barcode. If it does, the pixel output data are transmitted to the decoder 318 where the pixel output data corresponding to the second row of pixels 206 are decoded.
If the pixel output data corresponding to the second row of pixels 206 do not correspond to a one-dimensional barcode, i.e., the pixel output data corresponds to a two-dimensional barcode, the pixel output data, as described above for the first row of pixels 204, are stored in a memory of the pixel processor 214 while awaiting for subsequent pixel output data, in order for all the pixel output data corresponding to the two-dimensional barcode to be transmitted to the decoder 318. The above methodology will be repeated for the third and any other subsequent rows.
If it is determined that the pixel output data corresponding to the first row of pixels 204, the pixel output data corresponding to the second row of pixels 206 and the pixel output data corresponding to the third row of pixels 207 are non-decodeable, the processing circuits 212 and/or pixel processor 214 then determines to combine or add (sum) the pixel signals corresponding to the first row of pixels 204, the second row of pixels 206, the third rows of pixels 207 or any combination thereof to increase the aspect ratio of the imaging pixel array 202. The combination of the pixel signals occurs by switching circuitry 216 associate with each pixel to combine or add (i.e., sum) the pixel signals of each pixel to increase the aspect ratio of the imaging pixel array 202. Alternatively, if a more powerful decoder 318 is employed in the system 200, the pixel processor 214 could be commanded to enter a slave mode where the decoder 318 would then decide how to best combine pixels.
As shown in
By employing switching circuitry 216 to select any arbitrary pixel combination, the imaging pixel array may be configured “on-the-fly” in various ways depending on the target being scanned or application. Referring to
The combination of the pixel signals of each pixel column 210 results in the output of a composite output signal having data corresponding to the imaged barcode or other indicia and also having improved signal-to-noise (S/N) characteristics. Hence, the imaging pixel array 202 is programmable, since the aspect ratio of the imaging pixel array 202 can be altered “on-the-fly” to optimize aspect ratio, thereby increasing the signal-to-noise (S/N) ratio in the composite output signal transmitted to the pixel processor 214 and subsequently to the decoder 318.
The pixel processor 214 determines whether the composite output signal corresponds to a one-dimensional barcode (for example, by analyzing finder patterns, edges, etc. of the barcode). If it does, the composite output signal is transmitted to the decoder 318 where the data of the composite output signal which corresponds to the imaged barcode are decoded.
If the composite output signal does not correspond to a one-dimensional barcode, i.e., the data of the composite output signal corresponds to a two-dimensional barcode, the data are stored in a memory of the pixel processor 214 while awaiting for subsequent data, in order for all the data corresponding to the two-dimensional barcode to be transmitted to the decoder 318. The subsequent data are obtained by moving the barcode or barcode imager 302 relative to each other to image the remaining non-imaged portion of the barcode. The same methodology as described above is then repeated, i.e., the pixel signals of each pixel column 210 or individual pixel 208 are combined to increase the aspect ratio of the imaging pixel array 202 resulting in a composite output signal which is then transmitted to the pixel processor 214. It is contemplated that the processing circuits 212 can be integrated within the pixel processor 214 as a single, integrated chip.
Barcode Imaging System
The imaging circuitries 100, 200 of the first and second embodiments described above can be incorporated in a variety of imaging devices. One such imaging device is an image-based, one-dimensional barcode imaging system as shown by
As shown by
The control circuitry 308 includes a processor 314 for controlling the operation of the barcode imager 302, such as for actuating an image and decode process upon a user pressing a trigger button 316, actuating an actuator (not shown) for moving at least one lens element for focusing the optical code or target, controlling the illumination source 306, the aiming source 305 and communication circuitry 310, for operating the barcode imager 302 in the continuous imaging mode, and for executing a set of programmable instructions for decoding the imaged optical code or target or controlling operation of the decoder 318 for decoding the imaged optical code or target. The decoder 318 can be external to the processor 314 or resident within the processor 314.
The control circuitry 308 further includes a memory 315 for storing pixel output data and other data as described above with reference to the two embodiments and operational instructions, such as the sets of programmable instructions for operating the barcode imager 302 in the continuous imaging mode, capable of being executed by the processor 314. The memory 315 can be external to the processor 314 as shown in
The communication circuitry 310 outputs data indicative of the decoded and/or processed optical code or target to an external computing device, such as terminal 313, and receives data, such as data for changing at least one operational parameter of the barcode imager 302 as known in the art. The operational parameters can also be changed by imaging an optical code or target corresponding to at least one operational parameter and decoding and/or processing the imaged optical code or target, and subsequently changing the at least one operational parameter indicative of the decoded and/or processed optical code or target.
Alternatively, various components of the imaging system may be implemented in a single semiconductor device, e.g., a scanner-on-a-chip. Referring to
The described embodiments of the present disclosure are intended to be illustrative rather than restrictive, and are not intended to represent every embodiment of the present disclosure. Various modifications and variations can be made without departing from the spirit or scope of the disclosure as set forth in the following claims both literally and in equivalents recognized in law.