Patent Application
20060066346
Interface circuits are used to transmit and receive electrical signals between devices in electronic systems. These systems include digital systems where the signals communicated between the devices transition between high and low voltage levels. In some of these systems electrical signals need to be transmitted between integrated circuits (ICs). Interface circuits are used to minimize the effects of signal reflections on transmission lines interconnecting the integrated circuits.
Signal reflections occur from mismatches between signal source impedances and signal destination impedances. Because the signals transition between high and low voltage levels and because the transmission lines are lossy, the reflected signals eventually die out and a steady state is achieved on the signal transmission line. However, waiting for the signal to reach steady state results in delays in reading the signal on the transmission line. These delays eventually became unacceptable as switching speeds of integrated circuit continue increased.
To minimize reflections, designers of electrical systems try to match the source and destination as closely as possible. This matching is typically addressed in the design of input/output (I/O) buffer circuits in the integrated circuits. However, variances in impedances due to fabrication processes, voltages used, and temperatures to which the integrated circuits are exposed make this process difficult. The variances also make it difficult to create designs that are portable among applications.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be used and structural and logical changes may be made without departing from the scope of the present invention.
This document describes systems and methods to improve the process of impedance matching of integrated circuits.
However, it is difficult to know precisely when the reflection hits a receiver due to variances in the system such as transmission line length. This makes it difficult to know when to read the signal on the transmission line in order to adjust the impedance during an impedance tuning process. Taking a conservative approach that waits for a steady state in the transmission lines leads to dead time in the impedance switching. This lengthens the tuning process and adds cost to developing and implementing the design.
Additionally, adjusting an impedance during the tuning process can result in impedance glitches that add reflections to the system and compound the problem. For example, as the impedance is tuned by advancing a binary code in the registers, a code value change may result in rollover of several bits in the register, such as “0111” to “1000” for example. Due to the relative change in bit switching times, a rollover of several bits in the register will cause a glitch in the impedance of the I/O Buffers. A glitch that causes a full signal reflection on the transmission line causes errors in the impedance tuning process. Thus, it is important to minimize glitches while tuning the impedance.
The circuit 100 in
Outputs of counter 115 are coupled to inputs of the adjustable impedance circuit 125. The counter 115 counts according to a weighted code pattern that includes a pseudo-thermometer code. As the counter 115 counts, the counter outputs change according to the pattern. Because the outputs of the counter 115 are coupled to the inputs of the adjustable impedance circuit 125, the impedance changes according to the weighted code pattern as the outputs change.
The voltage divider divides a first reference 130 (VREF1) to produce a voltage at a first node 140 that is coupled to an input of the comparison circuit 110. In some embodiments, the first reference 130 is the difference between a supply voltage VCC and ground. The other input of the comparison circuit 110 is coupled to a second voltage reference 145 (VREF2). The output of the comparison circuit 110 is connected to an input of the counter 115. Based on the comparison of the inputs of the comparison circuit 110, a signal from the output of the comparison circuit 110 causes the counter 115 to count.
In one embodiment, when the voltage at the first node 140 is less than VREF2, a signal is output to cause the counter 115 to decrement. The decrease in the count causes the adjustable impedance to increase which raises the voltage at the first node 140. When the voltage at the first node 140 is greater than VREF2, a signal is output to cause the counter 115 to increment. The increase in the count causes the adjustable impedance to decrease which lowers the voltage at the first node 140. In an alternative embodiment, an increase in the count causes the impedance to increase and a decrease in the count causes the impedance to decrease. The comparison circuit 110 causes the output to change until the count reaches a steady state and an impedance value is obtained. In one embodiment, the steady state is reached when the output of the comparison circuit 110 oscillates or “dithers” between a signal to increment the count and a signal to decrement the count. For example, if a low or “0” output signal causes the counter 115 to increment, and a high or “1” causes the counter 115 to decrement, a steady state is reached when the output signal changes as 010101, . . . and so on. When a steady state is reached, the voltage at the first node 140 matches the voltage of VREF2. In one embodiment, VREF2 is chosen to be one-half the value of VREF1 and the adjustable impedance matches the reference impedance when the voltage at the first node 140 matches the voltage of VREF2. Different values of impedance in relation to the reference voltage can be found by changing the value of VREF2 in relation to VREF1.
Because the counter counts according to a pseudo-thermometer code, the counter does not roll over a large number of count bits that would normally cause a glitch in the impedance. Table 1 shows an embodiment of a pseudo-thermometer code.
In the embodiment, seven bits are used to encode eleven states. The outputs of the counter 115 are connected to the adjustable impedance circuit 125 according to the code weight. Thus a code weight output of 1× is connected to an input such that an active level on that output changes the adjustable impedance by 1× of a unit impedance. Similarly, a change in a 2× code weight changes the adjustable impedance by 2× of the unit impedance. The code is a pseudo-thermometer code because some of the code bits have a weight of 2× rather than all weights of 1× as in a pure thermometer code. Note that at most two bits change levels between any two successive states and the change in weight between any two states is 1×.
In some embodiments, the counter 115 includes a pseudo-thermometer code combined with a binary code. Table 2 shows a binary coding scheme using five bits. The Tables show that a combination of the binary coding scheme and pseudo-thermometer coding scheme produces forty-one states from twelve bits. In some of the embodiments, the counter 115 includes logic to enable only the binary code portion to count until a first steady state is reached and to enable only the pseudo-thermometer code portion to count until a second steady state is reached. A steady state is reached when the output of the comparison circuit 110 dithers between a signal to increment the count and decrement the count.
In the embodiments, only the binary portion is first allowed to count while holding the pseudo-thermometer portion frozen until dithering occurs. Then, only the pseudo-thermometer portion is allowed to count while holding the binary portion frozen until dithering occurs. Thus, a coarse adjustment is provided by the binary code and a fine adjustment is provided by the pseudo-thermometer code.
In some embodiments the circuit 100 is included in an integrated circuit die and the reference impedance is external to the integrated circuit die. In one embodiment, the reference impedance is a precision resistor coupled to a die pad. In this way, the impedance on the integrated circuit can be tuned to an impedance external to the integrated circuit, such as an external impedance due to a printed circuit board, a coaxial connection, or combinations of external impedances.
One or a combination of the transistor inputs are coupled to outputs of the counter 215 so that the transistors realize weighted multiples of a unit impedance value that correspond to the weights of the outputs. The multiples can be formed from connecting together multiples of a unit-sized transistor or creating different transistors sizes that have width to length ratios that are multiples of a unit-sized width to length ratio. The adjustable impedance circuit 225 includes transistor resistances of 1× and 2× attached to the portion of the counter 215 that counts according to a pseudo-thermometer code, and transistor impedances of 1× through NX attached to the portion of the counter 215 that counts according to a binary code; N being a binary integer.
In the embodiment shown, the adjustable impedance circuit 225 includes a network of PMOS transistors 255 and a network of NMOS transistors 260. The circuit also includes enable/disable logic to disable the PMOS network, the NMOS network, or both. By disabling one or the other network, the circuit 200 is able to tune the networks separately. When the PMOS network is being tuned, the voltage difference between VCC and VCC/2 is divided between the PMOS network and the reference resistance circuit 220 to produce a voltage at a first node 240 that is coupled to one input of the comparison circuit 210. The other input of the comparison circuit 210 is coupled to a first reference 245 (VREF). When the count increases, more transistor inputs become active and the PMOS impedance decreases. When the NMOS network is being tuned, the voltage difference between VCC/2 and ground is divided between the NMOS network and the reference resistance circuit 220 to produce a voltage at the output node 240. When the count increases, the NMOS impedance decreases.
In another embodiment, a second reference is coupled to the comparison circuit 210. A comparison is made between the first reference 245 and the output node 240 to obtain a count, or impedance code value, for the PMOS network, and a comparison is made between the second reference and the output node 240 to obtain an impedance code value for the NMOS network. Only one network is active at a time when tuning the impedance. Enabling both networks causes indeterminate results.
The impedance measurement circuit includes a voltage divider 305, a comparison circuit 310, and a counter 315. The voltage divider 305 divides a first reference 330 (VREF1) to produce a voltage on an output node 340. The voltage divider includes a reference impedance circuit 320 coupled to an adjustable impedance circuit 325 at the output node 340. The adjustable impedance circuit 325 includes inputs to adjust the impedance according to a weighted coding scheme. Outputs of the counter 315 are coupled to inputs of the adjustable impedance circuit 325. The counter 315 counts according to a weighted code pattern that includes a pseudo-thermometer code. Because the outputs of the counter 315 are coupled to the inputs of the adjustable impedance circuit 325, the adjustable impedance changes according to the weighted code pattern as the counter 315 counts.
The voltage divider 305 produces a voltage at the output node 340 that is coupled to an input of the comparison circuit 310. The other input of the comparison circuit 310 is coupled to a second voltage reference 345 (VREF2). The output of the comparison circuit 310 is connected to an input of the counter 315. Based on the comparison of the inputs of the comparison circuit 310, a signal from the output of the comparison circuit 310 causes the counter 315 to count.
In one embodiment, when the voltage at the output node 340 is less than VREF2, a signal is output from the comparison circuit 310 to cause the counter 315 to increment. The increase in the count causes the adjustable impedance to decrease which raises the voltage at the output node 340. When the voltage at the output node 340 is greater than VREF2, a signal is output to cause the counter 315 to decrement. The decrease in the count causes the adjustable impedance to increase which lowers the voltage at the output node 340. In another embodiment, the positions of the reference impedance circuit 325 and the adjustable impedance circuit 320 are interchanged and the impedance is adjusted similar to the embodiment in
The I/O buffer circuit 302 includes a storage circuit 350 coupled to an adjustable impedance circuit 355. The storage circuit 350 stores the impedance code value obtained when the counter 315 reaches a steady state. The I/O buffer adjustable impedance circuit 355 includes inputs to adjust the impedance according to a weighted coding scheme. Thus, the value stored in the storage circuit 350 sets the impedance of the adjustable impedance circuit 355 according to the value of the impedance code.
In some embodiments, the I/O buffer adjustable impedance circuit 355 is the same as the adjustable impedance circuit 325 of the impedance measurement circuit. In some of the embodiments, storing the impedance code value in the storage circuit 350 sets the I/O buffer 302 impedance equal to the measured steady state impedance value. If the adjustable impedance was tuned to the reference impedance, the I/O buffer impedance is set equal to the reference impedance. If the reference impedance is representative of an impedance of a signal source or destination, the I/O buffer circuit 302 impedance is matched to the impedance and signal reflections are minimized.
In other embodiments, the system further includes an update circuit coupled between the counter 315 and the storage circuit 350. The update circuit includes logic to scale the impedance code value by a multiple, to add an offset to the impedance code value, or both to obtain an updated impedance code value. The term “logic” includes any logic circuits used to implement the scaling or multiplying and providing an offset to the impedance code value. In some of these embodiments, the system 300 includes groups of at least one I/O buffer circuit 302. The buffers can be grouped according to values of external impedance at the buffer interfaces, or by function of the I/O signals. Each group of I/O buffers includes a storage circuit 350. Either the impedance code value or an updated impedance code value can be stored in the storage circuits 350 to set the impedance of each group of buffers. In one embodiment, one I/O buffer circuit 302 is dedicated for use as the adjustable impedance circuit 325 for impedance tuning.
Once an impedance code value is obtained for one group of I/O buffers, previous circuit simulation has shown what impedance can be expected for the other groups of buffers. The update circuit then provides an updated impedance code value appropriate for the other groups of buffers. For example, assume the I/O buffer circuits 302 are on an integrated circuit (IC) that interfaces to other ICs. It is known that all clock I/O buffers drive two ICs and all data I/O buffers drive one IC. Also assume that the reference impedance circuit 320 represents the impedance seen at the data I/O buffers, and simulation has shown that the impedance seen at the clock I/O buffers is twice that of the data I/O buffers. Once the impedance code value for the data I/O buffers is obtained from the impedance measurement circuit, the update circuit scales the impedance code value by two before the impedance code value is stored in the storage circuit 350 for the clock I/O buffers. In some embodiments, the system further includes a memory circuit, and the value used by the update circuit to scale the impedance code value, to offset the impedance code value, or both is stored in a look-up table in the memory circuit. In some of the embodiments, the memory circuit includes a static random access memory (SRAM).
In some embodiments, the adjustable impedance circuits 325, 355 include a plurality of transistors. For the adjustable impedance circuit 325 of the impedance measurement circuit, the transistors are connectable to apply multiples of a unit impedance value to the output node 340. The inputs of the transistors are coupled to the outputs of the counter 315. An active state from a counter output provided at the input of a transistor applies the transistor impedance to the first node 340 to adjust the division ratio of the voltage divider 305. In some embodiments, the plurality of transistors includes a PMOS transistor network and an NMOS transistor network. An enable/disable input to the networks causes only the PMOS network or only the NMOS network to be active at the first node 340. By disabling one or the other network, the system 300 is able to tune the networks separately to obtain a PMOS impedance code value and an NMOS impedance code value.
For the I/O buffer adjustable impedance circuit 355, the transistors are included in the interface drive circuit of the buffers. In some embodiments, the PMOS and NMOS transistors are the I/O buffer pull-up and pull-down drivers respectively. The impedance code value or values written into the storage circuit 350 determine how many transistors are added to the pull-up and the pull-down circuits.
According to some embodiments, the I/O buffer circuit 302 further includes a slew rate control circuit. The slew rate is determined from a slew rate value provided to the slew rate control circuit. Previous circuit simulation is used to determine what slew rate value corresponds to an impedance code value. In some the embodiments, the system 300 includes a memory circuit for storing a slew rate look-up table and the values for the slew rates corresponding to the impedance code values are stored in the look-up table.
In some embodiments, the I/O buffer circuit 302 is included in an integrated circuit die and the reference impedance circuit 320 is external to the integrated circuit die. In some of the embodiments, the integrated circuit die is to be mounted on a printed circuit board and the reference impedance corresponds to a printed circuit board (PCB) impedance. In other embodiments, the reference impedance is a combination of impedances. For example the reference impedance may represent a lumped impedance of a PCB impedance with a coaxial transmission line impedance. In some embodiments, the integrated circuit die includes a processor. In some embodiments, the integrated circuit die is included in a network controller.
In some embodiments, the transistors include a network of PMOS transistors and a network of NMOS transistors. In the embodiments, dividing the first reference voltage includes first dividing the reference voltage between the reference impedance and a PMOS transistor network. The adjustable impedance is changed to obtain a PMOS impedance code value for the PMOS transistor network. The first reference voltage is then divided between the reference impedance circuit and an NMOS transistor network. The adjustable impedance is changed to obtain an NMOS impedance code value for the NMOS transistor network. Compensating at least one I/O buffer includes using the impedance code values to compensate pull-up and pull-down circuits for the at least one I/O buffer. The impedances of the pull-up and pull-down circuit are set relative to the reference impedance. In some of the embodiments, this includes scaling the impedance code value, adding an offset to the code value, or both to set the relative impedance.
In some embodiments, changing the adjustable impedance includes selectively activating transistors according to a coarse impedance adjustment weighted according to a binary code and a fine impedance adjustment weighted according to a pseudo-thermometer code. In some of the embodiments, changing the adjustable impedance value includes changing only the binary code portion until a first steady state is reached and changing only the pseudo-thermometer code portion until a second steady state is reached. A steady state is reached when the voltage across the adjustable impedance is sufficiently close to the second reference voltage so that no meaningful changes occur in the weighted code as the impedance is adjusted.
In some method embodiments, compensating the at least one I/O buffer includes compensating a plurality of I/O buffers using the impedance code value to set the impedance of the I/O buffers. In some of the embodiments, compensating includes compensating groups of at least one I/O buffer by using the code value to obtain a group code value, if necessary, by scaling the code value, or by adding an offset to the code value, or both. Setting an impedance of a group of I/O buffers includes using either the impedance code value or the group impedance code value.
In some embodiments, the method further includes setting a slew rate of the at least one I/O buffer using the impedance code value. In some of the embodiments, setting a slew rate includes looking up a slew rate value in a look up table using the code value.
The accompanying drawings that form a part hereof, show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
Such embodiments of the inventive subject matter may be referred to herein, individually, collectively, or both by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.
The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own.
