Patent Application
20210404078
The present disclosure is directed to health and performance monitoring and control for an electrochemical system, such as a proton exchange membrane (PEM) stack system using alternating current impedance spectroscopy derived signals.
Electrical circuits in which a cell is either a power source or a load are problematic in that chemical degradation effects can take place for which the only observable symptom or measurement is a degradation in the potential or impedance of the cell. This is problematic for systems implemented in field where the degrading condition is occurring and the only measurement is voltage because there is no way to differentiate between possible failure modes that can cause the degradation and to remedy the degrading condition before the degrading condition becomes permanent or chronic. Alternating current impedance spectroscopy can be used in a laboratory setting to analyze different frequency responses of cells to determine different failure modes. However, for applications in the field, laboratory equipment may not be used because it is not hardened and the resultant ripple from a laboratory signal generator if it were used at a kilowatt or even megawatt scale would be so impactful to use case customers that it would not be permitted.
According to one embodiment, an alternating current (AC) impedance spectroscopy method includes providing an AC impedance spectroscopy ripple from power electronics into an electrochemical device, and absorbing the ripple in the power electronics.
According to another embodiment, an alternating current (AC) impedance spectroscopy system includes a power factor corrected (PFC) rectifier electrically connectable to an AC power source via an AC split bus and to a direct current DC/DC converter via a DC bus. The PFC rectifier includes a plurality of electric power inverters electrically connectable to respective AC busses of the AC split bus, a first capacitor and a second capacitor electrically connected in parallel to the plurality of electric power inverters via a middle DC bus at a DC-link midpoint; and an auxiliary electric power converter electrically connected to the DC-link midpoint via the middle DC bus and electrically connectable to the direct current (DC)/DC converter via the DC bus.
Like reference symbols in the various drawings indicate like elements.
The embodiments will now be described more fully hereinafter with reference to the accompanying figures, in which exemplary embodiments are shown. The foregoing may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. All fluid flows may flow through conduits (e.g., pipes and/or manifolds) unless specified otherwise.
All documents mentioned herein are hereby incorporated by reference in their entirety. References to items in the singular should be understood to include items in the plural, and vice versa, unless explicitly stated otherwise or clear from the text. Grammatical conjunctions are intended to express any and all disjunctive and conjunctive combinations of conjoined clauses, sentences, words, and the like, unless otherwise stated or clear from the context. Thus, the term “or” should generally be understood to mean “and/or,” and the term “and” should generally be understood to mean “and/or.”
Recitation of ranges of values herein are not intended to be limiting, referring instead individually to any and all values falling within the range, unless otherwise indicated herein, and each separate value within such a range is incorporated into the specification as if it were individually recited herein. The words “about,” “approximately,” or the like, when accompanying a numerical value, are to be construed as including any deviation as would be appreciated by one of ordinary skill in the art to operate satisfactorily for an intended purpose. Ranges of values and/or numeric values are provided herein as examples only, and do not constitute a limitation on the scope of the described embodiments. The use of any and all examples or exemplary language (“e.g.,” “such as,” or the like) is intended merely to better illuminate the embodiments and does not pose a limitation on the scope of those embodiments. No language in the specification should be construed as indicating any unclaimed element as essential to the practice of the disclosed embodiments.
The embodiments described herein reference a “cell” as an electric power source and/or an electric load of an electrochemical system, such as a proton exchange membrane (PEM) fuel cell generator, PEM electrolyzer, other PEM unit, and/or other electrochemical system, which may include cells, such as electrochemical cells (e.g., batteries, flow batteries, fuel cells, electrolyzer cells, hydrogen pumping cells, oxygen pumping cells), photovoltaic cells, motors, generators, and other semiconductor junction based cells. In some embodiments, a cell as an electric power source may include electrical or electrochemical ammonia synthesis cells, electrical or electrochemical metal-organic framework cell (MOF-cell) water condenser, electrical or electrochemical oxygen, nitrogen, or air purifiers, electrical or electrochemical water polisher, such as an electrodialysis cell, etc. In some embodiments, a cell as an electric load may include a customer load, (e.g., an electrical system of a building, a facility, an environment conditioning system, a machine, a computer network, etc.), a hydrogen pumping cell, and oxygen generating cell, a MOF-cell, etc. Examples of such PEM electrolyzer cells are described in U.S. patent application Ser. No. 17/101,224, entitled “SYSTEMS AND METHODS OF AMMONIA SYNTHESIS” by Ballantine et al., U.S. patent application Ser. No. 17/101,232, entitled “ELECTROCHEMICAL DEVICES, MODULES, AND SYSTEMS FOR HYDROGEN GENERATION AND METHODS OF OPERATING THEREOF” by Ballantine et al., and U.S. Provisional Patent Application No. 63/057,406, entitled “MODULAR SYSTEM FOR HYDROGEN AND AMMONIA GENERATION WITHOUT DIRECT WATER INPUT FROM CENTRAL SOURCE” by Light et al. the entire contents of each of these references incorporated herein by reference.
Embodiments and examples herein may be described with reference to PEM based electrolyzer stacks (herein PEM stack) for clarity and ease of explanation, and do not limit the scope of the claims and descriptions to PEM stacks as one of skill in the art shall recognize that such embodiments may be similarly applicable to other cells.
Embodiments provide devices and methods of determining the health and points of control for an electrochemical system, such as a PEM stack based system, using alternating current (AC) impedance spectroscopy derived signals. Such devices and methods may be configured to monitor for leakage, errors, deterioration, and overall life quality of a PEM stack using a small AC ripple across a direct current (DC) power input into the PEM stack and reading the frequency of the resultant impedance wave. In some embodiments the AC ripple may sweep through set frequencies and gather data to analyze against predetermined errors and the system may be corrected to clear the error and/or the error may be reported to the owner/customer. The small ripple current should not be higher than the DC current magnitude and should not impact the PEM stack operation or life.
Existing circuit arrangements for AC impedance spectroscopy require the power flow to or from the electrochemical stack to be interrupted and impedance to be monitored by observing the voltage transient response. This method has the substantial disadvantage of requiring an interruption of the power flow. Further, the full breadth of frequency spectrum analysis is not possible with this method.
Existing circuit arrangements for AC impedance spectroscopy also include structures where multiple elements of power electronics are operated 180 degrees out of phase to cancel ripple on the power bus when ripple is applied to the electrochemical stack bus. This has the substantial disadvantage of requiring that multiple circuits be operated in order to create the canceling effect. A single stack circuit is not possible.
Embodiments herein provide power electronics hardware and power electronics control configured for in-situ AC impedance spectroscopy in which the ripple back to a power supply source may be cancelled. Such embodiments avoid the requirement of existing circuit arrangements for AC impedance spectroscopy for multiple segments of power electronics to be operating out of phase to cancel ripple currents.
Embodiments herein provide integration of in-situ AC impedance spectroscopy in an electrochemical system, such as a PEM fuel cell generator, PEM electrolyzer, other PEM unit or other electrochemical system, where the feature of AC impedance spectroscopy is used for system diagnostics and control.
The resulting ripple back to a power supply source may be canceled so that there is no resulting impact of harmonics to a load for the electrochemical system. In some embodiments, the ripple may be cancelled by ripple canceling power electronics hardware, as described further herein with reference to
A voltage on the electrolyzer stack or groups of cells may monitored by electronics in the power supply module and/or in the electrolyzer module. A phasor impedance of the electrolyzer stack at the ripple frequency may be determined by comparing a driving current ripple signal with an induced voltage ripple. Multiple impedances at different frequencies may be determined by changing the driving current ripple frequency. In some embodiments, the driving current ripple may be swept through frequencies in a stepwise fashion. In some embodiments, the driving current ripple may be selected frequencies used individually or in small sets to obtain specific impedance data at specific frequencies.
Based on the impedance data, controls may be executed in order to improve the performance and lifetime of the electrolyzer module. The power electronics hardware and power electronics controls described herein may be integrated in tandem with system level controls for diagnostics or function control of the electrochemical system.
The PFC rectifier 102 may include various components configured for electric power conditioning and for AC impedance spectroscopy. The various components may include any number of electric power inverters 106, which may be electrically connectable to the AC power source 120, such as each of the electric power inverters 106 may be electrically connectable to the AC bus of the split AC bus 121 and at least one respective inductor 122. The PFC rectifier 102 may be electrically connected to the DC/DC converter 104. For example, the electric power inverters 106 may include at least two diodes, such as a first diode 118a and a second diode 118b, and the respective bus of the AC split bus 121 may be electrically connectable between an anode end of the first diode 118a and a cathode end of the second diode 118b. The cathode end of the first diode 118a may be electrically connected to a DC bus 123a and the anode end of the second diode 118b may be electrically connected to a return DC bus 123b. In some embodiments, the DC bus 123a and the return DC bus 123b may have opposite polarities.
In some embodiments, a half-bridge inverter 112 may be incorporated into each of the electric power inverters 106. A first end of the half-bridge inverter 112 may be electrically connected between the anode end of the first diode 118a and the cathode end of the second diode 118b. As such, in some embodiments, the first end of the half-bridge inverter 112 may be electrically connectable to the respective bus of the AC split bus 121 connected between the anode end of the first diode 118a and the cathode end of the second diode 118b. The half-bridge inverter 112 may be electrically connected to a middle DC bus 123c. In some embodiments, the middle DC bus 123c may be a neutral bus. In some embodiments, the half-bridge inverter 112 may include opposingly oriented pairs of paralleled diodes 114a, 114b and transistors 116a, 116b, such as insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). The pairs of paralleled diodes 114a, 114b and transistors 116a, 116b may include a cathode end of a diode 114a, 114b electrically connected to a collector end of a transistor 116a, 116b, and an anode end of the diode 114a, 114b electrically connected to an emitter end of the transistor 116a, 116b. The cathode end of a first diode 114a and the collector end of a first transistor 116a may be electrically connected in parallel between the anode end of the first diode 118a and the cathode end of the second diode 118b. The anode ends of the diodes 114a, 114b and the emitter ends of the transistors 116a, 116b may be electrically connected in parallel to a bus (e.g., bus 122). The transistors 116a, 116b may each include a gate end electrically connected in parallel to a bus. The cathode end of a second diode 114b and the collector end of a second transistor 116b may be electrically connected in parallel to the middle DC bus 123c.
The PFC rectifier 102 may include at least two capacitors, such as a first capacitor 108a and a second capacitor 108b, electrically connected in parallel to the middle DC bus 123c. The first capacitor 108a may be electrically connected to the middle DC bus 123c at a cathode end and electrically connected to the DC bus 123a at an anode end. The second capacitor 108b may be electrically connected to the middle DC bus 123c at an anode end and electrically connected to the return DC bus 123b at a cathode end. The capacitors 108a, 108b may be electrically connected in parallel to the electric power inverters 106 and/or the half-bridge inverters 112 via the middle DC bus 123c. In some embodiments, the capacitors 108a, 108b may be configured to approximately equally divide the DC voltage between the electric power inverters 106 and an auxiliary electric power converter 110 of the PFC rectifier 102. A connection of the capacitors 108a, 108b to the middle DC bus 123c may be a midpoint (“0”) for a DC-link of the PFC rectifier 102.
The auxiliary electric power converter 110 may include at least two additional capacitors, such as a first capacitor 124a and a second capacitor 124b, electrically connected in parallel to the middle DC bus 123c. The first capacitor 124a may be electrically connected to the DC bus 123a at a first end and electrically connected to the middle DC bus 123c at a second end. The second capacitor 124b may be electrically connected to the middle DC bus 123c at a first end and electrically connected to the return DC bus 123b at a second end. The capacitors 124a, 124b may be electrically connected in parallel to a filter inductor 126. The filter inductor 126 may be electrically connected to the middle DC bus 123c at a first end and to a second half-bridge inverter at a second end. The second half-bridge inverter has pairs of paralleled transistors 128a, 128b, such as insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes 130a, 130b. The pairs of paralleled transistors 128a, 128b and diodes 130a, 130b may include a collector end of a transistor 128a, 128b electrically connected to a cathode end of a diode 130a, 130b, and an emitter end of the transistor 128a, 128b electrically connected to an anode end of the diode 130a, 130b. The collector end of a first transistor 128a and the cathode end of a first diode 130a may be electrically connected in parallel to the DC bus 123a. The emitter end of the first transistor 128a and the anode end of the first diode 130a may be electrically connected in parallel to the second end of the filter inductor 126. The collector end of a second transistor 128b and the cathode end of a second diode 130b may be electrically connected in parallel to the second end of the filter inductor 126. The emitter end of the second transistor 128b and the anode end of a second diode 130b may be electrically connected in parallel to the return DC bus 123b.
A DC/DC converter 104 may be electrically connected between the DC bus 123a and the return DC bus 123b. The DC/DC converter 104 may be electrically connectable to any number and combination of other components (not shown) of the power electronics hardware 100a, 100b, such as a cell as an electric power source, and/or a cell as an electric load (not shown).
In some embodiments, a DC-link midpoint (“O”) of the PFC rectifier 102 may exist at a connection of the capacitors 108a, 108b and the middle DC bus 123c. Depending on the state of charge of the capacitors 108a, 108b, the DC-link midpoint's availability may vary. When the DC-link midpoint is not accessible, as shown in
The auxiliary electric power converter 110 may be switched, for example, through control of the transistors 130a, 130b in such a way that the auxiliary electric power converter 110 may draw only reactive power from the DC-link, with a specified magnitude and phase angle. The current drawn by the auxiliary electric power converter 110 from the DC-link may be controlled to compensate for a ripple current drawn by the DC/DC converter 104, from the DC-link of the PFC rectifier 102. In some embodiments control of the transistors 128a, 128b and the diodes 130a, 130b may be implemented using any number and combination of controllers (not shown).
In some embodiments, the control of the power electronics hardware 200 configured for AC impedance spectroscopy may be implemented by any number and combination of controllers (not shown). For example, a controller may receive signals from the AC power source 120 (“A”), signals from the inductors 122 (“B”), and signals from the capacitors 108a, 108b (“C” and “D”). The signals (A-D) may be representative of voltage and/or current levels at each of the AC power source 120, the inductors 122, and the capacitors 108a, 108b. The controller may use the signals (A-D) to implement control of the power electronics hardware 200 configured for AC impedance spectroscopy, as illustrated, for example, in
In the PFC rectifier 202, current loops may operate at high (e.g., several kHz) bandwidth to track current reference commands effectively. Typically, a DC bus voltage control loop would have a lower bandwidth to maintain sinusoidal grid currents, for example at the AC power source 120 (“A”) and/or at the inductors 122 (“B”), by providing appropriate current reference command (e.g., “SA”, “SB”, “SC”). In other words, the DC bus voltage loop bandwidth will be lower when compared to the current loop. The higher and lower bandwidths are relative and depend on the power rating of the underlying equipment.
A ripple voltage on the DC-link of the PFC rectifier 202, due to the converter perturbation for AC impedance spectroscopy at the DC/DC converter 104, may appear at an input error signal of a voltage controller. When the voltage controller error input contains low frequency signals (e.g., signals whose frequency is close to the voltage loop bandwidth or higher, especially around the voltage loop bandwidth), a ripple portion in the error signal may reach an output of the voltage controller. This adds undesirable frequency components to the current reference command. A current controller may ensure proper tracking of the reference command, which may result in injection of a lower frequency signal (related to the frequency perturbation injected by the DC/DC converter 104) into an electric power grid, such as AC power source 120.
To mitigate injection of the low frequency components to the grid, a controller may estimate or find a DC-link ripple voltage based on the known electrical quantities and injected perturbation for the AC impedance spectroscopy, or the controller may track the ripple voltage on the DC-link. The controller may remove the ripple component from a sensed DC-link voltage signal or error input to the controller, such as a DC-link voltage controller. This may prevent propagation of a perturbed voltage ripple in the DC-link from reaching the controller, such as the current controller, and effectively prevent the injection of the low frequency components into the grid.
The controller may implement a number of operations to remove the ripple component from a sensed DC-link voltage signal or error. For example, the controller may receive signals from the AC power source 120 (“A”), signals from the inductors 122 (“B”), and signals from the capacitors 108a, 108b (“C” and “D”). These signals (A-D) may be voltage signals at the respective components. The controller may sum 212a, 212h the signals (C and D), for example to generate a total voltage and a voltage difference of the signals (C and D). The controller may also receive three phase signals (A and B) and convert 218a, 218b three phase signals to voltage and current components in a two-axis reference frame (e.g., d-q). A hardware zero-crossing or digital phase-locked loop operation 224 may determine an angular frequency for converting 218a, 218b three phase signals to voltage and current components. A voltage sensor-less control also can be used for determining the grid phase angle or angular frequency.
The total voltage may be further summed 212b with a reactive voltage component to generate a real voltage component. The real voltage component may be summed 212c with a reference real voltage component to generate a voltage difference of the real voltage, which may be converted 214a (e.g., by a proportional and integral (“PI”) operation) to generate a corresponding reference current.
Reference currents in the two-axis reference frame may be summed 212d, 212f with the current components in the two-axis reference frame converted from the three phase signal (B) to generate a current differences, of which differentials 214b, 214c (e.g., by a PI operation) may be generated. In some embodiments, a reactive power reference current, summed 212f with a reactive power current, may equal zero. The differentials may be summed 212e, 212g with portions of the voltage components in the two-axis reference frame converted from the three phase signal (A) to generate values in the two-axis reference frame. The voltage difference of the signals (C and D) may be summed 212i with a zero value, from the result of which a value may be generated 214d (e.g., by a PI operation) in a third axis reference. The resultant values may be converted 216 to values in a three-axis reference frame of the received signals (A and B). The values in the three-axis reference frame may be augmented 220a, 220b, 220c by a reference voltage and converted 222 (e.g., by an enhanced pulse width modulation (“ePWM”) operation) to generate current reference commands (e.g., “SA”, “SB”, “SC”) that may be provided to the PFC rectifier 202.
In some embodiments in which an AC power source is a cell such as an electrochemical cell, or generator, and power electronics pass this power to a load, and in which the power electronics impart a perturbation, ripple, or sinusoid in sourced current on the cell, device, electrochemical cell or generator such that by monitoring the voltage of the cell or generator, the impedance of that item at the frequency of the perturbation, ripple, or sinusoid may be determined. Further, the power electronics may be configured to cause direct cancelation of the perturbation, ripple, or sinusoid such that it does not pass downstream into a feed to power to a load.
The electric power inverters 106 may include at least two pairs of paralleled transistors 308a, 308b, such as insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes 310a, 310b, instead of the diodes 118a and 118b of the first embodiment shown in
In some embodiments, a half-bridge inverter 302 may be incorporated into each of the electric power inverters 106. A first end of the half-bridge inverter 302 may be electrically connected between the emitter end of the first transistor 308a and the anode end of the first diode 310a, and the collector end of the second transistor 308b and the cathode end of the second diode 310b. As such, in some embodiments, the first end of the half-bridge inverter 302 may be electrically connectable to the respective bus of the AC split bus 122 which is electrically connected between the emitter end of the first transistor 308a and the anode end of the first diode 310a, and the collector end of the second transistor 308b and the cathode end of the second diode 310b. The second end of half-bridge inverter 302 may be electrically connected to the middle DC bus 123c. In some embodiments, the middle DC bus 123c may be a neutral bus. In some embodiments, the half-bridge inverter 302 may include pairs of paralleled transistors 306a, 306b, such as insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes 304a, 304b. The pairs of paralleled transistors 306a, 306b and diodes 304a, 304b may include a collector end of a transistor 306a, 306b electrically connected to a cathode end of a diode 304a, 304b, and an emitter end of the transistor 306a, 306b electrically connected to an anode end of the diode 304a, 304b. The collector end of a first transistor 306a and the cathode end of a first diode 304a may be electrically connected in parallel between the emitter end of the first transistor 308a and the anode end of the first diode 310a, and the collector end of the second transistor 308b and the cathode end of the second diode 310b. The emitter end of the first transistor 306a and the anode end of the first diode 304a may be electrically connected in parallel to a bus. The collector end of a second transistor 306b and the cathode end of a second diode 304b may be electrically connected in parallel to the bus. The emitter end of the second transistor 306b and the anode end of a second diode 304b may be electrically connected in parallel to the middle DC bus. The transistors 306a, 306b may each include a gate end electrically connected in parallel to a bus.
The capacitors 108a, 108b of the power electronics hardware 300a, 300b may be electrically connected in parallel to the middle DC bus 123c. The first capacitor 108a may be electrically connected to the middle DC bus 123c at the cathode end and the second capacitor 108b may be electrically connected to the middle DC bus 123c at the anode end. The capacitors 108a, 108b may be electrically connected in parallel to the electric power inverters 106 and/or the half-bridge inverters 302 via the middle DC bus 123c.
The active ripple mitigation in the power electronics hardware 300a, 300b for the electric power inverters 106 may be the same as that presented for the PFC rectifier 102 in
The digital control 210 of the ripple mitigation presented for the PFC rectifier 102 in
The power electronics hardware 500 may include a PFC rectifier 504 (e.g., PFC rectifier 102 in
In some embodiments, described with reference to
In some embodiments, the power electronics hardware 100a, 100b, 200, 300a, 300b, 400, and 500 may be unidirectional. In some embodiments, the power electronics hardware 100a, 100b, 200, 300a, 300b, 400, and 500 may be bidirectional.
In one embodiment, an alternating current (AC) impedance spectroscopy method comprises providing an AC impedance spectroscopy ripple from power electronics into an electrochemical device, and absorbing the ripple in the power electronics.
In one embodiment, the AC impedance spectroscopy ripple is provided from power electronics into the electrochemical device while an operating current or voltage is provided to or from the electrochemical device, such that the AC impedance spectroscopy ripple does interrupt the operation of the electrochemical device.
In one embodiment, the electrochemical device comprises an electrochemical stack, and impedance of different portions of the electrochemical stack is measured separately and compared to each other or to a reference or average impedance value. The method may also include determining a fault in a portion of the electrochemical stack, and electrically bypassing the portion of electrochemical stack containing the fault. The electrochemical stack may comprise a proton exchange membrane (PEM) electrolyzer stack.
In one embodiment, the power electronics comprise a plurality of electric power inverters electrically connectable to respective AC busses of the AC split bus, a first capacitor and a second capacitor electrically connected in parallel to the plurality of electric power inverters via a middle DC bus at a DC-link midpoint, and an auxiliary electric power converter electrically connected to the DC-link midpoint via the middle DC bus and electrically connectable to the direct current (DC)/DC converter via the DC bus. In one embodiment, the auxiliary electric power converter is configured to draw a reactive power amount from the DC-link to cancel the AC impedance spectroscopy ripple. In one embodiment, the method also includes measuring the AC impedance spectroscopy ripple voltage of the DC-link based on voltages at the first capacitor and the second capacitor, and injecting a canceling ripple to the DC-link configured to remove the ripple voltage from the DC-link.
With regard to
In block 602, the processing device may generate and output AC voltage at varying frequencies. The processing device may control various hardware components (e.g., transistors 116a, 116b in
In block 604, the processing device may measure impedance resulting from output of the AC voltage at varying frequencies. The processing device may take measurements of the resultant impedance of the AC voltages going through specified systems, such as a cell as a power source and/or a cell as a load. Measurements may be made by the processing device by monitoring voltages and currents at different locations of an AC impedance spectroscopy system (e.g., power electronics hardware 100a, 100b, 200, 300a, 300b, 400, and 500 in
In determination block 606, the processing device may determine whether a measurement of impedance exceeds a threshold for the AC voltage frequency. The processing device may access and retrieve threshold values of impedance for AC voltage frequencies from a memory, stored in association with each other, such as in a data structure or a database. The processing device may compare a measurement of impedance for the AC voltage frequency with the threshold values of impedance for AC voltage frequency to determine whether the measurement of impedance exceeds a threshold for the AC voltage frequency.
In response to determining that the measurement of impedance does not exceed a threshold for the AC voltage frequency (i.e., determination block 606=“No”), the processing device may generate and output AC voltage at varying frequencies in block 602. In response to determining that the measurement of impedance does exceed a threshold for the AC voltage frequency (i.e., determination block 606=“Yes”), the processing device may determine and handle a fault associated with the AC voltage frequency in block 608. The processing device may access and retrieve fault information, including fault type, processes for remedying or addressing the fault, etc. for the AC voltage frequency from a memory, stored in association with each other, such as in a data structure or a database. The processing device may implement the processes for remedying or addressing the fault.
The following are non-exhaustive examples of faults and processes for remedying the faults for different voltage frequencies. For example, a fault associated with a first voltage frequency may include dryout detection of the PEM, and the fault may be handled by the processing device causing an increase in a humidification function in order to increase inlet stream water content to the PEM stack in order to properly humidify and moisturize the PEM. In some embodiments, each time the fault occurs, the processing device may take account of an environment in and/or around the PEM stack and may run humidification processes increasingly more often and/or at higher levels. In one embodiment, flow direction of a dead-ended PEM stack may be reversed (inlet to outlet reverses to outlet to inlet) by the processing device when PEM dryout is detected via impedance in the range of approximately 1 kHz.
In another example, a fault associated with a second voltage frequency may include poisoning of the PEM. If the fault occurs where there are impurities in the input constituents (e.g., water, pure oxygen) and the PEM is poisoned, a change in the cell impedance spectra may be detected. In some embodiments, the processing device may handle this fault by triggering cell rejuvenation cycles, such as hydrogen pumping from one electrode to another, or an oxidation/reduction cycle of the electrodes. In some embodiments, the processing device may handle this fault by triggering an increased function of impurity filtering mechanisms in the electrochemical system such as water or air or fuel purification.
In another example, a fault associated with a third voltage frequency may include flooding (e.g., accumulation of liquid water) of the PEM, and the fault may be handled by the processing device causing the PEM system controls to execute either a purge of the chambers where flooding is occurring, such as on the anode or cathode of the cell, and/or increasing a rate of recirculation of the anode or cathode to clear the flooding condition. In one embodiment, flooding fault may be detected by the processing device by monitoring the impedance of the PEM stack at a frequency of 1 Hz.
In another example, a fault associated with a fourth voltage frequency may include leakage from the PEM. If a leak occurs, such as detected by the processing device when there is a divergence between electrochemical system function (output flows or output power per input flow) as compared with the baseline impedance spectra, the leakage fault may be handled by the processing device by causing the electrochemical system to adjust and supply more fuel (not running as efficiently) to cover needs. The processing device may send an error code for service in order for the leak to be fixed. An impedance measurement may be taken to determine where the exact leak occurred.
In another example, a fault associated with a fifth voltage frequency may include excess reverse diffusion. If excess reverse diffusion occurs, such as detected by the processing device when there is a divergence of output as compared to cell impedance values, then the electrochemical system will evaluate why the excess happens, and if it is strictly environmental, the excess reverse diffusion fault may be handled by the processing device by causing the electrochemical system to correct itself and decrease input reactant use to minimize reverse diffusion.
In another example, a fault associated with a sixth voltage frequency may include bubble formation on an anode. If bubbles form on the anode plate as detected by the processing device through low frequency impedance monitoring, the processing device may handle this fault by jogging or increasing water flow in order to remove the bubbles.
In another example, a fault associated with a seventh voltage frequency may include insufficient compression. The processing device may detect an insufficient compression fault when impedance spectra indicate that bulk resistance has increased. The processing device may handle this fault by increasing compression may in order to compensate and correct the condition.
In block 610, the processing device may send notice(s) to a service team. In some embodiments, the processing device may send a notice that a fault has occurred. The notice may be specific as to the type of fault detected and/or include AC impedance spectroscopy results, such as an impedance measurement, a voltage frequency, and/or a location in the electrochemical system of the measured impedance. In some embodiments, the processing device may send a notice that the error has been resolved and/or not resolved. In some embodiments, the processing device may send a notice of the impact on the electrochemical system performance.
In some embodiments, the blocks of the method 600 may be implemented in any combination of continuously, periodically, and responsively. For example, blocks 602, 604, 606 may be continuously implemented, even in parallel with the implementation of each other and/or other blocks of the method 600.
In some embodiments, the impedance spectroscopy is used to separately measure the impedance of portions of an electrochemical stack, such as a PEM stack. For example, impedance of one portion of a stack may be compared to an impedance of another portion of the same stack, or to a reference impedance or the average of the stack with impedance values. A differential impedance measurement across portion of the stack may pinpoint the error or fault easier. Furthermore, in addition to the measuring of impedance, the triggering current bypass or shunting of portion (i.e., section) sections of a stack based on impedance will also occur. This provides for a more efficient system which requires less manual service and maintains a longer lifespan. In other words, a defective portion of a PEM stack may be bypassed electrically in case of an error impedance measurement from the defective portion.
In one embodiment, the power electronics hardware 100a, 100b, 200, 300a, 300b, 400, and 500 in
Various examples (including, but not limited to, the examples discussed above with reference to
With reference to
The above systems, devices, methods, processes, and the like may be realized in hardware, software, or any combination of these suitable for the control, data acquisition, and data processing described herein. This includes realization in one or more microprocessors, microcontrollers, embedded microcontrollers, programmable digital signal processors or other programmable devices or processing circuitry, along with internal and/or external memory. This may also, or instead, include one or more application specific integrated circuits, programmable gate arrays, programmable array logic components, or any other device or devices that may be configured to process electronic signals. It will further be appreciated that a realization of the processes or devices described above may include computer-executable code created using a structured programming language such as C, an object oriented programming language such as C++, or any other high-level or low-level programming language (including assembly languages, hardware description languages, and database programming languages and technologies) that may be stored, compiled or interpreted to run on one of the above devices, as well as heterogeneous combinations of processors, processor architectures, or combinations of different hardware and software. At the same time, processing may be distributed across devices such as the various systems described above, or all of the functionality may be integrated into a dedicated, standalone device. All such permutations and combinations are intended to fall within the scope of the present disclosure.
Embodiments disclosed herein may include computer program products comprising computer-executable code or computer-usable code that, when executing on one or more computing devices, performs any and/or all of the steps of the control systems described above. The code may be stored in a non-transitory fashion in a computer memory, which may be a memory from which the program executes (such as random access memory associated with a processor), or a storage device such as a disk drive, flash memory or any other optical, electromagnetic, magnetic, infrared or other device or combination of devices. In another aspect, any of the control systems described above may be embodied in any suitable transmission or propagation medium carrying computer-executable code and/or any inputs or outputs from same.
The method steps of the implementations described herein are intended to include any suitable method of causing such method steps to be performed, consistent with the patentability of the following claims, unless a different meaning is expressly provided or otherwise clear from the context. So, for example performing the step of X includes any suitable method for causing another party such as a remote user, a remote processing resource (e.g., a server or cloud computer) or a machine to perform the step of X. Similarly, performing steps X, Y and Z may include any method of directing or controlling any combination of such other individuals or resources to perform steps X, Y and Z to obtain the benefit of such steps. Thus, method steps of the implementations described herein are intended to include any suitable method of causing one or more other parties or entities to perform the steps, consistent with the patentability of the following claims, unless a different meaning is expressly provided or otherwise clear from the context. Such parties or entities need not be under the direction or control of any other party or entity, and need not be located within a particular jurisdiction.
It will be appreciated that the methods and systems described above are set forth by way of example and not of limitation. Numerous variations, additions, omissions, and other modifications will be apparent to one of ordinary skill in the art. In addition, the order or presentation of method steps in the description and drawings above is not intended to require this order of performing the recited steps unless a particular order is expressly required or otherwise clear from the context. Thus, while particular embodiments have been shown and described, it will be apparent to those skilled in the art that various changes and modifications in form and details may be made therein without departing from the scope of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202021027158 | Jun 2020 | IN | national |
