Patent Application
20220391172
Softmax is a common operation in neural networks, often used where a discrete probability is needed. It is also used in some cases to normalise a tensor so that all elements along a certain axis or axes are strictly in the range [0,1] and sum to 1. The challenge of implementing a softmax layer in a neural network is that it is a relatively complicated operation with several steps.
A softmax layer performs, for any value xj in a set or vector of values, the operation:
In order to drop the subscript notation, this equation can be rewritten in terms of a vector x:
Softmax maps input values in the range (−∞, +∞) to outputs in the range [0,1]. Furthermore, the sum of the output values is 1 (as required for a discrete probability distribution).
It is known that the evaluation of a softmax layer may suffer from numerical instability problems if the input values x are large in magnitude. The input x may have such large positive values that overflow occurs in the output of the exponential ex, or such large negative values that underflow occurs. Even when overflow does not occur, with large values of x, some of the exponential values ex may be so large in comparison with others that the normalisation is no longer reliable.
A solution to at least some of these issues is to subtract the maximum value from all values in the tensor (or vector) x:
Where M=max(x). This redefined layer is identical to the definition above but is more stable numerically. The subtraction of the maximum reduces the range of the input from (−∞, +∞) to (−∞, 0], but does not affect the result.
Traditionally, a softmax layer has often been used as the final layer of a neural network used for classification—for example, image classification. Here, the softmax layer would produce a vector of probabilities, each value in the vector representing the probability (as estimated by the neural network) that the image belonged to a respective class from a set of mutually exclusive classes. Softmax is often applied over the channel dimension of a 4D tensor with dimensions for batch, height, width and channels, but the present disclosure is not limited to this usage.
It is becoming increasingly common to implement neural networks on specially adapted hardware accelerators, known as neural network accelerators (NNAs). These devices—usually integrated circuits—are typically specialised at evaluating the most computationally intensive operations encountered when using a neural network for inference. For example, a neural network accelerator may include a plurality of convolution engines, which are specialised at evaluating convolutional layers.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
Methods are disclosed for implementing an exponential operation, and a softmax neural network layer, in neural network accelerator hardware. Also disclosed are a data processing system for implementing the exponential operation and a data processing system for implementing the softmax layer. The exponential operation or softmax layer is mapped to a plurality of elementary neural network operations, and the neural network accelerator hardware evaluates these operations, to produce the result of the operation or layer respectively. It should be understood that the term “exponential operation” is used to refer to an operation implementing the natural exponential function ƒ(x)=ex.
According to one aspect, there is disclosed a method of implementing an exponential operation in a hardware accelerator comprising fixed-function circuitry configured to perform a set of available elementary neural network operations, according to claim 1.
The input to the layer may be a tensor or a vector. Where the input is a tensor, the tensor may have dimensions of batch, channel, height, and width.
The first, second, and/or third LUT may each be implemented by a separate hardware module. Alternatively, two of these LUTs (in particular, the first LUT and second LUT) may be implemented by the same hardware module at different times. For example, a single LUT hardware module may be loaded with values representing a sigmoid function, for evaluating the first lookup, at a first time, and may be loaded with values representing a reciprocal function, for evaluating the second lookup, at a second time. This can increase hardware utilisation, reuse, and flexibility, by re-using the same LUT hardware for different operations.
The representation may comprise or consist exclusively of the plurality of elementary neural network operations.
“Fixed-function,” in this context, refers to the property of the hardware that the logic it implements cannot be reconfigured after manufacture (or at least cannot be reconfigured extensively). This is in contrast to field programmable logic, for example, which is reconfigurable. It is also in contrast with general purpose processor hardware, which is fully programmable to implement any (arbitrary) function or algorithm. The hardware accelerator may be comprised in an application specific integrated circuit (ASIC). The behaviour of the fixed-function hardware may be programmable to a limited extent. A fixed-function hardware module may be able to perform its fixed function under the control of a limited set of parameters, for example. Each hardware module may therefore be reconfigurable only in the sense that it can implement, for example, convolution or pooling with various strides and kernel sizes, but it is not fully programmable in the sense that it could execute an arbitrary algorithm.
The plurality of elementary neural network operations may implement: a negation, applied to input values, to produce negated input values; a sigmoid function, applied to the negated input values, to produce sigmoid negated values; a reciprocal operation, applied to the sigmoid negated values, to produce reciprocal sigmoid values; and an addition or subtraction, applied to the reciprocal sigmoid values, to subtract a constant from the reciprocal sigmoid values and thereby produce output values of the exponential operation.
The constant may be equal to 1 (unity). The constant may be expressed as a positive number (for example, +1) and subtracted from the reciprocal sigmoid values. Alternatively, the constant may be expressed as a negative number (for example, −1) and added to the reciprocal sigmoid values.
According to this method, the exponential operation can be constructed from elementary operations using the identity
This representation of the exponential operation consists entirely of operations that can be performed by existing hardware in an exemplary hardware accelerator. The use of the sigmoid function is based on the recognition that this function is related to the exponential operation. This relationship is usually used to evaluate the sigmoid function by first evaluating the exponential function. However, it has been recognised that the relationship can be inverted, to allow the exponential operation to be evaluated by first evaluating the sigmoid function. This can provide a convenient way to evaluate the exponential operation, since the sigmoid function is a common activation function and may therefore already be implemented efficiently in a hardware accelerator.
The negation may be evaluated by an element-wise subtraction operation, using an element-wise operations unit of the hardware accelerator.
The sigmoid function may be evaluated by a first lookup, using an activation unit of the hardware accelerator.
The sigmoid function is a standard choice for an activation function; therefore, a lookup table (LUT) in an exemplary hardware accelerator will commonly offer the ability to implement a sigmoid function.
The reciprocal operation may be evaluated by one of: a second lookup, using an activation unit of the hardware accelerator; a local response normalisation, using an LRN unit of the hardware accelerator; and an element-wise division, using an element-wise operations unit of the hardware accelerator.
Local response normalisation is a commonly used operation in neural networks, for scaling variables. The LRN is a computationally complex function; however, the inventors have realised that, by choosing the parameters of the function carefully, the LRN can be simplified and exploited to implement a reciprocal. Alternatively, reciprocals may be programmed into a lookup table (if the hardware and software implementation allows this flexibility).
In some embodiments, the reciprocal operation and the sigmoid function may be combined in the third lookup. For example, the third LUT may contain the function
In some of these embodiments, the reciprocal operation and the sigmoid function may be further combined with the first subtraction, which negates the input values. That is, the third LUT may contain the function
The third lookup, like the first lookup and the second lookup, may be evaluated using an activation unit of the hardware accelerator.
The addition or subtraction may be evaluated by an element-wise addition or element-wise subtraction, using an activation unit of the hardware accelerator. The activation unit may be configured to add/subtract the same value to/from every element of a tensor.
According to another aspect, there is provided a method of implementing a softmax layer in a hardware accelerator comprising fixed-function circuitry configured to perform a set of available elementary neural network operations, according to claim 7.
The plurality of elementary neural network operations may include at least one function approximation operation, wherein the function approximation operation is implemented as a lookup in an LUT, the LUT optionally comprising one of: a sigmoid function; a reciprocal function; a reciprocal of a sigmoid function; the function ƒ(z)=2z, where z is a value in the range (0,1) and an exponential function.
If the plurality of elementary neural network operations comprises two or more lookups, then these lookups may be implemented by separate LUTs, in separate hardware modules. Alternatively, they may be implemented by a single LUT hardware module carrying out different lookups at different times. Reuse of a single LUT in this way can improve hardware utilisation.
The plurality of elementary neural network operations may implement: a maximum operation, applied to input values, to obtain the maximum among the input values; a first subtraction, subtracting the maximum from each of the input values, to produce negative-shifted input values; an exponential operation, applied to the negative-shifted input values, to produce exponentiated values; a summation, applied to the exponentiated values, to produce a sum of the exponentiated values; and a division, dividing each of the exponentiated values by the sum of the exponentiated values.
The maximum operation may be evaluated by one of: a max pooling operation, using a pooling unit of the hardware accelerator; and repeated iterations of an element-wise maximum operation, using an element-wise operations unit of the hardware accelerator.
If the softmax layer is to be evaluated over a channel dimension (or batch dimension) of an input tensor, evaluating the maximum operation by means of the max pooling operation may comprise applying a transpose (or permute) operation to the input tensor prior to the max pooling, so that the elements whose maximum is to be calculated are arranged over one or both of a height dimension and a width dimension. This may be beneficial if the pooling unit is specialised at evaluating pooling operations over one or both of these spatial dimensions. A transpose (or permute) operation may be applied after the max pooling, to invert the first transpose and return the dimensions to their original configuration.
If the maximum operation is to be evaluated by means of repeated element-wise maximum operations, the evaluating may comprise splitting the input tensor into two halves, comparing the two halves element-wise by means of an element-wise maximum, and repeating this process until a single unique maximum value (in the relevant dimension or dimensions) is obtained.
The first subtraction may be evaluated by an element-wise subtraction operation, using an element-wise operations unit of the hardware accelerator.
The exponential operation may be mapped to a subset of the plurality of elementary neural network operations, wherein said subset implements: a negation, applied to the negative-shifted input values, to produce negated input values; a sigmoid function, applied to the negated input values, to produce sigmoid negated values; a first reciprocal operation, applied to the sigmoid negated values, to produce reciprocal sigmoid values; and an addition or a second subtraction, applied to the reciprocal sigmoid values, to subtract a constant from the reciprocal sigmoid values and thereby produce output values of the exponential operation.
The component operations of the exponential operation may be implemented as already summarised previously above.
Alternatively, in some embodiments, the exponential operation may be evaluated directly by a lookup in an LUT, using an activation unit of the hardware accelerator.
The summation may be evaluated by a convolution, using one or more convolution engines of the hardware accelerator. The convolution may comprise a convolution with a tensor of ones of the same size as the tensor of exponentiated values in the dimensions over which the sum is to be taken. If the softmax layer is to be applied over the channel dimension, the convolution may be a 1×1 convolution, wherein the kernel has width=height=1, a number of input channels equal to the number of channels in the tensor of exponentiated values, and a single output channel.
The division may be implemented as a second reciprocal operation and a multiplication.
The multiplication operation may be evaluated by an element-wise multiplication operation, using an element-wise operations unit of the hardware accelerator.
At least one of the first reciprocal operation and the second reciprocal operation may be evaluated by one of: a lookup, using an activation unit of the hardware accelerator; a local response normalisation, using an LRN unit of the hardware accelerator; and an element-wise division, using an element-wise operations unit of the hardware accelerator.
The inventors have recognised that a local response normalisation can be used to calculate reciprocals. By setting the constants α, β=1 and k, n=0, the LRN reduces from a complicated normalisation function to one that returns the reciprocal of the input.
One reciprocal operation may be evaluated using the activation unit and the other reciprocal operation may be evaluated by the LRN unit. Alternatively, both reciprocal operations may be evaluated by the activation unit, or both reciprocal operations may be evaluated by the LRN unit.
In some embodiments, the softmax layer is to be applied to input data comprising a first element and a second element, and wherein the plurality of elementary neural network operations implements: at least one subtraction, to obtain at least one difference between the first element and the second element; and a sigmoid function, applied to the at least one obtained difference, to produce an output of the softmax layer.
The first element and second element may be elements of a tensor. The tensor may have a size of 2 in the dimension in which the softmax layer is to be evaluated.
The at least one subtraction may be evaluated by a convolution, using one or more convolution engines of the hardware accelerator. Alternatively, or in addition, the sigmoid function may be evaluated by a function approximation operation, optionally using an activation unit of the hardware accelerator. The function approximation operation may comprise a lookup in an LUT of the activation unit.
Mapping the neural network layer to the representation comprising the plurality of elementary neural network operations optionally comprises: identifying at least two consecutive elementary neural network operations that can be combined; and combining the at least two consecutive elementary neural network operations into a smaller number of elementary neural network operations.
For example, a negation operation may be combined with an addition or subtraction operation. In another example, two consecutive LUT lookup operations could be combined by loading into a single LUT a representation of a single compound function that combines the individual functions that were implemented by the consecutive LUTs.
Also provided is a data processing system for implementing an exponential operation, according to claim 19. The representation may comprise or consist exclusively of the plurality of elementary neural network operations.
Additionally provided is a data processing system for implementing a softmax layer, according to claim 20. Again, the representation may comprise or consist exclusively of the plurality of elementary neural network operations. The function approximation operation may be implemented as a lookup in an LUT.
The hardware accelerator may comprise any one of, or any combination of two or more of: an activation unit, comprising an LUT; a local response normalisation unit, configured to perform a local response normalisation; an element-wise operations unit, configured to apply a selected operation to every pair of respective elements of two tensor of identical size; one or more convolution engines, configured to perform convolution operations; and a pooling unit, configured to perform pooling operations, including (but generally not limited to) max pooling.
Optionally, when the hardware accelerator comprises the activation unit, one or more of the plurality of elementary neural network operations may implement a sigmoid function, and the activation unit may be configured to evaluate the sigmoid function.
Optionally, when the hardware accelerator comprises the local response normalisation unit, one or more of the plurality of elementary neural network operations may implement a reciprocal operation, and the local response normalisation unit may be configured to evaluate the reciprocal operation.
The data processing system may further comprise a memory manipulation module, configured to manipulate data stored in a memory, and the hardware accelerator may comprise a pooling unit, configured to perform pooling operations, including max pooling. The one or more of the plurality of elementary neural network operations may implement a maximum operation, applied to input data over a channel dimension, wherein the memory manipulation module is configured to rearrange the dimensions of the input data to arrange the channel dimension over one or more spatial dimensions, and wherein the pooling unit is configured to evaluate the maximum operation by performing max pooling over the one or more spatial dimensions.
Also provided is a data processing system configured to perform the method of any of the appended claims.
A data processing system may be embodied in hardware on an integrated circuit.
Also provided is a method of manufacturing, using an integrated circuit manufacturing system, a data processing system as summarised above or as claimed in any of the appended claims.
Also provided is a method of manufacturing, using an integrated circuit manufacturing system, a data processing system as summarised above or as claimed in any of the appended claims, the method comprising: processing, using a layout processing system, a computer readable description of the data processing system so as to generate a circuit layout description of an integrated circuit embodying the data processing system; and manufacturing, using an integrated circuit generation system, the data processing system according to the circuit layout description.
Also provided is computer readable code configured to cause a method as summarised above or the method of any of the appended claims to be performed when the code is run. Also provided is a computer readable storage medium having encoded thereon said computer readable code.
Further provided is an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a data processing system as summarised above or as claimed in any of the appended claims.
Additionally provided is a computer readable storage medium (optionally non-transitory) having stored thereon a computer readable description of a data processing system as summarised above or as claimed in any of the appended claims that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the data processing system or NNA.
Also provided is a computer readable storage medium (optionally non-transitory) having stored thereon a computer readable description of a data processing system as claimed in any of the appended claims which, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to: process, using a layout processing system, the computer readable description of the data processing system so as to generate a circuit layout description of an integrated circuit embodying the data processing system; and manufacture, using an integrated circuit generation system, the data processing system according to the circuit layout description.
Also provided is an integrated circuit manufacturing system configured to manufacture a data processing system as summarised above or as claimed in any of the appended claims.
Also provided is an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable description of a data processing system as summarised above or as claimed in any of the appended claims; a layout processing system configured to process the computer readable description so as to generate a circuit layout description of an integrated circuit embodying the data processing system; and an integrated circuit generation system configured to manufacture the data processing system according to the circuit layout description.
The layout processing system may be configured to determine positional information for logical components of a circuit derived from the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the data processing system.
The above features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the examples described herein.
Examples will now be described in detail with reference to the accompanying drawings in which:
The accompanying drawings illustrate various examples. The skilled person will appreciate that the illustrated element boundaries (e.g., boxes, groups of boxes, or other shapes) in the drawings represent one example of the boundaries. It may be that in some examples, one element may be designed as multiple elements or that multiple elements may be designed as one element. Common reference numerals are used throughout the FIGs., where appropriate, to indicate similar features.
The following description is presented by way of example to enable a person skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein and various modifications to the disclosed embodiments will be apparent to those skilled in the art.
Embodiments will now be described by way of example only.
Faced with a desire to implement a softmax layer in a system using a neural network accelerator (NNA), one possibility would be to design a dedicated fixed-function hardware module that is specialised at evaluating softmax layers. This hardware module could then be included in the NNA, where it would take responsibility for evaluating any softmax layers, as needed.
Another alternative would be to evaluate softmax layers in general purpose hardware outside the NNA, such as a general purpose CPU or DSP.
Providing a dedicated fixed-function hardware module in an NNA, to handle the evaluation of softmax layers, may allow for an optimised, fast evaluation. However, it has the drawback that the dedicated fixed-function hardware module occupies additional area in the integrated circuit. Moreover, because the evaluation of softmax layers typically represents a small part of the workload of the NNA, the utilisation of the dedicated fixed-function hardware module will be low for most typical neural networks. In other words, the dedicated fixed-function softmax module will be inactive most of the time.
Meanwhile, evaluating softmax layers in general purpose hardware allows for flexibility, and avoids leaving large areas of the NNA underutilised; however, it is typically less efficient, because the hardware is less specialised.
The configurability of general purpose hardware incurs a cost in power and area because: (i) additional logic is required to route the data flexibly; (ii) computational elements cannot be as specialised, meaning that computational density is generally not as high as for fixed-function hardware; and (iii) it is harder to balance the bandwidth and compute requirements of the hardware. Dedicated hardware can be more efficient because it is designed such that it does not include any more functionality than is strictly necessary for the task at hand.
Additionally, when using general-purpose hardware that is external to the NNA, there is an overhead in transferring the necessary data from the NNA to the general-purpose hardware (for example, CPU). This typically involves the NNA writing the data to a memory, and the CPU reading the data from the memory, before evaluating the softmax layer. This is likely to slow down the evaluation of the layer, especially if—as is often the case—the speed of memory access dominates. Furthermore, CPU time is often at a premium due to the requirements of the operating system and other processes being run. Spending CPU time evaluating the softmax layer can cause these other processes to slow down and is an inefficient use of resources. The same is also true for GPUs and DSPs.
The performance penalty incurred by using an external CPU to evaluate the softmax layer might be mitigated when this layer is the final layer of the neural network. In this case, the output of the softmax layer does not need to be transferred back to the NNA for further processing. However, this still consumes host CPU time (potentially in considerable quantities, especially at high inference rates). Moreover, in some recent attention based neural networks, it is becoming more common to include softmax layers as intermediate layers within the neural network. This means that the output data of the softmax layer needs to be transferred back to the NNA for further processing. A softmax layer within a neural network may also have larger input and output tensors than a typical softmax layer at the output of the neural network. This increase in the size of the data increases the memory bandwidth required, and therefore increases the performance penalty for using an external CPU to evaluate the layer. Increasing the bandwidth used also has the effect of increasing power consumption.
Still another alternative would be to include one or more general programmable units, such as a CPU or digital signal processor (DSP), within the NNA itself. This would in one sense be a hybrid of the two possible solutions mentioned above. It would avoid the need to consume system bandwidth in order to hand over the evaluation of each softmax layer to an external general-purpose processor; however, it would have the disadvantages of increased hardware/software complexity, increased power consumption and greater integrated circuit area occupied.
It would be desirable to implement softmax layers within an NNA, but without the need to add a dedicated hardware unit, or additional general-purpose hardware, to the NNA architecture for this purpose. However, until now, it has not been apparent how a relatively complex softmax layer could be evaluated by the relatively limited set of operations that an exemplary NNA is adapted to perform. Unlike the operations performed by a CPU, the operations performed by an NNA are not designed to be a flexible or complete set of general purpose operations. Instead, each neural network operation is specialised to perform a particular computationally intensive neural network calculation quickly and efficiently. The trade-off is that an NNA has a very limited capacity to perform functions beyond this specialised set. For this reason, it is challenging to repurpose existing neural network operations to evaluate softmax layers.
Examples according to the present disclosure provide ways to implement a softmax layer in hardware, based on elementary neural network operations that are available on an exemplary NNA. The softmax layer can be viewed as a computational graph, as shown in
As shown in
Examples of the present disclosure use elementary neural network operations, executed by these fixed-function hardware units, to implement a softmax layer. In the present implementation, the calculations are performed in fixed point arithmetic. Experiments have shown that the fixed point implementation is sufficiently accurate that it does not significantly degrade the overall accuracy of the exemplary neural networks tested.
A softmax layer may be constructed from the following operations:
For each of these operations, there may be more than one way that the operation can be restructured for execution on the hardware accelerator. The operations will be explained in turn in more detail below.
First, the input tensor x undergoes a maximum operation 110. This operation is performed over the dimension or dimensions in which the softmax layer is to be evaluated. In the current example of channel-wise softmax, this operation is performed along the channel dimension. Where the softmax layer is evaluated over a different dimension or dimensions, the maximum operation 110 would instead be performed along that different dimension or dimensions. The maximum operation 110 returns the largest positive value over the relevant dimension(s) within x, to produce a tensor of maximum values M. In subtraction operation 120, also referred to as the first subtraction, the tensor of maximum values M is subtracted from the respective elements of the tensor x. (This can be implemented using broadcasting, as discussed in further detail below). This subtraction operation 120 results in a negative-shifted tensor x−M. The negative-shifted tensor is input to an exponential operation 130. This calculation applies each element of the negative-shifted tensor as a power of Euler's number e. The exponential operation 130 results in a tensor of exponentiated values, referred to herein as the exponential tensor ex−m. The exponential tensor ex−M undergoes a summation 140. This summation sums all of the elements of the exponential tensor along the dimension or dimensions in which the softmax layer is to be evaluated (in the current example, the channel dimension), resulting in a tensor containing the sum of the exponentiated values Σex−M. In division operation 150, the exponentiated values are divided by their sum. This returns the output of the softmax layer:
Continuing with the example of
Finally, the tensor of reciprocal sigmoid values undergoes a second subtraction 138, to subtract a constant (one) from each element of the tensor. This returns the exponential tensor
which is identical to ex−M.
In general, this exemplary method of using the operations available in the exemplary NNA to perform the exponential operation 130 may be used either on its own to evaluate an exponential operation, or as part of an implementation of a softmax layer.
The memory interface 210 is configured to provide an interface between the hardware accelerator 200 and external memory 25. The external memory 25 may be considered as a separate module to the hardware accelerator 200. The command or configuration information may, for example, comprise information regarding weight and data size and format as well as their location in the external memory.
The memory interface 210 is configured to receive, from external memory 25, weights and data to be used in calculations within the neural network, as well as command information to control the operation of the hardware accelerator 200. The received weights (also referred to herein as coefficients) are passed to the coefficient buffer controller 225 and the received data is passed to the input buffer controller 215. The received commands are passed to the command decoder 220, which, in turn, is configured to decode the commands and subsequently issue control information to elements of the hardware accelerator, including the coefficient buffer controller 225 and input buffer controller 215 to control the manner in which the weight and input data is stored in the buffers.
The weights and input data received from external memory via memory interface 210 during a read of the external memory may form the weights and input data for only a portion of a single layer, all of the weights and input data to be used in processing a single layer, or may comprise the weights and input data for processing multiple layers. For example, the weights received from external memory may form the weights of a single layer and the input data received may form only a portion of the input data for a single layer (or vice versa). Any combination of data and weights across one or more layers may be received from external memory 25 in a single read from the memory (for example using a burst read).
In practice, the number of weights and data received in a single read from external memory 25 will depend upon the size of the coefficient buffer 230 and the input buffer 235. The weights are passed from the coefficient buffer controller 225 to the coefficient buffer 230 and the data received is passed from the input buffer controller 215 to a plurality of input buffers 235a-235n. The number of input buffers will depend upon the specific implementation of the accelerator 200 but may take any value. The input data is shared across all of the input buffers 235a-235n. The input buffers each form an effective bank such that the number of input buffers can be increased or decreased depending on the application.
The input buffers 235a-235n are connected to each of a plurality of multiplexers since each convolution engine 240a-240n requires access to all of the effective ‘banks’ of the input data. The multiplexers are each configured to select an output from one of the input buffers 235 and to pass the values output from the selected input buffer 235 to a respective convolution engine 240a-240n. In addition, weights from the coefficient buffer 230 are provided as a second input into each convolution engine 240a-240n. The convolution engines 240 are configured to perform a convolution calculation on the received input data using the weights received from the coefficient buffer 230. The resultant output of each convolution engine 240a-240n is provided as an input to a respective accumulator of a plurality of accumulators 245a-245n.
Each accumulator 245a-245n is connected to an accumulation buffer 250. The accumulation buffer 250 is configured to store accumulated results received from each accumulator 245a-245n. The accumulation buffer 250 is connected to the memory interface 210. As such, the accumulation buffer 250 is configured to send and receive data to and from external memory 25 via memory interface 210. Specifically, the accumulation buffer 250 is configured to be able to store and restore its values from the external memory 25 via memory interface 210, as will be described in more detail below. The accumulation buffer 250 is connected to the input of the accumulators 245a-245n and is configured to feed values back into the accumulators 245a-245n to enable accumulation calculations to take place.
The accumulation buffer 250 is configured to pass accumulated values to the activation unit 255 and/or the element-wise operations unit 285. The activation unit 255 is configured to perform at least one of a number of different activation functions. The activation unit 255 incorporates a lookup table (LUT), for storing an activation function, such as a sigmoid activation, to be applied to data input to the activation unit. The activation unit 255 is also operable to add/subtract a bias value to/from a tensor. This can be used to add a constant to the tensor or subtract a constant from the tensor.
The resultant value calculated by the activation unit 255 can be passed to be processed by the LRN unit 265 and/or the pooling unit 275 via the shared buffer 270. The LRN unit 265 is configured to perform a local response normalisation. This may be performed within a single plane of input data. Alternatively or in addition, the LRN operation may also be performed across planes.
A result stored in the shared buffer 270 is passed to the memory interface 210, which can either store the result in external memory 25 or pass the result back into the input buffers for further processing without having to first be passed out to external memory.
The shared buffer 270 is configured to buffer values from any one or more of the activation unit 255, the LRN unit 265, the pooling unit 275, and the element-wise operations unit 285 until all the values required to perform the next operation are available. In this way, the shared buffer 270 is used for efficiency of storage as it can hold values required in later operations without having to use external memory 25.
The element-wise operations unit 285 comprises circuitry configured to perform element-wise operations on tensors received from the accumulation buffer 250 and/or activation unit 255. The supported element-wise operations may include element-wise addition, subtraction, multiplication, division, and maximum (or minimum) of the respective elements of the tensors.
Element-wise operations are operations that are repeated for multiple elements of at least one tensor. The operations are typically repeated for all elements of the tensor. Two categories of element-wise operation may be considered: unary operations, having a single operand, and binary operations, having two operands. The element-wise operations unit 285 handles binary element-wise operations. Element-wise operations may also be performed by other components of the hardware accelerator. For example, the activation unit 255 may perform unary element-wise operations, by loading a desired function into the LUT and applying the function to every element of a tensor.
Whilst the hardware accelerator of
In some examples, the functions performed by the activation 255, LRN 265, pooling 275, and element-wise 285 units may all be performed. In other examples, only some of these functions may be performed and not necessarily in the order set out in the hardware accelerator 200. To achieve a configurable order of processing these functions, each of the activation 255, LRN 265, pooling 275 and element-wise 285 units may be configured to receive control signalling configuring the unit into a bypass mode in which the function is not performed and the input values are simply passed through the unit without change.
In some examples, the data of a particular layer may need to be processed first by the convolution engines 240a-n and then second according to the activation, LRN, pooling, and element-wise units 255, 265, 275, 285. In these examples, the outputs from the convolution engines 240a-n are passed via the accumulators 245a-n to the accumulation buffer 250 and are then passed to activation, LRN, pooling, and element-wise units 255, 265, 275, 285 for further processing. In other examples, the data may need to be processed differently. For example, data may need to be processed first according to the activation, LRN, pooling, and element-wise units 255, 265, 275, 285 and second according to the convolution engines 240a-n.
In these arrangements, data can be passed directly to the activation unit 255 via the accumulation buffer 250, where the accumulation buffer 250 has received the input data directly from the memory interface 210 which has received the data from external memory. In this way, the processing performed by convolution engines 240a-n and accumulator 245a-n is effectively skipped and the data can be passed directly to the activation 255, LRN 265, pooling 275, and element-wise 285 units. Then, once processing using activation, LRN, pooling, and element-wise units 255, 265, 275, 285 is completed, the resultant values can be passed into the input buffer controller 215 via the memory interface 210. In some arrangements, the resultant values can be first passed to external memory 25 via memory interface 210 and then retrieved from external memory 25 before use.
In other arrangements, the memory interface 210 may pass the resultant values to the input buffer controller 215 without passing the values to external memory 25. By avoiding the need to pass the values resulting from calculations using the activation, LRN, pooling, and element-wise unit 255, 265, 275, 285 to external memory 25, memory bandwidth is reduced and therefore the latency in processing the data is also reduced.
Advantageously, since the activation, LRN, pooling, and element-wise units 255, 265, 275, 285 are placed linearly, it is possible to perform these operations back-to-back without having to retrieve data from external memory 25. In some implementations, the order in which the activation, LRN, pooling, and element-wise units 255, 265, 275, 285 are connected may vary. For example, the activation, LRN, and pooling units 255, 265, 275 may be connected in reverse order such that the pooling unit is connected to the accumulation buffer 250 and the activation unit is connected to the memory interface 210.
The hardware accelerator 200 is configured to evaluate the plurality of elementary neural network operations. The MMM 40 is configured to manipulate multidimensional data in memory in various ways, including transpose or permute operations that interchange different dimensions of the data. In some examples, the MMM 40 may be configured to transform data by embedding the channel dimension of the data in one or both of the width or height dimensions, or exchanging the channel dimension with one or both of these spatial dimensions. In alternative examples, the MMM may transpose or permute any other combination of the dimensions of the input data, including the batch dimension.
The memory reading block 420 reads data from the memory 25. The memory reading block 420 writes the data (that was read from the memory 25) to the internal buffer 410. The memory writing block 430 reads data from the internal buffer 410 and writes the data (that was read from the internal buffer 410) back to the external memory 25. By the combination of operations performed by the memory reading block 420 and the memory writing block 430, the data may be transformed in the ways previously described. The transformation may occur when moving the data from the memory 25 to the internal buffer 410, or it may occur when moving the data from the internal buffer 410 to the memory 25. In some cases, the transformation may occur in part between the memory 25 and the internal buffer 410, and in part between the internal buffer 410 and the memory 25.
Because the memory reading block 420 and the memory writing block 430 are provided as separate hardware blocks, they are able to operate in parallel. That is, the memory reading block 420 can perform steps 310 and 320 while the memory writing block 230 is performing steps 330 and 340 (the steps are explained in detail below with reference to
In step 310, the controller 15 receives as an input a definition of a neural network layer involving an exponential operation. In step 320, the controller maps the layer to an equivalent computational graph comprising a plurality of elementary neural network operations. In step 330, the hardware accelerator 200 evaluates the plurality of elementary neural network operations, to produce the result of the exponential operation. In the present example, the mapping to the plurality of elementary operations is based on the computational graph of
The softmax layer and exponential operation are mapped to elementary neural network operations based on manipulation of the computational graphs of
Two possible implementations of the maximum operation 110 will be explained with reference to
The maximum operation 110 can be implemented:
In the pooling unit 275; or
In the element-wise operations (EWO) unit 285.
These units may be assisted by transpose or permute operations performed, for example, in the memory manipulation module 40.
An alternative to padding is to split the tensor into more than two sub-tensors, each sub-tensor having a size in the relevant dimension that is a power of 2. For example, a tensor with 5 channels may be split into two tensors with 2 channels each and a final tensor with 1 channel. The two tensors with 2 channels can be reduced by splitting and taking the element-wise maximum, as described above. The resulting 1-channel tensors can be compared to produce a tensor with 1 channel. Finally, this tensor can be compared with the remaining tensor with 1 channel, to return the maximum of the original tensor on the channel dimension. This process is illustrated by way of example in
The splitting operation may be performed by the memory manipulation module 40, by reading data from one location and writing a first part of the data to a first location and a second part of the data to a second location. Alternatively, the splitting might not require a separate operation, and may instead be performed as part of the output of the preceding operation. In the example of
The subtractions 120, 138 and the negation 132 can be performed by the element-wise operations unit 285. The element-wise operations unit can perform a respective subtraction operation on each element of a tensor. Where a constant is subtracted—as in the subtraction 138—the subtraction may be performed either by the element-wise operations unit 285 or by the activation unit 255. Subtraction of a constant (for example, subtraction of 1) can be implemented in the activation unit by loading the function y=x−c into the LUT, where c is the constant to be subtracted. Subtraction of a constant can be implemented as an element-wise addition in the element-wise operations unit, by adding the negative of the constant (for example, adding −1). Similarly, the negation 132 could be performed either by the element-wise operations unit 285 (by subtracting the input tensor from a constant, 0), or by the activation unit 255 (by loading the function y=−x into the LUT).
In the present example, the negation 132 is performed by subtracting each element of the tensor from zero. It could also be performed by element-wise subtraction in other ways—for example, by subtracting the tensor from itself twice, or multiplying every element of the tensor by two and subtracting the result from the original tensor. Alternatively, the negation may be performed by changing the sign bit of each element of the tensor where a sign and magnitude representation of numbers is used. Where a two's complement representation is used, the negation may be performed by inverting all of the bits representing the number and then adding one.
The exponential operation 130 receives an input and raises e to the power of that input. For an input of x, the output of the exponential operation 130 is ex.
The exponential operation could be evaluated:
1. Directly in a lookup table (LUT), in the activation unit 255;
2. By means of a sigmoid function 134, reciprocal 136, negation 132 and subtraction 138 as shown in
3. By means of a reciprocal sigmoid function, negation 132 and subtraction 138.
The first implementation is relatively straightforward, provided that the hardware and software of the hardware accelerator allows the LUT to be programmed with the exponential function. However, this might not always be possible. Therefore, the second implementation may be used as an alternative.
The second implementation makes use of the following identity:
Where σ(−x) is the negative sigmoid function. Here, in common with most literature in the field of neural networks, we use the term “sigmoid” synonymously with “logistic function”. That is, the sigmoid (logistic) function is defined as:
The negative sigmoid function is therefore:
The second implementation uses elementary neural network operations to implement the steps shown in
The reciprocal 136 of the value of σ(−x) can be evaluated in several ways, depending on the exact capabilities of the hardware accelerator 200. The options for evaluation of a reciprocal include:
Referring once again to
Going one step runner, the negation 132 could also be subsumed into the LUT, so that it returns the result of the function
In practice, however, it is likely that if the LUT were fully programmable in this way, it would be easier to simply program it with the exponential function.
The summation 140, shown in
Where a softmax layer is evaluated over one or more spatial dimensions, a depth-wise convolution may be used, meaning that the kernel is applied to each channel separately. In this case, the kernel would have a size of one in the channel dimension and a size greater than one in the height and/or width dimensions. If the hardware accelerator is limited to a certain maximum kernel size, it may be necessary to iterate the convolution in order to capture all elements of the input tensor, in a similar manner to that described above for the max pooling operation. It should be understood that in other examples, the softmax layer may be evaluated over other combinations of dimensions, such as the channel dimension and one or more spatial dimensions. The convolution kernel will be adapted according to the relevant dimensions.
Alternatively, the summation 140 could be implemented by the EWO unit 285 using iterated pairwise addition operations. This approach is very similar to the element-wise maximum operation explained in relation to
The reciprocal 136 can be implemented:
Using the LRN unit 265;
Using the activation unit 255, by loading a reciprocal function into an LUT of the activation unit; or
As an element-wise division, using the element-wise operations unit 285, by dividing a constant, 1, by the input values whose reciprocal is to be calculated.
If the LUT of the activation unit 255 is available, and is programmable, it can be programmed with a reciprocal function ƒ(x)=1/x.
The LRN unit 265 may be used, in particular, if the LUT is not available or if it is not programmable to implement arbitrary functions. The LRN unit 265 is designed to carry out the following LRN calculation:
By setting α=1, β=1, k=n=0, this function can be reduced to
b
i,x,y=αi,x,y/(αi,x,y)2
Which is identical to the desired reciprocal:
b
i,x,y=1/ai,x,y
Either of these two solutions can be used to evaluate reciprocals. Both ways of evaluating reciprocals can also be useful for evaluating division operations, as explained further below. Alternatively, as mentioned above, the reciprocal could itself be implemented by means of an element-wise division, in the element-wise operations unit 285 (assuming that element-wise division is supported).
In the evaluation of the exponential operation as shown in
which is passed to the subtraction operation 138 (for example, implemented by element-wise subtraction in the EWO unit 285).
In some examples, division 150 (reproduced in
While examples of the present disclosure have been described using an LUT lookup to approximate one or more of the exponential operation, the sigmoid function and the reciprocal function, this does not have to be the case. Other function approximation operations that do not use an LUT are possible, and may be used to approximate one or more of the exponential operation, the sigmoid function and the reciprocal function. One such example of an alternative type of function approximation is iterative refinement. For example, the exponential operation may be approximated iteratively by calculating the Taylor series expansion of ex.
It should be noted that several of the substitutions outlined above involve substitute operations that are equally as complex as, or more complex than, the operations replaced. This is true of the use of the LRN unit to perform the reciprocal, for example, as well as the implementation of the exponential operation by means of the sigmoid, reciprocal, and subtraction. However, the present inventors have recognised that such substitutions—which at first glance might seem far from optimal—are nevertheless often more attractive than the alternatives of (a) using a CPU or DSP to evaluate softmax layers or (b) implementing a bespoke hardware unit to evaluate softmax layers. This is because the substitutions allow the evaluation to take advantage of the considerable computational power of the dedicated hardware modules. The use of these dedicated modules, even in a relatively “inefficient” manner, can therefore still offer performance gains in terms of power and bandwidth consumption (for example), compared with the alternatives.
The maximum 110 of
The subtraction 120 is evaluated by an element-wise subtraction 530 in the element-wise operations unit 285.
The exponential operation 130 has been replaced by the operations of
The summation 140 is evaluated by a convolution 570, using one or more of the plurality of convolution engines 240.
The division 150 is evaluated by an LRN operation 552, using the LRN unit 265, and an element-wise multiplication 580, using the element-wise operations unit 285.
It should be understood that for each step shown in
In general, when performing element-wise operations where the inputs are tensors of different sizes (like the element-wise subtraction 530 and element-wise multiplication 580), broadcasting is used. The smaller tensor is “broadcast” across the larger tensor, to repeat similar calculations for all corresponding elements of the two tensors. In the element-wise subtraction 530, for example, the original input tensor has dimensions B×C×H×W. The result of the maximum operation 510, 520, 513 has reduced dimensionality B×1×H×W, because the maximum was calculated over the channel dimension. Broadcasting, performed by the element-wise operations unit 285, enables the maximum value in each channel to be subtracted from each individual value in that channel. Broadcasting could also be used—but is not required—for operations involving a tensor and a scalar, like the element-wise subtraction 532. As an alternative to element-wise broadcasting, these tensor-scalar operations may be implemented in the activation unit 255, which always applies an operation uniformly to all elements of the tensor. As explained above, this can be done by loading an appropriate function, such as y=x−c, into the LUT of the activation unit.
When using an LUT as part of the evaluation of a softmax layer, whether as part of the exponential operation 130 or for the reciprocal 136, precision may be improved by restricting the range of values loaded into the LUT. Using the example of
In another example, an LUT loaded with exponential values may have its outputs limited in order to improve precision within a desired range. In the example of
The implementation of a special case of a softmax layer will now be described, with reference to
Accordingly, the evaluation of the softmax layer can be broken down into two steps:
The calculation of the differences, (a−b) and (b−a); and
The application of the sigmoid function to each difference.
The first difference, a−b, can be evaluated by convolving the input tensor with a filter [1, −1]. Similarly, the second difference, b−a, can be evaluated by convolving the input tensor with a filter [−1, 1]. These two operations can be carried out by a single convolution operation 571, with two input channels, and two filters (that is, two output channels), with dimensions 2×2×1×1. In other words, just a single call to a convolution routine can evaluate both operations together, using the convolution engines 240.
As an alternative, it will be apparent that each difference is the negative of the other:
a−b=−(b−a)
Therefore, a first difference could be formed (for example, by convolution or element-wise subtraction), and the second difference could be obtained by negating the first (for example, by changing the sign bit of each value). Nevertheless, in the present example, because of the optimised implementation of the convolution operation in the hardware accelerator, it has been found that using the convolution operation 571 is more efficient.
Having obtained the tensor containing the differences (a−b) and (b−a), a sigmoid activation 541 can be applied by means of a lookup in the LUT of the activation unit 255, as described above. This returns the output of the softmax layer, for this special case.
It will be understood that the examples described above are not limiting, and many variations are possible. For instance, although the examples above have focused on the case of a softmax layer evaluated over the channel dimension, a softmax layer could alternatively be evaluated over any other dimension or combination of dimensions, without limitation. The specific substitutions to map the layer to elementary neural network operations might vary, but the same principles (and same advantages) would apply.
In addition to the examples mentioned above, there may be other ways in which an exponential operation could be implemented in hardware. For example, an exponential operation could be implemented using the relationship ex=2kx, where k=log2e is a constant. This may be evaluated in two parts: firstly an element-wise multiply, to evaluate the product kx, followed by raising 2 to the power of this product. This latter step can be accomplished in two stages. The integer part of the power can be implemented by a bit-shift—for example, to raise 2 to the power of 3, a bit may be shifted to the left by three places. The non-integer part of the power—a number in the range (0,1)—can be implemented using an LUT with a further element-wise multiplication to combine this with the integer part of the power.
Alternatively, in some implementations, the hardware accelerator may natively support the operation 2z, where z is in general a non-integer value—for example by adding an additional fixed-function unit to handle this elementary operation, in the block diagram of
Some optimisations may also be possible. For example, it may be noted that the computational graphs of
In the example of
While
The data processing system of
The data processing systems described herein may be embodied in hardware on an integrated circuit. The data processing systems described herein may be configured to perform any of the methods described herein. Generally, any of the functions, methods, techniques or components described above can be implemented in software, firmware, hardware (e.g., fixed logic circuitry), or any combination thereof. The terms “module,” “functionality,” “component”, “element”, “unit”, “block” and “logic” may be used herein to generally represent software, firmware, hardware, or any combination thereof. In the case of a software implementation, the module, functionality, component, element, unit, block or logic represents program code that performs the specified tasks when executed on a processor. The algorithms and methods described herein could be performed by one or more processors executing code that causes the processor(s) to perform the algorithms/methods. Examples of a computer-readable storage medium include a random-access memory (RAM), read-only memory (ROM), an optical disc, flash memory, hard disk memory, and other memory devices that may use magnetic, optical, and other techniques to store instructions or other data and that can be accessed by a machine.
The terms computer program code and computer readable instructions as used herein refer to any kind of executable code for processors, including code expressed in a machine language, an interpreted language or a scripting language. Executable code includes binary code, machine code, bytecode, code defining an integrated circuit (such as a hardware description language or netlist), and code expressed in a programming language code such as C, Java® or OpenCL. Executable code may be, for example, any kind of software, firmware, script, module or library which, when suitably executed, processed, interpreted, compiled, executed at a virtual machine or other software environment, cause a processor of the computer system at which the executable code is supported to perform the tasks specified by the code.
A processor, computer, or computer system may be any kind of device, machine or dedicated circuit, or collection or portion thereof, with processing capability such that it can execute instructions. A processor may be any kind of general purpose or dedicated processor, such as a CPU, GPU, NNA, System-on-chip, state machine, media processor, an application-specific integrated circuit (ASIC), a programmable logic array, a field-programmable gate array (FPGA), or the like. A computer or computer system may comprise one or more processors.
It is also intended to encompass software which defines a configuration of hardware as described herein, such as HDL (hardware description language) software, as is used for designing integrated circuits, or for configuring programmable chips, to carry out desired functions. That is, there may be provided a computer readable storage medium having encoded thereon computer readable program code in the form of an integrated circuit definition dataset that when processed (i.e. run) in an integrated circuit manufacturing system configures the system to manufacture a data processing system configured to perform any of the methods described herein, or to manufacture a data processing system comprising any apparatus described herein. An integrated circuit definition dataset may be, for example, an integrated circuit description.
Therefore, there may be provided a method of manufacturing, at an integrated circuit manufacturing system, a data processing system as described herein. Furthermore, there may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, causes the method of manufacturing a data processing system to be performed.
An integrated circuit definition dataset may be in the form of computer code, for example as a netlist, code for configuring a programmable chip, as a hardware description language defining hardware suitable for manufacture in an integrated circuit at any level, including as register transfer level (RTL) code, as high-level circuit representations such as Verilog or VHDL, and as low-level circuit representations such as OASIS (RTM) and GDSII. Higher level representations which logically define hardware suitable for manufacture in an integrated circuit (such as RTL) may be processed at a computer system configured for generating a manufacturing definition of an integrated circuit in the context of a software environment comprising definitions of circuit elements and rules for combining those elements in order to generate the manufacturing definition of an integrated circuit so defined by the representation. As is typically the case with software executing at a computer system so as to define a machine, one or more intermediate user steps (e.g. providing commands, variables etc.) may be required in order for a computer system configured for generating a manufacturing definition of an integrated circuit to execute code defining an integrated circuit so as to generate the manufacturing definition of that integrated circuit.
An example of processing an integrated circuit definition dataset at an integrated circuit manufacturing system so as to configure the system to manufacture a data processing system will now be described with respect to
The layout processing system 1004 is configured to receive and process the IC definition dataset to determine a circuit layout. Methods of determining a circuit layout from an IC definition dataset are known in the art, and for example may involve synthesising RTL code to determine a gate level representation of a circuit to be generated, e.g. in terms of logical components (e.g. NAND, NOR, AND, OR, MUX and FLIP-FLOP components). A circuit layout can be determined from the gate level representation of the circuit by determining positional information for the logical components. This may be done automatically or with user involvement in order to optimise the circuit layout. When the layout processing system 1004 has determined the circuit layout it may output a circuit layout definition to the IC generation system 1006. A circuit layout definition may be, for example, a circuit layout description.
The IC generation system 1006 generates an IC according to the circuit layout definition, as is known in the art. For example, the IC generation system 1006 may implement a semiconductor device fabrication process to generate the IC, which may involve a multiple-step sequence of photo lithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of semiconducting material. The circuit layout definition may be in the form of a mask which can be used in a lithographic process for generating an IC according to the circuit definition. Alternatively, the circuit layout definition provided to the IC generation system 1006 may be in the form of computer-readable code which the IC generation system 1006 can use to form a suitable mask for use in generating an IC.
The different processes performed by the IC manufacturing system 1002 may be implemented all in one location, e.g. by one party. Alternatively, the IC manufacturing system 1002 may be a distributed system such that some of the processes may be performed at different locations, and may be performed by different parties. For example, some of the stages of: (i) synthesising RTL code representing the IC definition dataset to form a gate level representation of a circuit to be generated, (ii) generating a circuit layout based on the gate level representation, (iii) forming a mask in accordance with the circuit layout, and (iv) fabricating an integrated circuit using the mask, may be performed in different locations and/or by different parties.
In other examples, processing of the integrated circuit definition dataset at an integrated circuit manufacturing system may configure the system to manufacture a data processing system without the IC definition dataset being processed so as to determine a circuit layout. For instance, an integrated circuit definition dataset may define the configuration of a reconfigurable processor, such as an FPGA, and the processing of that dataset may configure an IC manufacturing system to generate a reconfigurable processor having that defined configuration (e.g. by loading configuration data to the FPGA).
In some embodiments, an integrated circuit manufacturing definition dataset, when processed in an integrated circuit manufacturing system, may cause an integrated circuit manufacturing system to generate a device as described herein. For example, the configuration of an integrated circuit manufacturing system in the manner described above with respect to
In some examples, an integrated circuit definition dataset could include software which runs on hardware defined at the dataset or in combination with hardware defined at the dataset. In the example shown in
The implementation of concepts set forth in this application in devices, apparatus, modules, and/or systems (as well as in methods implemented herein) may give rise to performance improvements when compared with known implementations. The performance improvements may include one or more of increased computational performance, reduced latency, increased throughput, and/or reduced power consumption. During manufacture of such devices, apparatus, modules, and systems (e.g. in integrated circuits) performance improvements can be traded-off against the physical implementation, thereby improving the method of manufacture. For example, a performance improvement may be traded against layout area, thereby matching the performance of a known implementation but using less silicon. This may be done, for example, by reusing functional blocks in a serialised fashion or sharing functional blocks between elements of the devices, apparatus, modules and/or systems. Conversely, concepts set forth in this application that give rise to improvements in the physical implementation of the devices, apparatus, modules, and systems (such as reduced silicon area) may be traded for improved performance. This may be done, for example, by manufacturing multiple instances of a module within a predefined area budget.
The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2102728.9 | Feb 2021 | GB | national |
