Patent Application
20090327562
The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing bus interface calibration to improve bus interface initialization time in a processor system.
To boot a system, often each bit/wire of a bus interface needs to be calibrated, for both transmit and receive paths. The bus interface connects, for example, a processor chip to another processor chip, a memory module to a memory controller or a processor, a memory controller to another memory controller, or the like.
In general from a high level, the calibration technique for the bus interface includes writing known patterns and adjusting the clock to the ideal location relative to data, or alternatively adjusting the data with respect to the clock. As the clock or data is adjusted the known pattern will either pass or fail.
The ideal location for the clock is essentially the center of a data eye where the known pattern transitions from failing to pass and the pattern transitions from passing to failing. This method of finding the ideal location or phase is a time consuming process of moving the clock relative to data, or moving the data relative the clock, while observing the known data pattern.
Many systems, such as a system using an extreme data rate dynamic random access memory (XDR DRAM) or Rambus memory, the calibration must be performed every time the system is booted. A rigid training process is followed without implementing any potential for quickly booting. The time consuming process limits applications for the use of many systems.
A need exists for an effective mechanism for implementing bus interface calibration to improve bus interface initialization time in a processor system.
A principal aspect of the present invention is to provide a method and apparatus for implementing bus interface calibration to improve bus interface initialization time in a processor system. Other important aspects of the present invention are to provide such method and apparatus for implementing bus interface calibration to improve bus interface initialization time in a processor system substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for implementing bus interface calibration to improve bus interface initialization time in a processor system. Bus interface calibration is performed using saved calibration values as a seed and average calibration values are saved. At bus interface initialization time, checking for saved calibration values is performed. The saved calibration values are loaded and tested. When the saved calibration values pass the test, then the saved calibration values are used for system operation without performing any training steps.
In accordance with features of the invention, a processor unit performing the test of the saved calibration values detects a pattern that does not work, then a bus interface calibration using the current saved calibration values is performed and new average calibration values are saved. The new saved average calibration values are used at a next system boot.
In accordance with features of the invention, once a system has booted, responsive to identifying a predefined event, the bus interface is placed in an auto-calibration mode and bus interface calibration is performed to adjust clock settings to actual ideal while the system is up and running. The predefined event includes, for example, a detected data error on the bus, a periodic event, changing environmental conditions, such as when the device temperature has increased by a set value of 5° C., a threshold system activity level such as a low-activity period, a system call, and a user call.
In accordance with features of the invention, after booting the system, any delta from the original average calibration values are recomputed and stored into the average calibrations values. The stored average calibration values include an average calibration value for a center of a data eye, and respective average maximum and minimum calibration values for opposite sides of the data eye. The average calibration values are saved with corresponding environmental conditions, such as driver and receiver voltages and temperatures. The average calibration values are saved in nonvolatile system memory.
The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
In accordance with features of the invention, a method is provided that implements optimized bus interface calibration to improve bus interface initialization time in a processor system. For example, the method provides substantial performance improvement in a system using extreme data rate dynamic random access memory (XDR DRAM) or Rambus memory. The method finds an average solution over many calibrations and uses the running-average solution to allow a system to boot quickly. A major advantage to this solution is that a system with near ideal bus interface calibrations data can be developed based upon an average without going through the time consuming process of actually training the bus interface.
In accordance with features of the invention, the method allows a system to utilize previously discovered bus interface calibration values or a function of those calibration values. The history of the bus interface calibrations has sufficient margin relative to the ideal settings in order to eliminate the need to calibrate each bit on every power up.
Referring now to the drawings, in
System 100 includes a memory 112, such as a nonvolatile random access memory (NVRAM) 112. Computer system 100 includes an operating system 114, a bus interface calibration control program 116 of the preferred embodiment, and a plurality of converged calibration values 118 of the preferred embodiment resident in the memory 112.
Computer test system 100 is shown in simplified form sufficient for understanding the present invention. The illustrated computer test system 100 is not intended to imply architectural or functional limitations. The present invention can be used with various hardware implementations and systems and various other internal hardware devices.
Referring now to
In accordance with features of the invention, the method allows using stored average calibration values to be used as the calibration information or phase data to boot the system 100.
In accordance with features of the invention, the method tests the opposite minimum and maximum edges of the data eye to verify the stored calibration settings. Although this testing costs time, additionally robustness for the method of the preferred embodiment is gained.
Referring now to
Checking whether the phase calibration value passes is performed as indicated at a decision block 204. If the phase calibration value fails, then a calibration is performed with the prior calibration values used as seed as indicated at a block 206.
In accordance with features of the invention, the method provides a history of successful configuration set points and the corresponding environmental conditions including driver and receiver voltages and temperatures in a large four-dimensional space for those set points so that, the next intelligently selected initial setpoints advantageously are calculated as a function of the present environmental conditions.
Then new average Phase, Max FP_Phase, and Min PF_Phase calibration values identified from the calibration process at block 206 are learned and stored for the next bus interface initialization or boot of the system 100 as indicated at a block 208.
The new average Phase, Max FP_Phase, and Min PF_Phase calibration values are saved with corresponding environmental conditions (e.g., driver and receiver voltages and temperatures at block 208. The Max FP_Phase, and Min PF_Phase calibration values represent respective opposite sides of the data eye. This completes the bus interface calibration process as indicated at a block 210.
Otherwise if the phase calibration value passes, then the stored FP_Phase is loaded and tested as the phase calibration value as indicated at a block 212. Checking whether the phase calibration value FP_Phase passes is performed as indicated at a decision block 214. If the phase calibration value fails, then the calibration is performed at block 206 and continues as described above.
If the phase calibration value FP_Phase passes, then checking the phase calibration value PF_Phase is loaded and tested as the phase calibration value as indicated at a block 216. Checking whether the phase calibration value PF_Phase passes is performed as indicated at a decision block 218. If the phase calibration value fails, then the calibration is performed at block 206 and continues as described above.
If the phase calibration value PF_Phase passes, then the phase calibration values Phase, PF_Phase, and FP_Phase are reloaded and the system 100 is ready for normal operations as indicated at a block 220. This completes the bus interface calibration process at block 210.
In accordance with features of the invention, the method enables that once the system 100 is running, the bus interface 106 can be placed in an auto-calibration mode to allow bus interface 106 to adjust its clock settings to actual ideal while the system is up and running. Then any delta from the original average calibration values are recomputed into the average calibrations settings and stored, for example, in nonvolatile random access memory (NVRAM) 112 or other system nonvolatile memory of system 100.
In accordance with features of the invention, the method enables building an autonomic database each time the interface re-calibrates itself, by storing the optimal setpoint conditions in conjunction to the environmental conditions. This enables novel pro-active use of the historical set points based upon their associated environmental conditions. Conversely, if the environmental conditions have not changed significantly, then a periodic re-calibration event advantageously is ignored to increase system availability and performance.
In accordance with features of the invention, the combination of valid setpoints and environmental conditions advantageously is used preemptively to initiate a new re-calibration event in response to a detected error, or a changing environmental conditions. Pre-emptive in that, if the device temperature has increased by, for example, 5° C., this indicates that the bus needs to be re-calibrated now, and should begin re-calibration using initial values (that may be optimal based on learned history) at a given set point. Another embodiment of pre-emptive calibrations is provided responsive to monitoring system activity, and the periodic re-calibration sequence is initiated during a low-activity period. A third preemptive re-calibration is initiated from a system, or user call. The pre-emptive methodologies yield higher performance and more reliability enabling to keep the bus optimally performing, rather than passively waiting for some preset period.
Referring now to
Referring now to
When the prior calibration data is not operational, then as indicated at a block 406 the configuration is reset to use saved calibration values as seed as described above. Next trial values are obtained as indicated at a block 408. The current values are tested as indicated at a block 410. Checking for a sufficient number of trials is performed as indicated at a decision block 412. When a sufficient number of trials is not identified, then new trial values are obtained as indicated at a block 408, and the steps are repeated as described above.
When a sufficient number of trials is identified, then checking whether the trials converge is performed as indicated at a decision block 414. When the trials do not converge, then new trial values are obtained as indicated at a block 408, and the steps are repeated as described above. Otherwise when the trials converge, then the converged calibration values are saved as indicated at a block 416. This completes the training at block 404.
Referring now to
A sequence of program instructions or a logical assembly of one or more interrelated modules defined by the recorded program means 504, 506, 508, 510, direct the system 100 for implementing bus interface calibration of the preferred embodiment.
While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
