Implementing large multipliers in a programmable integrated circuit device

Abstract

A specialized processing block is configurable as one ternary linear decomposition or two binary linear decompositions to perform large multiplications using smaller multipliers, and includes a first number of multiplier circuits of a first size, a second number of pre-adders, and a third number of block inputs. The block inputs are connected to a first subset of the multiplier circuits, and to the pre-adders which are connected to a second subset of the multiplier circuits. There is also a fourth number of additional inputs. A plurality of shifters shift partial product outputs of each of the multipliers by various shift amounts. A joint adder structure combines the shifted partial products. Controllable elements controllably select between different configurations of inputs to the multipliers and pre-adders, controllably connect and disconnect certain ones of the shifted partial products, and selectively split the joint adder structure into two smaller adder structures.

Description

BACKGROUND OF THE INVENTION

This invention relates to implementing large multiplication operations in programmable integrated circuit devices such as, e.g., programmable logic devices (PLDs).

As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.

One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.

For example, PLDs sold by Altera Corporation, of San Jose, Calif., as part of the STRATIX® family, include DSP blocks, each of which may include four 18-by-18 multipliers. Each of those DSP blocks also may include adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-by-18 multipliers, but also as four smaller multipliers, or as one larger (36-by-36) multiplier. In addition, one 18-by-18 complex multiplication (which decomposes into two 18-by-18 multiplication operations for each of the real and imaginary parts) can be performed.

Larger multiplications can be performed by using more of the 18-by-18 multipliers—e.g., from other DSP blocks. For example, a 54-by-54 multiplier can be decomposed, by linear decomposition, into a 36-by-36 multiplier (which uses the four 18-by-18 multipliers of one DSP block), two 36-by-18 multipliers (each of which uses two 18-by-18 multipliers, for a total of four additional 18-by-18 multipliers, consuming another DSP block), and one 18-by-18 multiplier, consuming a portion of a third DSP block. Thus, using 18-by-18 multipliers, nine multipliers are required to perform a 54-by-54 multiplication. Similarly, as noted above, using 18-by-18 multipliers, four multipliers are required to perform a 36-by-36 multiplication

SUMMARY OF THE INVENTION

The present invention reduces the number of multipliers of a particular size that are required to perform a multiplication larger than that size. In the example of a 54-by-54 multiplication, the number of 18-by-18 multipliers required may be reduced from nine to six by using a ternary decomposition. As discussed in more detail below, each 54-bit number is split into three 18-bit numbers. Before multiplication, the 18-bit numbers are added in six different combinations. These combinations are multiplied to produce three terms, and six of the 18-bit numbers are multiplied to produce three terms, for a total of six unique terms. These 6 unique terms are added, with twelve different offsets, to generate the 108-bit product. Although the additional adders required add to the required device area for this computation, the decomposition reduces the number of multipliers required, which are even more area-intensive. And bit is well-suited for a programmable integrated circuit device, where the entire operation can occur in a relatively small number of clock cycles.

In such an implementation, while only six multipliers are required, additional adders may be required. In addition, in at least one embodiment, at least one of the multipliers may be required to handle an additional bit in each input; thus, in the 18-by-18 example given above, at least one of the multiplications may be a 19-by-19 multiplication. 19-by-19 multipliers may be provided, or an “extension” of each multiplication may be provided, by appropriately configuring available programmable logic.

Similarly, in the example of a 36-by-36 multiplication, the number of 18-by-18 multipliers required may be reduced from four to three. This may be achieved by using a binary decomposition rather than a ternary decomposition.

According to a further aspect of the present invention, a specialized processing block including six 18-by-18 multipliers and circuitry for adding the outputs of those multipliers may be used to perform, using a ternary decomposition, a 54-by-54 multiplication, or may be partitioned into two half-blocks having three multipliers, to perform, using binary decomposition, two 36-by-36 multiplications.

Therefore, in accordance with the present invention, there is provided a specialized processing block for performing multiplication operations in a programmable integrated circuit device. The specialized processing block includes a first number of multiplier circuits of a first size, a second number of pre-adders, and a third number of block inputs. Respective pairs of the block inputs are connected to respective ones of a first subset of the multiplier circuits. The respective pairs of the block inputs are also combined in the pre-adders and then input to a second subset of the multiplier circuits. There also is a fourth number of additional inputs. A first set of controllable elements controllably select between the additional inputs, and outputs of some of the pre-adders, for input to one of the multipliers, and also controllably select between the additional inputs, and some of the block inputs, for input to some of the pre-adders. A plurality of shifters shift partial product outputs of each of the multipliers by one or more shift amounts to provide one or more shifted partial product outputs from each of the multipliers. A joint adder structure combines the shifted partial product outputs of the multipliers. A second set of controllable elements controllably connects and disconnects certain ones of the shifted partial products to or from the joint adder structure. A third controllable element selectively splits the joint adder structure into two smaller adder structures.

A method for configuring such a programmable device, and a machine-readable data storage medium encoded with software for performing the method, are also provided.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIGS. 1A and 1B (hereinafter collectively referred to as FIG. 1) are a diagram of the logic flow, and a circuit configuration with which a programmable device may be programmed, for performing multiplication in accordance with an embodiment of the disclosure;

FIG. 2 is a diagram of the logic flow, and a circuit configuration with which a programmable device may be programmed, for a multiplier extension in accordance with an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a specialized processing block that may be incorporated in a programmable device, and which is particularly well-suited to implement an embodiment of the invention;

FIG. 4 is a schematic diagram of the specialized processing block of FIG. 3 configured according to an embodiment of the invention to implement a single multiplication operation of a first size;

FIG. 5 is a schematic diagram of the specialized processing block of FIG. 3 configured according to an embodiment of the invention to implement two multiplication operations of a second size smaller than the first size;

FIG. 6 shows an alignment pattern for partial products in the implementation of FIG. 5;

FIG. 7 shows an alignment pattern for partial products in the implementation of FIG. 4;

FIG. 8 shows further detail of the alignment pattern of FIG. 7;

FIG. 9 shows an arrangement of compressors and carry-propagate adders that may be used in an implementation such as that of FIG. 4;

FIG. 10 is a cross-sectional view of a magnetic data storage medium encoded with a set of machine-executable instructions for performing the method according to the present invention;

FIG. 11 is a cross-sectional view of an optically readable data storage medium encoded with a set of machine executable instructions for performing the method according to the present invention; and

FIG. 12 is a simplified block diagram of an illustrative system employing a programmable logic device incorporating the present invention.

DETAILED DESCRIPTION OF THE INVENTION

When a 54-by-54 multiplication (e.g., for double-precision floating-point operations) is implemented in 18-by-18 multipliers using a ternary linear decomposition, each of the two 54-bit operands a and b can be expressed as a set of 18-bit numbers a₂:a₁:a₀ and b₂:b₁:b₀, so that their product can be represented as follows:(2^2x+a₂+2^xa₁+a₀)*(2^2x+b₂+2^xb₁+b₀)The power-of-2 factors represent left-shifting by a number of places equal to the exponent. Expanding, the 54-by-54 multiplication is:2^4xa₂b₂+2^3xa₂b₁+2^2xa₂b₀+2^3xa₁b₂+2^2xa₁b₁+2^xa₁b₀+2^2xa₀b₂+2^xa₁b₁+a₀b₀ There are nine unique terms a_nb_m, so nine multipliers are required.

Instead, however, the 18-bit components a_n, b_m can be combined as follows:A:(a₂+a₁)*(b₂+b₁)=a₂b₂+a₂b₁+a₁b₂+a₁b₁ B:(a₁+a₀)*(b₁+b₀)=a₁b₁+a₁b₀+a₀b₁+a₀b₀ C:(a₂+a₀)*(b₂+b₀)=a₂b₂+a₂b₀+a₀b₂+a₀b₀ Grouping terms from the linear decomposition:2^4xa₂b₂+2^3x(a₂b₁+a₁b₂)+2^2x(a₂b₀+a₀b₂)+2^x(a₁b₀+a₁b₁)+a₀b₀

Substituting A, B, and C into these expressions:2^4xa₂b₂+2^3x(A−a₂b₁+a₁b₁)+2^2x(C−a₂b₂−a₀b₀+a₁b₁)+2^x(B−a₂b₂−a₀b₀)+a₀b₀

In this formulation of the computation, there are only six unique terms A, B, C and a_nb_m (n=0, 1, 2), but a total of twelve terms. By comparison, the linear decomposition includes nine unique terms a_nb_m (n=0, 1, 2; m=0, 1, 2), constituting nine total terms. Therefore, it is possible to trade off multipliers (specific and expensive) for adders (general purpose and inexpensive).

Each term A, B, C is a product of two terms (a_n+a_m) and (b_p+b_q), each of which is the sum of two 18-bit numbers and is therefore 19-bits wide. Thus, computing A, B or C requires a 19-by-19 multiplier. These multipliers may be provided on the device, or a 19-by-19 multiplication may be performed by “extending” an 18-by-18 multiplier using three AND gates and an adder, as described below. 18-by-19 multipliers are provided in the STRATIX® V FPGA available from Altera Corporation, and such multipliers also may be extended for 19-by-19 operations.

As noted above, according to a further aspect of the present invention, a specialized processing block including six 18-by-18 multipliers (extendable as discussed above, and further discussed below), and circuitry for adding the outputs of those multipliers, may be particularly well-suited for implementing this computation which, as mentioned above, includes six unique terms. Pre-adders for preprocessing of the inputs also may be included in the specialized processing block.

In addition, it sometimes is necessary or desired to perform a 36-by-36 multiplication (e.g., for single-precision floating-point operations), which normally requires four 18-by-18 multipliers. However, such a multiplication also may be implemented using a binary decomposition, in which each of the two 36-bit operands a and b can be expressed as a set of 18-bit numbers a₁:a₀ and b₁:b₀. It can readily be established that such a decomposed operation can be implemented using three 18-by-18 multipliers rather than the four 18-by-18 multipliers otherwise required. This type of decomposition, and recursive extensions thereof, is referred to as a “Karatsuba decomposition.” Higher-order versions of this decomposition, such as the ternary decomposition described above, are sometimes referred to as “Karatsuba-like.” However, for ease of description, both binary and higher-order decompositions of this type will be described as “Karatsuba decompositions.”

Because a ternary Karatsuba decomposition uses six multipliers while a binary Karatsuba decomposition uses three multipliers, in accordance with a still further aspect of the present invention the aforementioned six-multiplier specialized processing block (which is capable of performing a ternary Karatsuba decomposition) may be partitioned into two sub-blocks, each containing three 18-by-18 multipliers (and each therefore able to perform a respective 36-by-36 multiplication using a binary Karatsuba decomposition).

As discussed further below, the partitioning of the larger six-multiplier specialized processing block may be achieved by providing programmable elements, such as multiplexers and AND gates (although other programmable elements also may be used), to make or break certain connections as described below.

The invention will now be described with reference to FIGS. 1-9.

FIG. 1 is a diagram 100 of examples of both the logic flow, and an embodiment of a circuit configuration, with which a programmable device, such a CYCLONE® FPGA from Altera Corporation (having 18-by-18 multipliers), may be programmed, for multiplying a first 54-bit number a by second 54-bit number b. Inputs or input registers 101-106 represent the six 18-bit components a₂[a53:36], a₁[a35:18], a₀[a17:0], b₂[b53:36], b₁[b35:18], b₀[b17:0] of a and b. Each of registers 101-106 feeds one of 18-by-18 multipliers 111, 112, 113 which produce, respectively, the three terms a_nb_m (n=0, 1, 2) discussed above.

The output of multiplier 111 is shifted by 72-bit left-shifter 1111 representing the 2^4x factor above, by 54-bit left-shifter 1112 representing the 2^3x factor above, and by 36-bit left-shifter 1113 representing the 2^2x factor above. The output of multiplier 112 is shifted by 54-bit left-shifter 1122 representing the 2^3x factor above, by 36-bit left-shifter 1121 representing the 2^2x factor above, and by 18-bit left-shifter 1123 representing the 2^x factor above. The output of multiplier 113 is shifted by 36-bit left-shifter 1132 representing the 2^2x factor above, by 18-bit left-shifter 1133 representing the 2^x factor above, and by 0-bit left-shifter 1131 (which could be omitted).

Each of registers 101-106 also feeds appropriate ones of adders 114, 115, 116, 117, 118, 119, each of which provides one of terms (a_n+a_m) or (b_p+b_q) as described above for input to 19-by-19 multipliers 121, 122, 123 that compute A, B and C. Each 19-by-19 multiplier 121, 122, 123 includes a respective 18-by-18 multiplier 131, 132, 133, that operates on the lower 18 bits of the adder outputs (designated in the drawing as AA, BB and CC because they compute only a portion of A, B or C), plus an extension block 134.

The output 1310 of multiplier 131 of multiplier 121 is shifted by 54-bit left-shifter 1311 representing the 2^3x factor above. The extension process requires an additional 18-bit shift, so the output 1341 of extension block 134 of multiplier 121 is shifted by 72-bit left-shifter 1312 representing the 2^3x factor and the additional 18 bits. The output 1320 of multiplier 132 of multiplier 122 is shifted by 36-bit left-shifter 1321 representing the 2^2x factor above. The output 1342 of extension block 134 of multiplier 122 is shifted by 54-bit left-shifter 1322 representing the 2^2x factor and the additional 18 bits. The output 1330 of multiplier 133 of multiplier 123 is shifted by 18-bit left-shifter 1331 representing the 2^x factor above. The output 1343 of extension block 134 of multiplier 123 is shifted by 72-bit left-shifter 1332 representing the 2^x factor and the additional 18 bits.

The various shifter outputs are summed as shown by summers 141, 142, and sum 1420 is subtracted from sum 1410 at 143, as shown to provide the final 108-bit result 1430.

The aforementioned extension process works as follows:

If the two 19-bit inputs are referred to as “x” and “y,” then if the 19th or most-significant bit (MSB) of x (x[18]) is “1”, then the 18 least-significant bits of y (y[17:0]), left shifted by 18 bits, should be added to the product xy[35:0]. If the MSB (19th bit) of y (y[18]) is “1,” then the 18 least-significant bits of x (x[17:0]), left shifted by 18 bits, should be added the product xy[35:0]. The logical AND of the two MSBs (x[18] and y[18]), left shifted by 36 bits, also should be added the product xy[35:0]. These additions occur in summers 141, 142.

FIG. 2 shows both the logic flow, and an embodiment of a circuit configuration with which a programmable device may be programmed, for extension block 134 that performs the extension process. Inputs 21, 22 hold the 19-bit inputs X and Y, broken down into a most-significant bit X[18] or Y[18] and 18 least-significant bits X[17:0] or Y[17:0].

AND-gate 23 combines the X[18] bit and the Y[17:0] bits to implement the aforementioned addition of Y[17:0] when X[18] is “1”. AND-gate 24 combines the Y[18] bit and the X[17:0] bits to implement the aforementioned addition of X[17:0] when Y[18] is “1”. AND-gate 25 combines the X[18] bit and the Y[18] bit, and that result is concatenated at 26 with 18 0's, to implement the aforementioned logical ANDing of the two MSBs, and 18 bits of the aforementioned 36-bit shifting of that logical AND result. These three results are then summed at 27.

Although multiplication operations in accordance with the invention have been described thus far in terms of a 54-by-54 multiplication being broken down into a number of 18-by-18 multiplications, the present invention can be used to break down any large multiplication by breaking the inputs down into smaller segments. Thus, a 48-by-48 multiplication can be broken down into a number of 16-by-16 multiplications by breaking the inputs into three 16-bit segments. The number of multipliers needed will be equal to the number of terms—e.g., two numbers each broken into three segments will require six multipliers (plus three extension blocks)—instead of the square of the number of terms. And if the segments are smaller than 18-by-18, where 18-by-18 multipliers are available, then no extension blocks would be required.

FIG. 3 shows an embodiment of a six-multiplier specialized processing block 300, as discussed above, that may be used to implement another embodiment of a logical configuration to carry out a 54-by-54 multiplication (e.g., for double-precision operations), and that may be partitioned into two three-multiplier sub-blocks that may carry out respective 36-by-36 multiplications (e.g., for single-precision operations). And as discussed in the preceding paragraph, multiplications of other sizes may be implemented if the individual multipliers of specialized processing block 300 are of a size other than 18-by-18.

In specialized processing block 300, the foregoing first, second and third numbers are six and the fourth number is two, so that specialized processing block 300 has eight inputs 301, six pre-adders 312, 322, 332, 342, 352 and 362 (collectively referred to as 302), and six multipliers 313, 323, 333, 343, 353 and 363 (collectively referred to as 303) which may, as noted above, be 18-by-18 multipliers and may further be extendable as discussed. Various shifters 317, 327, 337, 347, 357, 367, 377, 387, 388, 389, 397 and 398 (collectively referred to as 307) are applied to the outputs of multipliers 303. The indicated shifts are denoted in numbers of words (e.g., numbers of groups of 18 bits in a case where the multipliers 303 are 18-by-18 multipliers), and align the multiplier outputs as discussed below in connection with FIGS. 6 and 7. The aligned multiplier outputs are combined by a joint adder structure, including structures such as compressors that perform addition operations without carries, and structures such as carry-propagate adders that perform addition operations with carries. The joint adder structure is indicated collectively at 304.

Multiplexers 305/315/325/335 and AND gates 306/316/326/336/346 may be provided to programmably select between the full specialized processing block 300 for use, e.g., in a 54-by-54 multiplication as described, and the partitioned specialized processing block 300, divided into the aforementioned sub-blocks, for use, e.g., in two 36-by-36 multiplications as described. Multiplexers 305/315/325/335 control the routing of inputs 301 to pre-adders 302, while one AND gate 306 partitions the joint compressor/carry-propagate adder structure 304 into two smaller compressor/carry-propagate adder structures 314/324, and the remaining AND gates 316/326/336/346 determine whether or not certain shifted multiplier outputs are routed to the compressor/carry-propagate adder structures 304/314/324.

FIG. 4 shows one implementation 400 in which specialized processing block 300 may be configured by multiplexers 305/315/325/335 and AND gates 306/316/326/336/346 as a single block for a 54-by-54 multiplication {a₃:a₁:a₀}*{b₃:b₁:b₀}. Multiplexer 305 selects input a₁ rather than input a₂ for pre-adder 312, and multiplexer 315 selects input b₁ rather than input b₂ for pre-adder 312. Multiplexers 325 and 335 select the outputs of pre-adders 332 and 342, rather than inputs a₂ and b₂, as the inputs of multiplier 333. Similarly, AND gate 306 is turned ON to maintain compressor/carry-propagate adder structures 314/324 as a single larger compressor/carry-propagate adder structure 304, and AND gates 316, 336 and 346 are turned ON to connect the outputs of shifters 337, 387 and 397 to compressor/carry-propagate adder structure 304 while AND gate 326 is turned OFF to disconnect the output of shifter 357 from compressor/carry-propagate adder structure 304.

FIG. 5 shows one implementation 500 in which specialized processing block 300 may be configured by multiplexers 305/315/325/335 and AND gates 306/316/326/336/346 as two sub-blocks 501/502 for performing two 36-by-36 multiplications {a₃:a₂}*{b₃:b₂} and {a₁:a₀}*{b₁:b₀}. Multiplexer 305 selects input a₂ rather than input a₁ for pre-adder 312, and multiplexer 315 selects input b₂ rather than input b₁ for pre-adder 312. Multiplexers 325 and 335 select inputs a₂ and b₂, rather than the outputs of pre-adders 322 and 332, as the inputs of multiplier 333. Similarly, AND gate 306 is turned OFF to maintain compressor/carry-propagate adder structures 314/324 as separate structures, and AND gates 316, 336 and 346 are turned OFF to connect the outputs of shifters 337, 387 and 397 from compressor/carry-propagate adder structures 314/324, while AND gate 326 is turned ON to connect the output of shifter 357 to compressor/carry-propagate adder structure 324.

The differences between the input, pre-adder and multiplier pattern of implementation 400 of FIG. 4, and the input, pre-adder and multiplier pattern of implementation 500 of FIG. 5, are that in implementation 500:

a. There are two additional 18-bit inputs (a₂ and b₂). These inputs (a₂ and b₂) feed multiplier 333, bypassing pre-adders 332/342;

b. Inputs a₂ and b₂ also feed the right inputs of pre-adders 312/322.

These input, pre-adder and multiplier pattern differences account for multiplexers 305/315/325/335.

The differences between the shift pattern into the compressor/carry-propagate adder structure of implementation 400 of FIG. 4, and the shift pattern into the compressor/carry-propagate adder structure of implementation 500 of FIG. 5, are that in implementation 500:

a. 2-word shifter 337 is not used;

b. Additional 3-word shifter 357 is used (multiplier 333 is 19-by-19, so this requires a 38-bit AND-gate 326).

c. 3-word shifter 387 is not used (this saves a 38-bit AND-gate 336); alternatively, shifter 387 could be multiplexed between outputs of multiplier 333 (for 36-by-36 mode) and multiplier 353 (for 54-by-54 mode);

d. 2-word shifter 397 is not used (this saves a 36-bit AND gate 346).

Remembering that specialized processing block 300 is a single block regardless of whether implementation 400 or implementation 500 is in use, and considering the rightmost end as drawn to be the least significant bit, the reason for the different shifting patterns of the two implementations becomes clear. There are thirteen possible inputs to compressor/carry-propagate adder structure 304, including the twelve inputs that pass through one of the twelve shifters 317, 327, 337, 347, 357, 367, 377, 387, 388, 389, 397 and 398, as well as one input on lead 399 which may be considered a zero shift.

If one considers the two sub-blocks 501, 502 of FIG. 5, they should be functionally identical, because each is performing a binary decomposition. But because the inputs are all aligned to the least significant bit of the overall block 500, which is in sub-block 502. Therefore all of the shifts in sub-block 501 have to result in the same relative shifts of the values in sub-block 501 as are performed on the values in sub-block 502, but also are offset beyond all of the bits of the values in sub-block 502.

This is shown in FIG. 6, which shows an alignment pattern 651 that is implemented in compressor/carry-propagate adder structure 314 of block 501, and an alignment pattern 652 that is implemented in compressor/carry-propagate adder structure 324 of block 502, for the separate 36-by-36 multiplications. As can be seen, the shifting pattern of the aligned values in pattern 651 is the same as the shifting pattern of the aligned values in pattern 652, except that pattern 651 is offset by two word lengths from pattern 652. Each pattern 651/652 includes five values shifted by various amounts, for a total of ten shifted values, corresponding to the thirteen possible values, less three values disconnected by turning OFF AND-gates 316/336/346. Each results in a compressed output including respective sum vectors 653/663 and respective carry vectors 654/664, which are separately combined (not shown) in respective separate carry-propagate adders.

In comparison, FIG. 7 shows the alignment pattern 751 used for the 54-by-54 multiplication. As seen, twelve of the thirteen possible shifted values are used, reflecting the turning OFF of AND-gate 326.

As seen in FIG. 8, the same structures 651/652 that produce the two separate results for the parallel 36-by-36 multiplications can be used for the 54-by-54 multiplication. Because in the 54-by-54 case, AND-gate 336 is turned ON while AND-gate 326 is turned OFF, shifted value 387 is used while shifted value 357 is not, which is the opposite of the situation in the 36-by-36 case. Both shifted values 357/387 are shifted by three words, so value 387 can replace value 357 in pattern 651. Indeed, because only one of values 357/387 is used at any one time, instead of two AND-gates 326/336 to turn values 357/387 ON and OFF, a single multiplexer can be provided (not shown) to select between the two values.

The two resulting sum and carry vector pairs 653/654 and 663/664, can be overlapped as shown at 801, and further combined with shifted values 337 and 397 (provided by turning ON AND-gates 316 and 346 which are turned OFF for the 36-by-36 case) using two overlapping carry-propagate adders as shown at 802, providing the result shown in FIG. 7. Thus, all shifted values for the 54-by-54 case are accounted for.

FIG. 9 shows how the sum and carry vector pairs 653/654 and 663/664 are combined in the two cases (36-by-36 and 54-by-54). As seen each sum vector S1 and S2 (663/653) and each carry vector C1 and C2 (664/654) is 72 bits wide. As also seen, the combination (e.g., using a small carry-propagate adder (not shown)) of partial product values 337 and 397 results in two product vectors P1 and P2 (951/952). Those six vectors, P1, P2, C1, C2, S1 and S2, are input to a 6:2 compressor 953 which provides a compressed carry vector CC (963) and a compressed save vector CS (973). Alternatively, uncompressed carry and save vectors from values 337 and 397 can be input along with P1, P2, C1, C2, S1 and S2 to an 8:2 compressor (not shown).

Outputs 966/967 of carry-propagate adders 956/957 can be the separate 36-by-36 outputs in the 36-by-36 case, where sum vector S2 (653) and carry vector C2 (654) are input to carry-propagate adder 956 and sum vector S1 (663) and carry vector C1 (664) are input to carry-propagate adder 957. Alternatively, in the 54-by-54 case, the carry from the 36th bit of carry-propagate adder 956 is routed via AND-gate 958 to the carry input of carry-propagate adder 957. In the 54-by-54 case, C2 and S2, along with the lower 36 bits of each of CC and CS are input via 4:2 multiplexer 954 to carry-propagate adder 956, while C1 and S1, along with the upper 72 bits of each of CC and CS are input via 4:2 multiplexer 955 to carry-propagate adder 957. Other splits between carry-propagate adders 956 and 957 can be used, as long as a value is carried out from the most significant compressor input position of carry-propagate adder 956 and carried in to carry-propagate adder 957.

It should be noted that each of the shifter elements described above could be implemented as logic, or could include essentially only wires, with little or no additional logic required.

Thus it is seen that a block such as block 301 including a number of multipliers can be used to efficiently carry out either a ternary decomposition of a larger multiplication or two binary decompositions of two smaller multiplications (using half the number multipliers for each), using essentially the same partial product alignment pattern.

A method according to the invention configures a programmable integrated circuit device, such as a PLD, having such a block, to create the structures shown in FIGS. 4-9 to perform multiplications larger than the multipliers provided on the device, using a smaller number of multipliers than previous methods, by virtue of being able to perform the aforementioned decompositions.

Instructions for carrying out the method according to this invention may be encoded on a machine-readable medium, to be executed by a suitable computer or similar device to implement the method of the invention for programming or configuring programmable integrated circuit devices to perform operations as described above. For example, a personal computer may be equipped with an interface to which a programmable integrated circuit device can be connected, and the personal computer can be used by a user to program the programmable integrated circuit device using a suitable software tool, such as the QUARTUS® II software available from Altera Corporation, of San Jose, Calif.

FIG. 10 presents a cross section of a magnetic data storage medium 600 which can be encoded with a machine executable program that can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium 600 can be a floppy diskette or hard disk, or magnetic tape, having a suitable substrate 601, which may be conventional, and a suitable coating 602, which may be conventional, on one or both sides, containing magnetic domains (not visible) whose polarity or orientation can be altered magnetically. Except in the case where it is magnetic tape, medium 600 may also have an opening (not shown) for receiving the spindle of a disk drive or other data storage device.

The magnetic domains of coating 602 of medium 600 are polarized or oriented so as to encode, in manner which may be conventional, a machine-executable program, for execution by a programming system such as a personal computer or other computer or similar system, having a socket or peripheral attachment into which the PLD to be programmed may be inserted, to configure appropriate portions of the PLD, including its specialized processing blocks, if any, in accordance with the invention.

FIG. 11 shows a cross section of an optically-readable data storage medium 700 which also can be encoded with such a machine-executable program, which can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium 700 can be a conventional compact disk read only memory (CD-ROM) or digital video disk read only memory (DVD-ROM) or a rewriteable medium such as a CD-R, CD-RW, DVD-R, DVD-RW, DVD+R, DVD+RW, or DVD-RAM or a magneto-optical disk which is optically readable and magneto-optically rewriteable. Medium 700 preferably has a suitable substrate 701, which may be conventional, and a suitable coating 702, which may be conventional, usually on one or both sides of substrate 701.

In the case of a CD-based or DVD-based medium, as is well known, coating 702 is reflective and is impressed with a plurality of pits 703, arranged on one or more layers, to encode the machine-executable program. The arrangement of pits is read by reflecting laser light off the surface of coating 702. A protective coating 704, which preferably is substantially transparent, is provided on top of coating 702.

In the case of magneto-optical disk, as is well known, coating 702 has no pits 703, but has a plurality of magnetic domains whose polarity or orientation can be changed magnetically when heated above a certain temperature, as by a laser (not shown). The orientation of the domains can be read by measuring the polarization of laser light reflected from coating 702. The arrangement of the domains encodes the program as described above.

Thus it is seen that a method for efficiently carrying out large multiplications in a programmable integrated circuit device, a programmable integrated circuit device programmed to perform the method, and software for carrying out the programming, have been provided.

A PLD 90 programmed according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system 900 shown in FIG. 12. Data processing system 900 may include one or more of the following components: a processor 901; memory 902; I/O circuitry 903; and peripheral devices 904. These components are coupled together by a system bus 905 and are populated on a circuit board 906 which is contained in an end-user system 907.

System 900 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD 90 can be used to perform a variety of different logic functions.

For example, PLD 90 can be configured as a processor or controller that works in cooperation with processor 901. PLD 90 may also be used as an arbiter for arbitrating access to a shared resources in system 900. In yet another example, PLD 90 can be configured as an interface between processor 901 and one of the other components in system 900. It should be noted that system 900 is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims.

Various technologies can be used to implement PLDs 90 as described above and incorporating this invention.

It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.

For example, the various elements of this invention can be provided on a programmable integrated circuit device in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.

Claims

1. A specialized processing block for performing multiplication operations in a programmable integrated circuit device, said specialized processing block comprising: a first number of multiplier circuits of a first size;a second number of pre-adders;a third number of block inputs, respective pairs of said block inputs being connected to respective ones of a first subset of said multiplier circuits, said respective pairs of said block inputs also being combined in said pre-adders and then input to a second subset of said multiplier circuits;a fourth number of additional inputs;a first set of controllable elements that controllably select between said additional inputs, and outputs of some of said pre-adders, for input to one of said multipliers, and that controllably select between said additional inputs, and some of said block inputs, for input to some of said pre-adders;a plurality of shifters so that partial product outputs of each of said multipliers are shifted by one or more shift amounts to provide one or more shifted partial product outputs from each of said multipliers;a joint adder structure for combining said shifted partial product outputs of said multipliers;a second set of controllable elements that controllably connect and disconnect certain ones of said shifted partial products to or from said joint adder structure; anda third controllable element for selectively splitting said joint adder structure into two smaller adder structures; wherein:when said third controllable element is controlled to maintain said joint adder structure as one adder structure, said second set of controllable elements connects and disconnects said certain ones of said shifted partial products to support one ternary Karatsuba decomposition of one multiplication operation; andwhen said third controllable element is controlled to split said joint adder structure into said two smaller adder structures, said second set of controllable elements connects and disconnects said certain ones of said shifted partial products to support two separate binary Karatsuba decompositions of two multiplication operations using respective third and fourth subsets of said multipliers.

2. The specialized processing block of claim 1 wherein said joint adder structure comprises compressors that perform addition operations without carries and adders that perform addition operations with carries.

3. The specialized processing block of claim 1 wherein: said first number is six;each of said third and fourth subsets of said multipliers includes three of said multipliers;said ternary Karatsuba decomposition performs a multiplication operation that requires nine of said multipliers in the absence of ternary Karatsuba decomposition; andeach respective one of said first and second binary Karatsuba decompositions performs a respective multiplication operation that requires four of said multipliers in the absence of binary Karatsuba decomposition.

4. The specialized processing block of claim 3 wherein when said third controllable element is controlled to split said joint adder structure into said two smaller adder structures: said first set of controllable elements connects said third subset of said multipliers to one of said two smaller adder structures and connects said fourth subset of said multipliers to another of said two smaller adder structures;said third subset of said multipliers includes a first group of multipliers from said first and second subsets of said multipliers, and said fourth subset of said multipliers includes a second group of multipliers from said first and second subsets of said multipliers;said second set of controllable elements connects and disconnects said certain ones of said shifted partial products to support two separate binary Karatsuba decompositions of two multiplication operations;said third subset of said multipliers and said one of said two smaller adder structures performs a first one of said binary Karatsuba decompositions for a first multiplication operation; andsaid fourth subset of said multipliers and said another of said two smaller adder structures performs a second one of said binary Karatsuba decompositions for a second multiplication operation.

5. The specialized processing block of claim 1 wherein, when said third controllable element is controlled to split said joint adder structure into said two smaller adder structures, said first set of controllable elements selects said additional inputs for input to said one of said multipliers and for input to said some of said pre-adders.

6. The specialized processing block of claim 1 wherein said joint adder structure provides two identical but offset patterns for aligning and combining said shifted partial product outputs of said multipliers.

7. The specialized processing block of claim 6 wherein: when said third controllable element is controlled to maintain said joint adder structure as one adder structure:said first set of controllable elements controllably select said outputs of said some of said pre-adders for input to said one of said multipliers, and controllably select said some of said block inputs for input to said some of said pre-adders;said joint adder structure comprises a compressor that compresses combined shifted partial product outputs of said multipliers to provide compressed vectors;said joint adder structure further comprises first and second carry-propagate adders;a first less significant group of bits of each of said compressed vectors is input to one of said first and second carry-propagate adders;a second more significant group of bits of each of said compressed vectors is input to another of said first and second carry-propagate adders; andsaid third controllable element connects, as a carry input to said another of said first and second carry-propagate adders, a bit from said one of said first and second carry-propagate adders corresponding to a most significant bit of said first less significant group of bits.

8. The specialized processing block of claim 1 wherein: at least one of said multipliers is extended by 1 bit in each dimension beyond said first size.

9. A method of configuring a programmable integrated circuit device to performing multiplication operations, said programmable integrated circuit device including a specialized processing block, said specialized processing block comprising: a first number of multiplier circuits of a first size,a second number of pre-adders,a third number of block inputs, respective pairs of said block inputs being connected to respective ones of a first subset of said multiplier circuits, said respective pairs of said block inputs also being combined in said pre-adders and then input to a second subset of said multiplier circuits,a fourth number of additional inputs,a first set of controllable elements that controllably select between said additional inputs, and outputs of some of said pre-adders, for input to one of said multipliers, and that controllably select between said additional inputs, and some of said block inputs, for input to some of said pre-adders,a plurality of shifters so that partial product outputs of each of said multipliers are shifted by one or more shift amounts to provide one or more shifted partial product outputs from each of said multipliers,a joint adder structure for combining said shifted partial product outputs of said multipliers,a second set of controllable elements that controllably connect and disconnect certain ones of said shifted partial products to or from said joint adder structure, anda third controllable element for selectively splitting said joint adder structure into two smaller adder structures, said method comprising:configuring said first and second sets of controllable elements and said third controllable element to select between operation of said specialized processing block as a single block with said first number of multipliers to support one ternary Karatsuba decomposition of one multiplication operation, and operation of said specialized processing block as two sub-blocks each having a respective third or fourth subset of said multipliers including half said first number of multipliers, to support two separate binary Karatsuba decompositions of two multiplication operations.

10. The method of claim 9 wherein: said first number is six;each of said third and fourth subsets of said multipliers includes three of said multipliers;said ternary Karatsuba decomposition performs a multiplication operation that requires nine of said multipliers in the absence of ternary Karatsuba decomposition; andeach respective one of said first and second binary Karatsuba decompositions performs a respective multiplication operation that requires four of said multipliers in the absence of binary Karatsuba decomposition.

11. The method of claim 10 further comprising, when said third controllable element is configured to split said joint adder structure into said two smaller adder structures: configuring said first set of controllable elements to connect said third subset of said multipliers to one of said two smaller adder structures and to connect said fourth subset of said multipliers to another of said two smaller adder structures, wherein said third subset of said multipliers includes a first group of multipliers from said first and second subsets of said multipliers, and said fourth subset of said multipliers includes a second group of multipliers from said first and second subsets of said multipliers; andconfiguring said second set of controllable elements to connect and disconnect said certain ones of said shifted partial products to support two separate binary Karatsuba decompositions of two multiplication operations; wherein:said third subset of said multipliers and said one of said two smaller adder structures performs a first one of said binary Karatsuba decompositions for a first multiplication operation; andsaid fourth subset of said multipliers and said another of said two smaller adder structures performs a second one of said binary Karatsuba decompositions for a second multiplication operation.

12. The method of claim 9 further comprising, when said third controllable element is configured to split said joint adder structure into said two smaller adder structures, configuring said first set of controllable elements to select said additional inputs for input to said one of said multipliers and for input to said some of said pre-adders.

13. The method of claim 9 further comprising providing in said joint adder structure two identical but offset patterns for aligning and combining said shifted partial product outputs of said multipliers.

14. The method of claim 13 further comprising, when said third controllable element is configured to maintain said joint adder structure as one adder structure, wherein said joint adder structure comprises a compressor that compresses combined shifted partial product outputs of said multipliers to provide compressed vectors, and said joint adder structure further comprises first and second carry-propagate adders: configuring said first set of controllable elements to select said outputs of said some of said pre-adders for input to said one of said multipliers, and to select said some of said block inputs for input to said some of said pre-adders;configuring a first less significant group of bits of each of said compressed vectors as inputs to one of said first and second carry-propagate adders;configuring a second more significant group of bits of each of said compressed vectors as inputs to another of said first and second carry-propagate adders; andconfiguring said third controllable element to connect, as a carry input to said another of said first and second carry-propagate adders, a bit from said one of said first and second carry-propagate adders corresponding to a most significant bit of said first less significant group of bits.

15. The method of claim 9 further comprising: extending at least one of said multipliers by 1 bit in each dimension beyond said first size.

16. A non-transitory machine-readable storage medium encoded with instructions for performing a method of configuring a programmable integrated circuit device to performing multiplication operations, said programmable integrated circuit device including a specialized processing block, said specialized processing block comprising: a first number of multiplier circuits of a first size,a second number of pre-adders,a third number of block inputs, respective pairs of said block inputs being connected to respective ones of a first subset of said multiplier circuits, said respective pairs of said block inputs also being combined in said pre-adders and then input to a second subset of said multiplier circuits,a fourth number of additional inputs,a first set of controllable elements that controllably select between said additional inputs, and outputs of some of said pre-adders, for input to one of said multipliers, and that controllably select between said additional inputs, and some of said block inputs, for input to some of said pre-adders,a plurality of shifters so that partial product outputs of each of said multipliers are shifted by one or more shift amounts to provide one or more shifted partial product outputs from each of said multipliers,a joint adder structure for combining said shifted partial product outputs of said multipliers,a second set of controllable elements that controllably connect and disconnect certain ones of said shifted partial products to or from said joint adder structure, anda third controllable element for selectively splitting said joint adder structure into two smaller compressor and adder structures, said instructions comprising:instructions to configure said first and second sets of controllable elements and said third controllable element to select between operation of said specialized processing block as a single block with said first number of multipliers to support one ternary Karatsuba decomposition of one multiplication operation, and operation of said specialized processing block as two sub-blocks each having a respective third or fourth subset of said multipliers including half said first number of multipliers, to support two separate binary Karatsuba decompositions of two multiplication operations.

17. The non-transitory machine-readable storage medium of claim 16 wherein: said first number is six;each of said third and fourth subsets of said multipliers includes three of said multipliers;said ternary Karatsuba decomposition performs a multiplication operation that requires nine of said multipliers in the absence of ternary Karatsuba decomposition; andeach respective one of said first and second binary Karatsuba decompositions performs a respective multiplication operation that requires four of said multipliers in the absence of binary Karatsuba decomposition.

18. The non-transitory machine-readable storage medium of claim 17 wherein, when said instructions comprise instructions to configure said third controllable element to split said joint adder structure into said two smaller adder structures, said instructions further comprise: instructions to configure said first set of controllable elements to connect said third subset of said multipliers to one of said two smaller adder structures and to connect said fourth subset of said multipliers to another of said two smaller adder structures, wherein said third subset of said multipliers includes a first group of multipliers from said first and second subsets of said multipliers, and said fourth subset of said multipliers includes a second group of multipliers from said first and second subsets of said multipliers; andinstructions to configure said second set of controllable elements to connect and disconnect said certain ones of said shifted partial products to support two separate binary Karatsuba decompositions of two multiplication operations; wherein:said third subset of said multipliers and said one of said two smaller adder structures performs a first one of said binary Karatsuba decompositions for a first multiplication operation; andsaid fourth subset of said multipliers and said another of said two smaller adder structures performs a second one of said binary Karatsuba decompositions for a second multiplication operation.

19. The non-transitory machine-readable storage medium of claim 16 wherein: when said instructions comprise instructions to configure said third controllable element to split said joint adder structure into said two smaller adder structures, said instructions further comprise instructions to configure said first set of controllable elements to select said additional inputs for input to said one of said multipliers and for input to said some of said pre-adders.

20. The non-transitory machine-readable storage medium of claim 16 wherein, when said instructions comprise instructions to configure said third controllable element to maintain said joint adder structure as one adder structure, wherein said joint adder structure comprises a compressor that compresses combined shifted partial product outputs of said multipliers to provide compressed vectors, and said joint adder structure further comprises first and second carry-propagate adders and provides two identical but offset patterns for aligning and combining said shifted partial product outputs of said multipliers, said instructions further comprise: instructions to configure said first set of controllable elements to select said outputs of said some of said pre-adders for input to said one of said multipliers, and to select said some of said block inputs for input to said some of said pre-adders;instructions to configure a first less significant group of bits of each of said compressed vectors as inputs to one of said first and second carry-propagate adders;instructions to configure a second more significant group of bits of each of said compressed vectors as inputs to another of said first and second carry-propagate adders; andinstructions to configure said third controllable element to connect, as a carry input to said another of said first and second carry-propagate adders, a bit from said one of said first and second carry-propagate adders corresponding to a most significant bit of said first less significant group of bits.

21. The non-transitory machine-readable storage medium of claim 16 wherein said instructions further comprise instructions to extend at least one of said multipliers by 1 bit in each dimension beyond said first size.