IN-BAND METHOD TO CONFIGURE EQUALIZATION LEVELS

Abstract

An in-band configuration technique configures a data communications link for high-speed data communications between at least a first and second integrated circuit using in-band communications between the first and second integrated circuits. The technique configures at least one equalizer of the data communications link with predetermined equalizer settings selected from a plurality of predetermined equalizer settings based on a selected rate of data communications for the link.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1 illustrates a block diagram of two integrated circuit devices coupled by a communications link.

FIGS. 2A and 2B illustrate block diagrams of two integrated circuit devices coupled by a communications link consistent with one or more embodiments of the present invention.

FIGS. 3A and 3B illustrate exemplary information and control flows for an in-band configuration technique consistent with one or more embodiments of the present invention.

FIG. 4 illustrates a block diagram of a portion of a communications link transmit path on an integrated circuit device consistent with one or more embodiments of the present invention.

FIG. 5 illustrates a block diagram of an exemplary portion of the transmit path of FIG. 4 consistent with one or more embodiments of the present invention.

FIG. 6 illustrates a block diagram of an exemplary portion of a receive path of an integrated circuit device consistent with one or more embodiments of the present invention.

FIG. 7 illustrates exemplary portions of a decision feedback restore circuit of a receiver interface consistent with at least one embodiment of the invention.

Claims

1. A method for performing in-band configuration of equalization levels associated with a communications link comprising: configuring a transmit clock signal of a transmitter circuit on a first integrated circuit and coupled to at least one communications path to have a first frequency based, at least in part, on supported clock frequencies of the first integrated circuit and at least a second integrated circuit, the supported clock frequencies being determined based, at least in part, on communications at a second frequency over the at least one communications path between the first and second integrated circuits;configuring at least one equalizer with one or more predetermined settings corresponding to the first frequency; andcommunicating data between the first and second integrated circuits using the at least one equalizer and the at least one communications path, the data communication being at a rate based, at least in part, on the first frequency.

2. The method, as recited in claim 1, wherein the data communication includes a plurality of packet sequences originating at one of the first and second integrated circuits and terminating at the other of the first and second integrated circuits.

3. The method, as recited in claim 1, further comprising: configuring the transmit clock signal to have a frequency based, at least in part, on the second frequency; andconfiguring the at least one equalizer with one or more predetermined settings corresponding to the second frequency,wherein the second frequency is substantially less than the first frequency and determination of the supported clock frequencies occurs while the at least one equalizer is configured with one or more predetermined settings corresponding to the second frequency.

4. The method, as recited in claim 1, wherein the equalizer is configured by a basic input/output system (BIOS) associated with an individual one of the first and second integrated circuits including the equalizer.

5. The method, as recited in claim 1, wherein the determining supported clock frequencies comprises: reading respective individual frequency capability registers corresponding to the first and second integrated circuits.

6. The method, as recited in claim 1, wherein the first frequency is based, at least in part, on information related to a layout of a printed circuit board attached to at least one of the first and second integrated circuits.

7. The method, as recited in claim 1, wherein the configuring the at least one equalizer comprises: selecting the one or more predetermined settings corresponding to the first frequency from a plurality of predetermined settings for the equalizer.

8. The method, as recited in claim 1, wherein the at least one equalizer includes a transmitter equalizer and a receiver equalizer.

9. The method, as recited in claim 1, wherein the transmit clock and a data signal are communicated between the first and second integrated circuits on separate ones of the at least one communications path.

10. The method, as recited in claim 1, further comprising: configuring the transmit clock signal to have a third frequency based, at least in part, on the supported clock frequencies and a power savings mode indicator;configuring the at least one equalizer to have settings corresponding to the third frequency; andcommunicating data between the first and second integrated circuits using the at least one equalizer and the at least one communications path, the data communication being at a rate based, at least in part, on the third frequency.

11. The method, as recited in claim 1, wherein the at least one communications path is at least one of a bus coupling the first and second integrated circuits within an embedded application, a bus on a printed circuit board coupling the first and second integrated circuits on a single printed circuit board, and a bus coupling the first and second integrated circuits on separate printed circuit boards.

12. An apparatus comprising: a first integrated circuit comprising at least one equalizer, the first integrated circuit being configured to receive at a first data rate, over at least one communications path, frequency capability information associated with a second integrated circuit,wherein the first integrated circuit is operable to configure based, at least in part, on the frequency capability information of the second integrated circuit, a transmit frequency and the equalizer with one or more predetermined settings,wherein the at least one communications path is an in-band communications path between the first and second integrated circuits.

13. The apparatus, as recited in claim 12, wherein the at least one equalizer circuit includes a transmitter equalizer and a receiver equalizer.

14. The apparatus, as recited in claim 12, wherein the first integrated circuit further comprises a basic input/output system (BIOS) configured to provide the one or more predetermined setting to the equalizer circuit.

15. The apparatus, as recited in claim 12, wherein the first integrated circuit comprises at least one storage element configured to store a frequency capability of the first integrated circuit and the clock frequency of the first signal is determined based, at least in part, on the frequency capability of the first integrated circuit.

16. The apparatus, as recited in claim 12, further comprising: the at least one communications path;at least the second integrated circuit coupled to the at least one communications path, the second integrated circuit comprising at least one storage element configured to store a frequency capability of the second integrated circuit.

17. The apparatus, as recited in claim 12, further comprising: the at least one communications path;the second integrated circuit; anda printed circuit board;wherein the first integrated circuit and the second integrated circuit are attached to the printed circuit board and coupled to each other by the at least one communications path.

18. The apparatus, as recited in claim 12, further comprising: the at least one communications path;an integrated circuit substrate; andthe second integrated circuit,wherein the first integrated circuit and the second integrated circuit are formed on the integrated circuit substrate and coupled to each other by the at least one communications path.

19. The apparatus, as recited in claim 12, wherein the first integrated circuit is configured to communicate a plurality of packet sequences to the second integrated circuit over the at least one communications path.

20. An apparatus comprising: at least one equalizer means of a first integrated circuit;means for configuring, in-band, using signals having a first frequency, the at least one equalizer means to have one or more predetermined setting corresponding to a second frequency, the second frequency being based at least in part on frequency capability information associated with a second integrated circuit.

21. The apparatus, as recited in claim 20, wherein the means for configuring comprises a basic input/output system (BIOS) configured to provide the one or more predetermined setting to the equalizer circuit.

22. The apparatus, as recited in claim 20, wherein the means for configuring determines supported clock frequencies of the first integrated circuit and at least a second integrated circuit coupled to the first integrated circuit by a first communications means.

23. The apparatus, as recited in claim 13, wherein the first integrated circuit comprises a driver circuit configured to generate a first signal on the differential node based, at least in part, on a data signal, the first signal having a voltage swing; andwherein at least a portion of the transmitter equalizer is configured to generate a current through the differential node based, at least in part, on a first bit-time of the data signal and an equalization operation, thereby adjusting the voltage swing of the first signal.