Patent Application
20170024298
The present disclosure relates generally to hardware emulation, and more specifically, to apparatus for in-system emulation of non-volatile memory devices.
It is known to use hardware emulation techniques in the development of one-time programmable PROM memory devices, and other non-volatile memory devices. In integrated circuit design, hardware emulation is the process of imitating the behavior of one or more pieces of hardware under development using another piece of hardware. Often in hardware emulation, the one or more pieces of hardware under development, sometimes called target hardware, is emulated during development of a system incorporating the hardware, sometimes called the target system. As applied in development of non-volatile memories, such as PROMs, hardware emulation techniques can avoid the need to burn numerous pre-production PROMs during the development process.
Hardware emulation systems for non-volatile memories, such as PROMs, typically employ a special purpose emulation system, such as an emulator device that includes a probe or other connector that is designed to communicate with a socket or other footprint of the PROMs. Because of the need for additional hardware, such as emulation electronics, wiring, and probes or other electrical interfaces, conventional PROM emulation systems can be quite bulky.
In various applications, it is necessary to test a target system including a target non-volatile memory device as an integral system with the target non-volatile memory secured within the system, e.g., in tests such as environmental tests. Conventional non-volatile memory emulation systems may not be usable where the extent of a conventional non-volatile memory emulation system is incompatible with volume constraints of the target system; or where it is necessary to emulate and test a target non-volatile memory component embedded within its target system. This is particularly true when the target non-volatile memory component occupies a limited volume and footprint within the target system.
Various non-volatile memory components (herein sometimes called “NVM”) are commonly known as read-only memory (“ROM”), programmable ROM (“PROM”), erasable PROM (“EPROM”), and electrically erasable PROM (“EEPROM”) integrated circuit (“IC”) chips. Other examples of NVM components include Flash memory, magnetoresistive random-access memory (MRAM), phase-change memory or “C-RAM” non-volatile memory, and Nano-RAM computer memory technology (“NRAM”). The present disclosure generally refers to embodiments involving in-system emulation of PROM devices, but references herein to in-system PROM emulation may also include in-system emulation of other NVM devices.
The embodiments described herein describe an apparatus for in-system emulation of a PROM memory device that permits development and testing of an emulated PROM installed within a target system, including target systems with severe volume constraints. The embodiments described herein describe an apparatus for in-system emulation of a PROM memory device, and applications of this apparatus. The in-system PROM emulation apparatus allows the design, prototyping and testing of a target PROM, wherein the in-system emulation apparatus serves as stand-in hardware for the target PROM within a target system. As stand-in hardware for the target PROM, the in-system PROM emulation apparatus is mounted within a surface mount footprint of the target PROM within the target system, and fits within length, width, and height constraints (i.e., volume constraints) of the target PROM within the target system.
In one embodiment, an apparatus for in-system emulation of a target programmable read-only memory (PROM) in a target system, the target PROM being a one-time programmable non-volatile memory device that stores data, and the target PROM being mounted to a surface mount footprint within a volume of the target PROM in the target system, the apparatus comprises a device converter including a device converter circuit board and at least one reprogrammable memory device electrically and mechanically coupled to the device converter circuit board; and a surface mount emulator foot secured to the device converter circuit board, the surface mount emulator foot having a developmental surface mount footprint that emulates the surface mount footprint of the target PROM, and the device converter and surface mount emulator foot fitting within the volume of the target PROM in the target system, the device converter and surface mount emulator foot provide electrical interface routing between device terminals of the at least one reprogrammable memory device and footprint terminals of the surface mount emulator foot to route developmental data stored by the reprogrammable memory device from the device terminals of the at least one reprogrammable memory device to the footprint terminals of the surface mount emulator foot, the developmental data stored by the reprogrammable memory device emulating the data stored by the target PROM.
In another embodiment, an apparatus for in-system emulation of a target programmable read-only memory (PROM) in a target system, wherein the target PROM is a one-time programmable non-volatile memory device that stores configuration data for configuring the target system and that stores programming data for programming the target system, and wherein the target PROM is a small-outline package (SOP) device mounted to a surface mount footprint in the target system, the apparatus comprises a device converter including a device converter circuit board and a plurality of reprogrammable memory devices electrically and mechanically coupled to the device converter circuit board, the plurality of reprogrammable memory devices configured to store developmental configuration data that emulate the configuration data of the target PROM and store developmental programming data that emulate the programming data stored by the target PROM; and a surface mount emulator foot secured to the device converter circuit board, the surface mount emulator foot having a developmental surface mount footprint that is configured to emulate the surface mount footprint of the target PROM, the device converter and surface mount emulator foot configured to route the developmental configuration data and the developmental programming data from the plurality of reprogrammable memory devices to the surface mount emulator foot.
Additional features and advantages of an embodiment will be set forth in the description which follows, and in part will be apparent from the description. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the exemplary embodiments in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying figures which are schematic and are not intended to be drawn to scale. Unless indicated as representing the background art, the figures represent aspects of the disclosure.
The present disclosure is here described in detail with reference to embodiments illustrated in the drawings, which form a part here. Other embodiments may be used and/or other changes may be made without departing from the spirit or scope of the present disclosure. The illustrative embodiments described in the detailed description are not meant to be limiting of the subject matter presented here. Furthermore, the various components and embodiments described herein may be combined to form additional embodiments not expressly described, without departing from the spirit or scope of the invention.
Reference will now be made to the exemplary embodiments illustrated in the drawings, and specific language will be used here to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Alterations and further modifications of the inventive features illustrated here, and additional applications of the principles of the inventions as illustrated here, which would occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of the invention.
The reprogrammable memory devices of in-system PROM emulator 240 enable development of the target PROM without requiring consumption (burning) of numerous PROMs during the development process. The reprogrammable memory devices (also called in-system reprogrammable memory devices in the present disclosure) can be reprogrammed as many times as required for a development program, allowing the reprogrammable memory devices to be iteratively tested with no need to replace memory devices of the in-system PROM emulator. It is only when the final design of the target PROM has been thoroughly tested using in-system PROM emulator 240 that this design is burned into the target PROM and the emulator is replaced with the target PROM. Similarly, for in-system emulation of NVM technologies other than PROM, the target NVM device may be produced or written with the final design only when that design has been thoroughly tested by in-system emulation.
Furthermore, repeated removal and replacement of the target PROM (or other target NVM) can wear away the circuit board containing this PROM, and can cause permanent damage to the PROM footprint at this circuit board. The present in-system emulation apparatus requires only a single rework cycle—install PROM emulator hardware; remove PROM emulator hardware; install target PROM (or other target NVM)—thereby avoiding the risks of wear and damage to the circuit board caused by repeated removal and replacement of the target PROM (or other target NVM).
Surface mount emulator foot 100 is secured to device converter 200 to form the in-system PROM emulator 240. In an advantageous approach to hardware emulation of PROM devices, in-system PROM emulator 240 acts as a stand-in hardware emulator during development of the target PROM and the target system containing that PROM. As stand-in hardware, the in-system PROM emulator 240 is mounted within a surface mount footprint of the target PROM within the target system. Furthermore, the in-system PROM emulator 240 fits within length, width, and height constraints (also herein called volume constraints) of the target PROM within the target system, such as requirements of physical separation of the target PROM from adjacent components of the target system. In an embodiment as seen in
As used in the present disclosure, a “target PROM” is a non-volatile memory device (NVM) under development, and a “target system” is a system incorporating the target PROM. In one embodiment, the target PROM is a one-time programmable PROM device under development. As used in the present disclosure, “development” and variants such as “develop” encompass various aspects or phases of product development such as design, programming, prototyping (design verification), and testing. As used in the present disclosure, “in-system emulation” refers to the emulation of a target PROM embedded within its target system, e.g., during testing.
In an embodiment, the target system is the SpaceCube™ spaceflight processing system disclosed, e.g., in U.S. Patent Publication No. 20130181809 A1, entitled “SpaceCube MINI,” which is hereby incorporated by reference in its entirety. This patent application discloses a miniature cube processing system for on-board spacecraft processing. In an embodiment, the target system is SpaceCube 2.0, a compact, high-performance, low-power onboard processing system that incorporates hybrid processing elements including a central processing unit (CPU), field programmable gate array (FPGA), and digital signal processor (DSP). In an embodiment, program execution can be reconfigured in real time and algorithms can be updated, modified, and/or replaced at any point during a spaceflight mission.
In an embodiment, SpaceCube 2.0 possesses compact size specifications (5×5×7 in. (≈12.7×12.7×17.8 cm)). As a result of this highly compact design, in-system emulation of hardware of this target system (i.e., the target PROM) requires that the in-system emulator fit within limited volume constraints of the target PROM, including not only the target PROM footprint, but also its height. This illustrates that depending on requirements of the target system, volume constraints of a target PROM in a target system, also herein called volume of the target PROM in the target system, may be more or less limited and may be comparable to or greater than the length, width, and height specifications of the target PROM itself.
In an embodiment, PROM memory devices of the target system (i.e., target PROM) are used for CPU boot, health and safety, and basic command and telemetry functionality in the SpaceCube 2.0 system. In one embodiment, the target PROM is a 3D PLUS™ programmable ROM (PROM) module, part number 3DPO64M08VS2299, supplied by 3D PLUS USA, Inc., McKinney, Tex. The 3D PLUS™ PROM is a 64 Mbit PROM, organized as 8M×8. The 3D PLUS™ PROM module is a 3.3V device. It is non-volatile, one-time-programmable, read only memory, designed to store configuration bitstreams of FPGA devices. The 3D PLUS™ PROM module is also designed for general data storage functions, such as processor boot PROM, and storage of data parameters.
The 3D PLUS™ PROM provides dual configuration modes: serial configuration (up to 264 Mb/s) and parallel (up to 264 Mb/s at 33 MHz). When the FPGA is in Master Serial mode, it generates a configuration clock that drives the module. A short access time after the rising clock edge, data appears on the module DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the module. When the FPGA is in Slave Serial mode, the module and the FPGA are both clocked by an incoming signal. When the FPGA is in Master SelectMAP mode, it generates a configuration clock that drives the module and the FPGA. After the rising CCLK edge, data are available on the module DATA (D0-D7) pins. In an embodiment, the data will be clocked into the FPGA on the following rising edge of the CCLK. When the FPGA is in Slave SelectMAP mode, the module and the FPGA both are clocked by an incoming signal. In an embodiment, a free-running oscillator is used to drive CCLK.
In another embodiment, the target PROM is a 128 Mbit 3D PLUS™ programmable ROM (PROM) module, part number 3DPO128M08VS4667. This 128 Mbit 3D PLUS™ PROM is organized as 16M×8. It has the same footprint as the 64 Mbit PROM, but a greater height than the 64 Mbit PROM.
The 64 Mbit and 128 Mbit 3D PLUS™ target PROMs stack vertically, a characteristic that imposes tight length and width constraints for the in-system PROM emulator.
In an embodiment, the 3D PLUS™ PROM is deployed within the SpaceCube 2.0 target system to configure two Virtex-5 field-programmable gate array (FPGA) parts (Virtex-5™ FPGA parts are supplied by Xilinx, Inc., San Jose, Calif.). 3D PLUS™ PROM also can configure other Xilinx FPGA devices, and can program Xilinx FPGA devices during a spaceflight mission.
In an embodiment, other exemplary computing power specifications for the SpaceCube 2.0 target system include four PowerPC 440 RISC processors (1100 DMIPS each), 500+DSP48Es (2×580 GMACS), 100+LVDS high-speed serial I/Os (1.25 Gbps each), and 2×190 GFLOPS single-precision (65 GFLOPS double-precision) floating point performance. Additionally the SpaceCube 2.0 target system may include RAM memory for program execution, and FLASH/EEPROM memory to store algorithms and application code for the CPU, FPGA, and DSP processing elements.
In an embodiment, various components of in-system PROM emulator 240, including reprogrammable memory devices of device converter 200, the footprint and pin assignments of surface mount emulator foot 100, and interface routing between these components, are designed to emulate the serial configuration and parallel configuration functions of the 3D PLUS™ PROM as well as other functions of the 3D PLUS™ PROM. In addition to configuration of FPGA devices, the reprogrammable memory devices of device converter 200 may store programming data to emulate programming data stored by the 3D PLUS™ PROM and used for various mission functions such as health and safety, basic command and telemetry. The reprogrammable memory devices of device converter 200 may emulate data-storage functions of the 3D PLUS™ target PROM such as storage of FPGA hardware Bootloader, or processor boot code; and storage of general data parameters. In addition, during development of the target system, in-system PROM emulator 240 can use configuration data stored by the reprogrammable memory devices of device converter 200 to directly configure field-programmable gate array (FPGA) devices of the target system, such as FPGA devices supplied by Xilinx, Inc.
In an embodiment, in-system PROM emulator 240 incorporates XILINX® XCF32P Flash In-System PROM devices as reprogrammable memory devices of device converter 240 (XILINX is a trademark of Xilinx, Inc., San Jose, Calif.). Xilinx® XCF32P Flash Programmable PROMs are designed for configuration of Xilinx FPGAs, as well as for general data storage, and are available in small-footprint 0.8 mm pitch, 48 ball BGA packages (ball grid array part). Xilinx® XCF32P Flash Programmable PROMs are cascadable for storing longer or multiple bitstreams.
In an embodiment, in-system PROM emulator 240 incorporates four Xilinx® XCF32P Flash In-System PROM reprogrammable memory devices 204, 206, 214, and 216 to support in-system emulation of both 3D PLUS™ 3DPO64M08VS2299 programmable ROM (PROM) module, a 64 Mbit PROM; and 3D PLUS™ 3DPO128M08VS4667 programmable ROM (PROM) module, a 128 Mbit PROM. While two Xilinx® XCF32P Flash In-System PROMs are sufficient to emulate the 64 Mbit PROM, in-system PROM emulator 240 includes the four Xilinx® XCF32P Flash In-System PROMs in order to emulate the 128 Mbit PROM. As described below, in-system PROM emulator 240 arrays these four in-system reprogrammable PROM devices and other components within a compact form factor suitable for mounting within the surface mount footprint, and for fitting within volume constraints, of the 3D PLUS™ programmable ROM (the target PROM).
Turning to
In an embodiment, emulator foot PCB 102 supports a surface mount package emulator adapter 112. Surface mount package emulator adapter 112 (also called emulator adapter 112) provide interconnections to 0.8 mm pitch, 7×7 array of BGA (ball grid array) pads 116, for access to the 44 leadless side castellations 104, 106. Emulator foot PCB 102 provides custom pin mapping between the 7×7 ball grid array (BGA) 116 and the 44 leadless side castellations 104, 106. In an embodiment, emulator adapter 112 is soldered to BGA 116 using solder balls. Emulator adapter 112 includes grid array 114 for a pluggable connection to device converter 200 to provide electrical and mechanical interface between the surface mount emulator foot 100 and the device converter 200. In an embodiment, grid array 114 is a 7×7, 0.8 mm pitch micro grid array of terminal pins, which are connected electrically within emulator adapter 112 to the solder balls soldered to the 7×7 BGA contacts array 116.
In an embodiment, the surface mount package emulator adapter 112 is a Giga-snaP™ BGA 0.8 mm male surface mount foot, part number SF-BGA4NB-B-66F, supplied by Ironwood Electronics, Eagan, Minn. In this embodiment, in the 7×7, 0.8 mm pitch micro grid array of terminal pins, the pin diameter is 0.2032 mm. In an embodiment, the emulator foot printed circuit board (PCB) 102 includes a circuit board substrate, IPC 4101/21/26/83/98, with thickness 0.635±0.18 mm, and Td≧345C (per IPC standard of the Association Connecting Electronics Industries).
In an embodiment as illustrated in
Turning to the top and bottom views of device converter 200 in
In an embodiment, the reprogrammable memory devices 204, 206, 214, and 216 are Flash PROM BGA packages. In an embodiment, reprogrammable memory devices 204, 206, 214, and 216 are XILINX® XCF32P Flash In-System PROMs, which are 0.8 mm pitch, 48 ball BGA packages. As seen in
In an embodiment, the overall height (h1; also called height H in the present disclosure) of in-system PROM emulator 240 is 7.31 mm. The overall length (L=26.00±0.13 mm) and width (W=15.00±0.13 mm) of in-system PROM emulator 240 are based upon the length and width of device converter PCB 202, which extend beyond length and width of the emulator foot PCB 102 (cf. the isometric view of in-system PROM emulator 240 in
In emulation of NVM technologies other than one-time programmable PROM devices, component design and dimensional limitations (L, W, H) of an in-system emulator may be chosen as appropriate for particular requirements of the in-system NVM.
In an embodiment, device converter 200 includes a voltage regulator 208 and four sets of bypass capacitors 210A, 210B, 210B, and 210D, to provide voltage supplies for the XILINX® XCF32P Flash PROMs 204, 206, 214, and 216 (
Device converter 200 includes joint test action group (JTAG) jumpers 212, which communicate with JTAG terminals of XILINX® XCF32P Flash PROMs 204, 206, 214, and 216 to support programming, prototyping, and testing according to IEEE Standard 1149.1/1532 Boundary-Scan (JTAG), during in-system emulation of the target PROM. Test ports TP1-TP4 corresponding to JTAG jumpers 212 are seen at 318 in
In an embodiment, the device converter printed circuit board (PCB) 202 includes a circuit board substrate, IPC 4101/21/26/83/98, with thickness 0.889±0.18 mm, and Td≧345C (per IPC standard of the Association Connecting Electronics Industries).
In an embodiment, device converter 200 includes a 7×7, 0.8 mm micro grid array 218 of female socket contacts. Selected terminals of the XILINX® XCF32P Flash PROMs 204, 206, 214, and 216 (also called device terminals in the present disclosure) are electrically connected to given contacts of the micro grid array 218 via custom pin mapping in the BGA device converter circuit board 202. Device converter printed circuit board 202 is electrically and mechanically connected to the surface mount emulator foot 100 by plugging the 7×7, 0.8 mm pitch micro grid array of terminal pins 114 of surface mount emulator foot 100 into the 7×7, 0.8 mm micro grid array of female socket contacts 218. In an embodiment, the connection of terminal pins 114 to socket contacts 218 is the only connection between surface mount emulator foot 100 and device converter 200 in assembling the in-system PROM emulator board 240. In an embodiment, terminal pins 114 are formed of a shell material of brass, and a shell finish of 10 microinch gold over 50 microinch nickel (min.). In an embodiment, female socket contacts 218 are formed of a contact material of beryllium copper, and a contact finish of 10 microinch gold over 100 microinch nickel (min.).
In an embodiment, XILINX® XCF32P Flash PROMs 204, 206, 214, and 216 provide in-system emulation of functions of the target PROM, 3D PLUS™ programmable ROM (PROM) module, part number 3DPO64M08VS2299, as a one-time programmable non-volatile device that stores Xilinx FPGA configuration files, and that can program a Xilinx FPGA as well as store general data. XILINX® XCF32P Flash PROMs 204, 206, 214, and 216 store developmental configuration data that emulate the configuration data stored by the 3D PLUS™ target PROM and developmental programming data that emulate the programming data stored by the 3D PLUS™ target PROM.
JTAG interfaces of PROM 302 include TDI (Test Data In); TDO (Test Data Out); TCK (Test Clock); and TMS (Test Mode Select). In an embodiment, the JTAG interfaces of Flash PROM 302 are daisy chained with JTAG interfaces of the other three Flash PROM devices (not shown), so that only one JTAG chain is needed. TMS and TCK data are common to all four devices. The TDI terminal of Flash PROM 302 feeds to this device data supplied by the TDO terminal of the prior Flash PROM device in the daisy chain. The TDO terminal of Flash PROM 302 supplies data to the TDI terminal of the next Flash PROM device in the daisy chain.
Chip Enable Input and Chip Enable Output are used in reading memory address registers of the four XILINX® XCF32P Flash PROMs. The Chip Enable Input terminal for Flash PROM 302 is FLASH CE0, and the Chip Enable Input terminal is FLASH CE2, Flash CE4, and Flash CE6 for the other three Flash PROMs, respectively (not shown in
Another device terminal of XILINX® XCF32P Flash PROM 302 seen in
Various components of the in-system PROM emulator 240 act as an interposer, providing provide electrical interface routing between the BGA48, 0.8 MM pitch device terminals of XILINX® XCF32P Flash PROMs 204, 206, 214, and 216, and the SOP44, 0.8 mm pitch footprint terminals of surface mount emulator foot 100. Segments of the electrical interface routing include: custom pin mapping by the device converter PCB 202 from the BGA48 device terminals to the micro-grid array 218; mating interconnections between the micro grid arrays 218 and 114; electrical interface routing by the surface mount package emulator adapter 112 from the micro grid array 114 to the 7×7 ball grid array (BGA) 116; and custom pin mapping by the emulator foot printed circuit board (PCB) 102 from the 7×7 BGA 116 to the SOP44 footprint terminals of the surface mount emulator foot 100.
While various aspects and embodiments have been disclosed, other aspects and embodiments are contemplated. The various aspects and embodiments disclosed are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.
The foregoing method descriptions and the interface configuration are provided merely as illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order presented. As will be appreciated by one of skill in the art the steps in the foregoing embodiments may be performed in any order. Words such as “then,” “next,” etc. are not intended to limit the order of the steps; these words are simply used to guide the reader through the description of the methods. Although process flow diagrams may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to a return of the function to the calling function or the main function.
The various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed here may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The invention described herein was made by employees of the United States Government and may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefore.
