Patent Application
20140369347
The technology of the disclosure relates to data transfers between and among digital data switches, servers, and other devices, and related components, devices, systems, and methods. The disclosure relates generally to data transfers between and among digital data switches, servers, and other devices, and more particularly to increasing radixes of digital data switches, communications switches, and related components and methods, which may be used in data centers and other data transfer applications.
As demand for network services increases, high density digital data switches are being used at an increasing rate. One application for digital data switches is in a data center or other installation where a large amount of data must be transferred among devices. High density switches, such as “top-of-rack” switches, help to decrease the number of “layers” in a network. This arrangement allows data to be transferred between devices while passing through a minimum number of intermediary switches and other devices.
Conventional switches can employ passive breakout cable assemblies each connected between a single high bandwidth port and a plurality of lower bandwidth ports. In this regard,
However, as the number of devices, such as servers, served by a switch increases, the limitations of the breakout cable assembly 10 become apparent. Many conventional servers are operated with 10 G connections, such as a main SFP+ connection and a backup SFP+ connection connected to a separate, redundant switch. However, because each conventional breakout cable assembly 10 of
Embodiments of the disclosure relate to increasing radixes of digital data switches and communications switches, and related components and methods. In one embodiment, a gearbox distributes a plurality of high bandwidth digital data signals from a digital data switch to a plurality of devices. A gearbox can be a device or component that combines, divides, converts or otherwise modifies one or more communications or other signals for distribution. The digital data switch is configured to combine one or more groups of downlink component digital data signals into one or more respective downlink combined digital data signals, and transmit each combined digital data signal to the gearbox. Each downlink component digital data signal is combined into only one of the at least one respective downlink combined digital data signal. Thus, no individual component digital data signal is divided between multiple downlink combined digital data signals, thereby simplifying the process of combining the downlink component digital data signals and dividing the downlink combined digital data signals. The gearbox is then configured to divide each downlink digital data signal into its respective downlink component digital data signal, and transmit each downlink component digital data signal to a unique device or location. As a non-limiting example, each of a plurality of pairs of 10 gigabit (10 G) downlink component digital data signals is combined into a respective 20 G combined digital data signal. Each 20 G combined digital data signal comprises interleaved sections of each of the respective pair of 10 G downlink component digital data signals that can be easily synchronized to a clock signal. The gearbox can then divide each 20 G combined digital data signal into the pair of 10 G downlink component digital data signals and transmit each 10 G downlink component digital data signal to a unique device or location. In this manner, digital data switches can be designed employing embodiments disclosed herein to support increased numbers of devices and/or bandwidths within conventional form factors. One advantage of this arrangement is that the switch radix is doubled while maintaining backward compatibility with existing ports and connectors.
One embodiment of the disclosure relates to a gearbox for a communications system. The gearbox comprises a plurality of server-side inputs, each configured to receive a respective uplink component communications signal from a respective location. The gearbox further comprises at least one multiplexer configured to combine at least two of the uplink component communications signals into at least one respective uplink combined communications signal such that each uplink component communications signal is combined into only one of the at least one respective uplink combined communications signal. The gearbox further comprises at least one switch-side output configured to transmit a respective uplink combined communications signal to a communications switch. In this manner, a radix of the communication switch can be increased in a simplified and efficient manner.
An additional embodiment of the disclosure relates to a communications switch. The communications switch comprises at least one input configured to receive a respective uplink combined communications signal comprising a plurality of uplink component communications signals from a gearbox, each uplink component communications signal corresponding to a unique location. The communications switch further comprises at least one demultiplexer configured to divide each of the at least one uplink combined communications signal into the respective plurality of uplink component communications signals.
An additional embodiment of the disclosure relates to a method of transferring communications signals. The method comprises receiving, at a gearbox, a plurality of uplink component communications signals. The method further comprises combining, at the gearbox, at least two of the uplink component communications signals into at least one respective uplink combined communications signal such that each uplink component communications signal is combined into only one of the at least one respective uplink combined communications signal. The method further comprises transmitting each of the at least one uplink combined communications signal to a communications switch.
An additional embodiment of the disclosure relates to a communications distribution system. The communications distribution system comprises at least one communications switch and at least one gearbox connected between the at least one communications switch and a plurality of locations. The at least one gearbox comprises a plurality of server-side inputs, each configured to receive a respective uplink component communications signal from a respective location. The at least one gearbox further comprises at least one gearbox multiplexer configured to combine at least two of the uplink component communications signals into at least one respective uplink combined communications signal such that each uplink component communications signal is combined into only one of the at least one respective uplink combined communications signal. The at least one gearbox further comprises at least one switch-side output configured to transmit a respective uplink combined communications signal to the at least one communications switch. The at least one communications switch comprises at least one input configured to receive a respective uplink combined communications signal comprising a plurality of uplink component communications signals from the at least one gearbox. The at least one communications switch further comprises at least one switch demultiplexer configured to divide each of the at least one uplink combined communications signal into the respective plurality of uplink component communications signals.
Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from the description or recognized by practicing the embodiments as described in the written description and claims hereof, as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework to understand the nature and character of the claims.
The accompanying drawings are included to provide a further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment(s), and together with the description serve to explain principles and operation of the various embodiments.
Various embodiments will be further clarified by the following examples. Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, in which some, but not all embodiments are shown. Indeed, the concepts may be embodied in many different forms and should not be construed as limiting herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Whenever possible, like reference numbers will be used to refer to like components or parts.
Embodiments of the disclosure relate to increasing radixes of digital data switches and communications switches, and related components and methods. In one embodiment, a gearbox distributes a plurality of high bandwidth digital data signals from a digital data switch to a plurality of devices. A gearbox can be a device or component that combines, divides, converts or otherwise modifies one or more communications or other signals for distribution. The digital data switch is configured to combine one or more groups of downlink component digital data signals into one or more respective downlink combined digital data signals, and transmit each combined digital data signal to the gearbox. Each downlink component digital data signal is combined into only one of the at least one respective downlink combined digital data signal. Thus, no individual component digital data signal is divided between multiple downlink combined digital data signals, thereby simplifying the process of combining the downlink component digital data signals and dividing the downlink combined digital data signals. The gearbox is then configured to divide each downlink digital data signal into its respective downlink component digital data signal, and transmit each downlink component digital data signal to a unique device or location. As a non-limiting example, each of a plurality of pairs of 10 gigabit (10 G) downlink component digital data signals is combined into a respective 20 G combined digital data signal. Each 20 G combined digital data signal comprises interleaved sections of each of the respective pair of 10 G downlink component digital data signals that can be easily synchronized to a clock signal. The gearbox can then divide each 20 G combined digital data signal into the pair of 10 G downlink component digital data signals and transmit each 10 G downlink component digital data signal to a unique device or location. In this manner, digital data switches can be designed employing embodiments disclosed herein to support increased numbers of devices and/or bandwidths within conventional form factors. One advantage of this arrangement is that the switch radix is doubled while maintaining backward compatibility with existing ports and connectors.
Before describing these and other embodiments in detail, an alternative solution is first described. In this regard,
A switch motherboard 38 includes an application-specific integrated circuit (ASIC) 40, or other circuit that includes a distribution function 42. The distribution function 42 is configured to aggregate the ten (10) 10 G downlink signals 44D(1)-44D(10) into one 100 G stream across four (4) separate 25 G downlink signals 46D(1)-46D(4), which is another standardized bandwidth of the Ethernet standard. Because the 25 G Ethernet standard follows the 10 G Ethernet standard, which is used by the breakout cable assembly 10 of
A similar process is used by the gearbox 24 in
For example, converting ten (10) 10 G signals 44 into four (4) 25 G signals 46 requires complicated circuitry to be included in both the ASIC 40 of the switch 20 and in the gearbox 24. In the example of
The complexity of the above arrangements can be reduced by employing exemplary embodiments described herein. In this regard,
In
The gearbox 52 is likewise configured to receive and transmit respective 20 G uplink and downlink signals 56D/U(1)-(4) between the multiplexer/demultiplexer 54 of the gearbox 52 and one or more communications switches or other network device or location via a respective plurality of switch-side input/output (I/O) connections 57(1)-57(4), each having a respective input and output. In this regard, the terms “server-side” and “switch-side” are used herein for clarity and to distinguish input/output (I/O) connections 53(1)-53(8) from switch-side input/output (I/O) connections 57(1)-57(8), for example, and are not specifically limited to switch and/or server connections.
Unlike the distribution function 50 of
The multiplexer/demultiplexer 54 in the embodiment of
One advantage of the gearbox 52 of
The improved gearbox 52 is connected between QSFP ports 62 connected to a switch motherboard 63 of the switch 60 and the SFP+ port 32 of each respective server 22. Each QSFP port 62 receives a QSFP transceiver 64 connected to the gearbox 52 via four optical fiber pairs 66(1)-62(4). It should be understood that other suitable media, such as copper-based media, may be used as a substitute for optical fiber in some embodiments, and vice versa. Each respective SFP+ port 32 receives an SFP+ connector 34. Each SFP+ connector 34 is connected to the gearbox 52 via a passive cable assembly 36, such as a copper-based cable. In this embodiment, each QSFP transceiver 64 is permanently attached to optical fiber pairs 66 (i.e., part of an active cable assembly that employs optical-to-electrical conversion and electrical-to-optical conversion), but the QSFP transceiver 64 and other connectors may be pluggable (i.e. passive) in other embodiments.
The switch motherboard 63 includes an ASIC 68 or other circuit that includes a multiplexer/demultiplexer 70, similar to multiplexer/demultiplexer 54 of gearbox 52. As with the gearbox multiplexer/demultiplexer 54, the switch multiplexer/demultiplexer 70 may be embodied in hardware, in software, or a combination of the two, and may also include a multiplexer and demultiplexer as separate components or as a single integrated component, for example. It should be noted that the terms “switch multiplexer/demultiplexer” and “gearbox multiplexer/demultiplexer” may be used herein for clarity and to distinguish embodiments of the multiplexer/demultiplexer 54 from embodiments of the multiplexer/demultiplexer 70, for example, and are not specifically limited to specific hardware and/or software.—for combining each of the four (4) unique pairs of the eight (8) 10 G downlink signals 44D(1)-44D(8) into one of four (4) 20 G downlink signals 56D(1)-56D(4). The multiplexer/demultiplexer 70 in the embodiment of
The multiplexer/demultiplexer 70 can combine these signals in a number of ways. In one example, the native data rate exiting the ASIC 68 is doubled. One advantage of this arrangement is that a pin count for the ASIC 68 remains constant, thereby allowing existing packaging to be used. Another solution is to double the pin count exiting the ASIC 68 and interpose a serializer/deserializer (SerDes) (not shown) between the ASIC 68 and a QSFP port 62. In this embodiment, the SerDes is disposed proximate to the QSFP port 62 to minimize a distance that each 20 G downlink signal 56D needs to travel on the switch motherboard 63. The operation of the multiplexer/demultiplexer 70 according to one non-limiting embodiment will be discussed in greater detail below with respect to
Returning to
Thus, the system 58 does not require any 10 G downlink signal 44D to be distributed across more than one 20 G downlink signal 56D. As discussed above, this arrangement permits each 20 G downlink signal 56D to be composed of interleaved sections of equal size for each 10 G downlink signal 44D of the respective unique pair of 10 G downlink signals 44D. Accordingly, extracting each 10 G downlink signal 44D in this embodiment can be achieved by extracting the interleaved sections of each 10 G downlink signal 44D based on the downlink clock signal 72D.
The gearbox 52 then distributes each 10 G downlink signal 44D to a server 22 or other device via a respective passive cable assembly 36 in a manner similar to the arrangement of
Thus, this system 58 retains the advantages of the system 18 of
As discussed above, the simplified process of combining each unique pair of 10 G signals 44D/44U into a respective 20 G signal 56D/56U is discussed in greater detail in
In this regard,
The multiplexer/demultiplexer 70 next combines these 10 G uplink signals 44U(1), 44U(2) into 20 G combined uplink signal 56D(1) (shown in
However, it is necessary to account for the differing actual data rates 80, 82 when the packets 86 delivered from 10 G uplink signal 44U(2) lag behind the packets 84 delivered from 10 G uplink signal 44U(2), or vice versa. In this example, a fixed length packet 90, comprising null bits, for example, is inserted into the 10 G combined uplink signal 56U(1) so that the alternating arrangement of the packets 84, 86 is preserved. Thus, each series of packets 84, 86 of both 10 G uplink signals 44U(1) and 44U(2) can be interleaved into a combined 20 G uplink signal 56U(1) in a synchronized manner.
The 20 G uplink signal 56U(1) is then processed by the multiplexer/demultiplexer 70 of the ASIC 68, which, in this example, essentially reverses the process of the multiplexer/demultiplexer 54 of the gearbox 52. Each interleaved packet 84, 86 is identified by the multiplexer/demultiplexer 70 of the ASIC 68 using the corresponding buffer segments 88, for example. Each packet 84 is then lengthened such that the four packets 84 of 10 G downlink signal 44D(1) can be carried over the 10 G bandwidth 78(1) of 10 G downlink signal 44D(1) at their original signal length 76. Each packet 86 is likewise lengthened along with a packet 90 such that the three packets 86 of 10 G downlink signal 44D(2) can be carried over the 10 G bandwidth 78(2) of 10 G downlink signal 44D(2). In this example, when each 10 G downlink signal 44D(1) and 44D(2) is extracted from the 20 G downlink signal 56D(1) by the multiplexer/demultiplexer 54 of the gearbox 52, the packet 90 containing null bits can be retained, where it may be ignored by the switch 60. In another embodiment, packet 90 can be removed by the multiplexer/demultiplexer 70 of the ASIC 68 by an additional process before transmitting 10 G uplink signals 44U(1) and 44U(2) at their original actual data rates 80, 82.
A similar process may be performed for the other pairs of 10 G uplink signals 44U (e.g., 44U(3)/44U(4), 44U(5)/44U(6), 44U(7)/44U(8)). Likewise, a similar, reversed process may be performed for corresponding pairs of 10 G downlink signals 44D as well. It should be understood, however, that synchronization of the alternating packets 84, 86 of the 10 G downlink signals 44D is not required in this example because, unlike the 10 G uplink signals 44U, all the 10 G downlink signals 44D originate from the same switch 60 and are thus already synchronized to a single clock signal 72D. It also should be understood that, although the above processes are symmetrical, and result in the same 10 G signals 44D/U being employed on both the switch 60 side and the gearbox 52 side, the above embodiments are not limited thereto, and that a number of variations, omissions or additions to the disclosed embodiments are contemplated.
Application of the above process of
Focusing now on 20 G optical fiber pair 66(1), interleaved data segments 84, 86 and buffer segments 88, 90 of 20 G downlink signal 56D, arranged according to the process of
In this manner, each QSFP port 62 of the switch 60 is capable of supporting up to eight (8) 10 G server 22 connections. In this example, the switch 60 includes sixteen (16) QSFP ports 62. Thus, the switch 60 in this example can support as many as one hundred twenty eight (124) individual servers 22, or a total of one thousand two hundred eighty (1280) gigabits of bandwidth. Using the conventional breakout cable assembly 10 of
In another embodiment, a 1U switch (not shown) may include as many as thirty six (36) QSFP ports 62 within a standard 1U rack space. Thus, a 1U switch having thirty-six (36) QSFP ports 62 can support up to two hundred eighty-eight (288) individual servers 22, or a total of two thousand eight hundred eighty (2880) gigabits of bandwidth. Using the conventional breakout cable assembly 10 of
In an alternative embodiment, a 3U switch (not shown) may include as many as one hundred eight (108) QSFP ports 62 within a standard 3U rack space. Thus, a 1U switch having one hundred eight (108) QSFP ports 62 can support up to eight hundred sixty-four (864) individual servers 22, or a total of eight thousand six hundred forty (8640) gigabits of bandwidth. Using the conventional breakout cable assembly 10 of
The above described systems can employ a number of processes to distribute communications signals. In this regard, an exemplary process for distributing communications signals is described with respect to
Any of the switch devices or other components disclosed herein, such as the switch 60 of
The processing device 120 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device 120 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 120 is configured to execute processing logic in instructions 128 (located in the processing device 120 and/or the main memory 122) for performing the operations and steps discussed herein.
The computer system 118 may further include a network interface device 130. The computer system 118 also may or may not include an input 132 to receive input and selections to be communicated to the computer system 118 when executing the instructions 128. The computer system 118 also may or may not include an output 134, including but not limited to a display, a video display unit (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device (e.g., a keyboard), and/or a cursor control device (e.g., a mouse).
The computer system 118 may or may not include a data storage device 136 that includes instructions 138 stored in a computer-readable medium 140. The instructions 138 may also reside, completely or at least partially, within the main memory 122 and/or within the processing device 120 during execution thereof by the computer system 118, the main memory 122 and the processing device 120 also constituting the computer-readable medium 140. The instructions 128, 138 may further be transmitted or received over a network 142 via the network interface device 130.
While the computer-readable medium 140 is shown in an exemplary embodiment to be a single medium, the term “computer-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “computer-readable medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the processing device and that cause the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term “computer-readable medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical and magnetic medium, and carrier wave signals.
The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.
The embodiments disclosed herein may be provided as a computer program product, or software, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a machine-readable storage medium (e.g., read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage medium, optical storage medium, flash memory devices, etc.).
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an ASIC, a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A controller may be a processor. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The embodiments disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
Further, as used herein, it is intended that terms “fiber optic cables” and/or “optical fibers” include all types of single mode and multi-mode light waveguides, including one or more optical fibers that may be upcoated, colored, buffered, ribbonized and/or have other organizing or protective structure in a cable such as one or more tubes, strength members, jackets or the like.
Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps, or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that any particular order be inferred.
It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the disclosure. Since modifications combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirit and substance of the disclosure may occur to persons skilled in the art, the specification should be construed to include everything within the scope of the appended claims and their equivalents.
