Differential signaling may be used to send serial data over a cable. To increase data transfer rate, two or more differential pairs are may be used in a high-speed serial link.
Alternatively, processor 101 may transfer digital pixel data to video display terminal 102 using any other appropriate communications protocol (such as Low-Voltage Differential Signaling, or LVDS), in which case the number of twisted wire differential pairs which are coupled between processor 101 and video display terminal 102 may be different. These twisted wire differential pairs are used to transmit red, green and blue digital pixel data to video display terminal 102, along with a clock signal for synchronizing the data.
Display terminal 102 includes receiver 107, transmitter 115 and DC offset module 125. Receiver 107 receives incoming digital pixel data and routes the data to row and column driver circuitry within display terminal 102. Transmitter 115 in display terminal 102 receives incoming digital data from peripherals which may be coupled to display terminal 102 and transmits this digital data to processor 101 using DC offset module 125. DC offset module 125 is used to manipulate the DC offsets on two of twisted wire differential pairs 105a-d. When the DC offsets in each of the two twisted wire pairs are compared, the difference between the two DC offsets is used to transmit digital data in a reverse direction.
Both wires in a first pair may have their DC offset adjusted by a small amount while the DC offset in both wires of a second pair remains unchanged. The first DC offset is compared with the second offset in order to communicate digital formation in the reverse direction. Further, both wires in the second pair may have their DC offset adjusted by a small amount while the DC offset in both wires of the first pair remains unchanged. The first DC offset is compared with the second offset in order to communicate digital information in the reverse direction. This allows for the bidirectional transfer of digital data. Digital data is also transferred in a reverse direction over two of the twisted wire differential pairs, 140 and 150.
The invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
In the following description, numerous specific details are set forth. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.
In the common-mode signaling configuration illustrated in
In the example of
In the computer system of
Alternatively, processor 201 may transfer digital pixel data to video display terminal 202 using any other appropriate communications protocol (e.g., LVDS), in which case the number of differential pairs between processor 201 and video display terminal 202 may be different. These differential pairs may be used to transmit red, green and blue digital pixel data to display terminal 202, along with a clock signal for synchronizing the data.
Display terminal 202 includes receiver 207, transmitter 215 and DC offset module 225. Receiver 207 receives incoming data and routes the data to row and column driver circuitry 230. Transmitter 215 in display 202 may receive incoming data from peripherals which may be coupled to display terminal 202 and may transmit this data to processor 201 using DC offset module 225. DC offset module 225 operates to manipulate the DC offsets on two of differential pairs 105a-d. When the DC offsets in each of the two twisted wire pairs are compared, the difference between the two DC offsets is used to transmit digital data from display 202 to processor 201.
Manipulation of the DC offsets by transmitter 215 allows for transmission of data over pairs of differential pairs to create virtual differential pairs 280 and 290. While the transmission is illustrated as from display device 202 to processor 201, a transmitter may be included in processor 201 and a receiver in display device 202 to allow for transmission over the virtual differential pairs from processor 201 to display device 202. Further, bi-directional communications may be supported over the virtual differential pairs.
Both wires in a first pair may have their DC offset adjusted by a small amount while the DC offset in both wires of a second pair remains unchanged. The first DC offset is compared with the second offset in order to communicate digital formation in the reverse direction. Further, both wires in the second pair may have their DC offset adjusted by a small amount while the DC offset in both wires of the first pair remains unchanged. The first DC offset is compared with the second offset in order to communicate digital information in the reverse direction. This allows for the bidirectional transfer of digital data. Digital data is also transferred in a reverse direction over two of the twisted wire differential pairs, 240 and 250.
In order to transmit the additional data transmitter 215 may mix data from a first data stream and a second data stream to generate a signal to be transmitted over a differential pair that represents both data streams via differential data with common-mode signaling. Receiver 210 decodes the differential data and common-mode signaling to recover the two data streams. Using the transmitter circuitry described with respect to
In
Because this common-mode voltage variation in a differential pair does not significantly affect differential data transfer, the differential and common-mode can be independent. Data can be sent data uni-directionally or bi-directionally. A different signal swing can be used for differential and common-mode signals. The signals can have different data rates. In the example of
A current switch circuit driven by D2+ and D2− modulates common-mode of differential pair via resistors R1 and R2. R1 and R2 also serve as differential source termination, thus the ideal value would be half of differential impedance of the cable. Resistors R3 and R4 serve as termination for the common-mode signal, thus the ideal value would be twice the common-mode impedance of the cable for termination impedance matching.
Resistors R5 and R6 extract common-mode voltage. They are also part of differential termination network composed of R3, R4, R5, and R6, thus the ideal value should meet this formula for differential impedance matching with the cable:
Z
differential=(R3+R4)//(R5+R6)
Differential amplifier AMP1 recovers data stream D1, and single-ended amplifier AMP2 recovers data stream D2.
In one embodiment, for HDMI mode, switch S is connected, which causes the receiver to work as a conventional HDMI receiver, getting four differential signal from CLK channel and Data Channel 0,1,2, and delivers CLK, D0, D1, D2 to system. For MHL mode, differential data with common mode clk signal added is applied to Data channel 0, all the other inputs—Clk Channel, Data channel 1 and 2—are floating, also the switch S is disconnected. Then the configuration is the same as described above and recovers CLK and D0.
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
This U.S. patent application claims priority to and incorporates by reference the corresponding U.S. provisional patent application Ser. No. 61/108,757, titled, “INDEPENDENT LINK(S) OVER DIFFERENTIAL PAIRS USING COMMON-MODE SIGNALING,” filed on Oct. 27, 2008.
Number | Date | Country | |
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61108757 | Oct 2008 | US |