Patent Application
20150146824
Implementations described and claimed herein address various problems by facilitating a signaling protocol that does not use a clock signal or a phase locked loop (PLL) to receive and decode symbol data. In accordance with one implementation, a method detects a transition in a signal received via one of a first indexed input and a second indexed input, the transition defining a first symbol having a symbol value. The first symbol is then output, in response to the operation of detecting the transition. The symbol value of the first symbol is designated by the index of the indexed input upon which the transition is detected.
In accordance with another implementation, a signal transition detector circuit is configured to detect a transition in a signal received via one of a first indexed input and a second indexed input. The transition defines a first symbol having a symbol value. A symbol generator circuit is coupled with the signal transition detector and is configured to output the first symbol in response to detection of the transition. The symbol value of the first symbol is designated by the index of the indexed input upon which the transition is detected.
In accordance with another implementation, a method outputs a transition in a signal via one of a first indexed output or a second indexed output. The transition defines a first symbol having a symbol value designated by the index of the indexed output via which the transition is output.
Other implementations are also described and recited herein.
Communication systems often send and receive signals via signaling protocols. In order to transmit and receive data, a clock signal is often used as part of a signaling protocol to synchronize data between a transmitter and a receiver. The clock signal signals the receiver that a new bit of data is available to be read from a data input line. However, a clock signal typically consumes an input pin in an environment in which available pins are becoming increasingly scarce and valuable resources. Moreover, every time a clock signal transitions from one state to another state (e.g., from a low state to a high state or from a high state to a low state), a small amount of radio frequency interference is created. This radio frequency interference can interfere with the operation of a circuit, such as the reception of data at a receiver circuit.
When a clock signal is used as part of a signaling protocol to receive data, the clock signal also influences the speed at which the data can be communicated from a transmitter to a receiver. For example, in the case of a periodic clock signal operating as a square wave, new data bits on a data bus can be clocked into a receiver on every rising edge of the clock signal. The clock signal will then transition low before transitioning high again. The time period between the point where the clock signal transitions low and the point where the clock signal subsequently transitions high can be considered an unused period of time in the signaling protocol. This unused period of time delays message throughput. Moreover, no information is conveyed by the clock signal itself The clock signal merely synchronizes the transfer of data without supplying any data via the clock signal itself.
The disclosed technology utilizes a signaling protocol that does not employ the transmission of a clock signal to a receiver circuit. Moreover, a phase locked loop (which adds complexity and system cost) need not be employed by the receiver circuit. The omission of a clock signal can provide efficiencies that are not possible even with some double data rate (DDR) systems. DDR systems utilize both the rising edge and falling edge of a clock signal to synchronize data.
For example, one implementation of the disclosed technology provides two data lines, although more than two data lines may be employed in other implementations. The first data line is associated with or indexed as the symbol “1” while the second data line is associated with or indexed as the symbol “0.” Any transition, e.g., from low to high or high to low, on the first data line indicates the transmission/receipt of a binary “1” value. Any transition, e.g., from low to high or high to low, on the second data line indicates the transmission/receipt of a binary “0” value. As each transition occurs on the two data lines, the receiver circuit translates the successive transitions into corresponding “1's” and/or “0's” in the order that the transitions are detected on each data line. Thus, a sequence of “1's” and “0's” can be transmitted and received using two data lines without requiring the transmission of a clock signal to the receiver circuit or the use of a PLL at the receiver circuit. Because the clock signal is not transmitted to the receiver circuit, drawbacks associated with the transmission of a clock signal are avoided.
In the example of
The receiver circuit is configured to detect transitions on the data lines and to output a data stream corresponding to the detected sequence of transitions. Thus, for example, the receiver converts the received signals at inputs 110 and 114 into a binary sequence of “1's” and “0's”.
Each T flip-flop operates by transitioning its output if a high signal is received (e.g., clocked-in) at the flip-flop input. Thus, whenever flip-flop 304 receives a high signal clocked-in at input T, the output from output Q is a transition from the previous state of Q. Whenever flip-flop 304 receives a low signal clocked-in at input T, the output from output Q does not change from the previous state of Q.
Thus, flip-flop 304 produces a transition change whenever the output from the shift register is a high value (e.g., a “1”). Because the output from shift register 302 is inverted by inverter 308 before being input into flip-flop 306, flip-flop 306 outputs a transition change whenever a low signal (e.g., a “0”) is output from shift register 302. Thus, for example, if the shift register outputs a low signal, the inverter 308 inverts the low signal to a high signal. When the high signal is clocked-in to input T of flip-flop 306, output Q of flip-flop 306 causes a transition from the previous state of Q. When the shift register outputs a high signal, the inverter 308 inverts the high signal into a low signal. In response to the low signal clocked-in at input T of flip-flop 306, flip-flop 306 does not cause a transition at output Q. In this manner, the combination of the shift register 302 and T flip-flops 304 and 306 serve as signal generating circuitry in the transmitter circuit 300.
The output from flip-flop 304 is transmitted across channel 310 to an indexed input on the receiver circuit 314 that is associated with a “one” signal. The output from flip-flop 306 is transmitted across channel 312 to an indexed input on the receiver circuit 314 that is associated with a “zero” signal. It should be noted that the implementation of the transmitter/receiver system shown in
With a circuit such as that shown in
In accordance with one implementation, a transmitter and receiver system can be configured to use two data lines in either a two-wire legacy system or an indexed communication system. For example, a two-wire legacy system utilizes a clock signal on a first data line and a data signal on a second data line. The data line represents “one” or “zero” depending on whether the voltage is high or low, respectively. The same two data lines could also be used as an indexed communication system, as described herein. Thus, the same two data lines could be used by a transmitter and receiver that are configured with circuits to communicate via both a two-wire legacy system and a two-wire indexed communication system. The transmitter and receiver circuits would simply switch to the agreed communication system in order to be able to communicate—but, the same two data lines would be utilized.
The receiver circuit 400 in
The D flip-flops 418 and 422 are clocked in response to an input signal having a rising edge transition. The D flip-flops 420 and 424 are clocked in response to an input signal having a falling edge transition.
The output of exclusive-or element 406 is the “Most Recent Signal” communicated via input 402 or input 404. The “Most Recent Signal” will be high if the most recent transition received is on input line 402 corresponding to the symbol “1.” The “Most Recent Signal” will be low if the most recent transition received is on input line 404 corresponding to the symbol “0.” Because the output of the exclusive-or element 406 reflects the value of the “Most Recent Signal,” the exclusive-or element 406 is an example of a symbol generator circuit.
In accordance with one implementation, a clock signal may be recovered from the signals received at inputs 402 and 404. Exclusive-or element 410 is used to generate the recovered clock signal. The signals on inputs 402 and 404 are routed to the inputs of exclusive-or element 410. Whenever the input signals transition such that a 1 and 0 combination or 0 and 1 combination are present at the inputs to the exclusive-or element 410, the exclusive-or element 410 will generate a high output signal. Whenever the input signals transition such that there are two low inputs at exclusive-or element 410, the exclusive-or element will generate a low output signal. It should be noted that the implementation of the receiver system shown in
Referring again to
While the operation of an example of a transmitter circuit has been described above at a system level, a transmitter circuit can also be understood by the method that the transmitter circuit performs.
Another output operation 604 transmits a subsequent transition. This subsequent transition immediately follows the previous transition in time (although not necessarily on the same output line). This subsequent transition defines a second symbol having a symbol value. The symbol value of the second symbol is designated by the index of the output line on which the subsequent transition was detected.
An output line can experience multiple transitions in a row. Multiple transitions can occur on the same output line without an intervening transition on another input line. Transitions can also occur on different output lines but in temporal order.
While the operation of an example of a receiver circuit has been described above at a system level, a receiver circuit can also be understood by the method that the receiver circuit performs.
Another detection operation 706 detects a subsequent transition on one of the indexed inputs. This subsequent transition defines a second symbol having a symbol value. The second symbol is designated by the indexed input upon which the subsequent transition is detected. Another output operation 708 outputs the second symbol in response to the detection of the subsequent transition.
The input signals detected by the receiver circuit can be multiple transitions occurring on the same indexed inputs. For example, multiple transitions occurring on the input associated with the symbol “1” will indicate a corresponding sequence of “1's.” In addition, the input signals detected by the receiver circuit can be transitions that occur in temporal sequence but on different indexed inputs.
A derivation operation 710 derives a clock signal from the detected transitions. As noted above, an exclusive-or gate can receive the signals from the indexed inputs and generate a clock signal as an output. This clock signal is considered a half-cycle clock signal because it has half the frequency of the clock used by the transmitter circuit to output the signals that serve as inputs to the receiver circuit.
It should be appreciated that the use of this signaling protocol can reduce the total number of transitions that are employed to communicate data. Because the number of transitions is reduced, the spectral energy and radio frequency interference associated with those transitions is also reduced. This allows for improved transmission quality across low power and bandwidth limited channels. For example, double data rate (DDR) transmission schemes are presently implemented. In addition to the transitions of the data signal itself, a DDR system relies on many transitions of the clock signal as well. Referring to
For example, transmitting two bits of data on a 2 wire DDR interface using one clock line and one data line utilizes four resolution events to communicate two data bits (e.g., data bit #1 arrival, first clock arrival, data bit #2 arrival, second clock arrival). Moreover, the DDR receiver would need to be pre-configured to recognize the order of arrival of signal edges.
Thus, the speed of a DDR receiver is determined by being able to deliver signal edges to the receiver and for the receiver to be able to determine the arrival order.
A two-wire indexed signaling protocol in accordance with one implementation of the present technology need utilize one half the number of resolution events as that of a two-wire DDR protocol. This is due to the fact that the two-wire indexed signaling protocol does not require a clock signal. Assuming that the number of resolution events is the key metric in determining the speed of a communication protocol, a two-wire indexed protocol would be considered to be twice as fast as a two-wire DDR protocol.
Moreover, spectral power density is often a relevant way of assessing a communication protocol. A two-wire indexed signaling protocol in accordance with one implementation of the present technology has ⅔ the spectral power density of a DDR protocol. Thus, less power is required by the two-wire indexed signaling protocol in comparison to a DDR protocol.
The implementations of the technology described herein can be implemented as logical steps in one or more computer systems. The logical operations of the present technology can be implemented (1) as a sequence of processor-implemented steps executing in one or more computer systems and/or (2) as interconnected machine or circuit modules within one or more computer systems. Implementation is a matter of choice, dependent on the performance requirements of the computer system implementing the technology. Accordingly, the logical operations of the technology described herein are referred to variously as operations, steps, objects, or modules. Furthermore, it should be understood that logical operations may be performed in any order, unless explicitly claimed otherwise or unless a specific order is inherently necessitated by the claim language.
While a transmitter and receiver are taught above using discrete circuit elements, it should be understood that the transmitter circuit and/or receiver circuit can be processor based circuits. Data storage and/or memory may be embodied by various types of storage, such as hard disc media, a storage array containing multiple storage devices, optical media, solid-state drive technology, ROM, RAM, and other technology. The operations may be implemented in firmware, software, hard-wired circuitry, gate array technology and other technologies, whether executed or assisted by a microprocessor, a microprocessor core, a microcontroller, special purpose circuitry, or other processing technologies. It should be understood that a write controller, a storage controller, data write circuitry, data read and recovery circuitry, a sorting module, and other functional modules of a data storage system may include or work in concert with a processor for processing processor-readable instructions for performing a system-implemented process.
The above specification, examples, and data provide a complete description of the structure and use of illustrative implementations of the technology. Since many implementations of the technology can be made without departing from the spirit and scope of the technology, the invention resides in the claims hereinafter appended. Furthermore, structural features of the different implementations may be combined in yet another implementation without departing from the recited claims.
