Patent Application
20110109415
The present invention relates to an improved inductor structure, particularly to an improved inductor structure installed on a special substrate and applied to the semiconductor field.
With the progress of the semiconductor technology, most of circuit systems now can be fabricated into a single chip, i.e. the so-called system-on-chip or SOC for short. A system-on-chip usually has oscillation circuits and thus needs capacitors and inductors. For a capacitor or an inductor, the stored energy is proportional to the area of the element. Thus, an inductor having higher inductance needs a greater area. An U.S. Pat. No. 6,600,403 disclosed a planar inductor, wherein a coil is helically formed on a carrier to function as an induction loop. This prior art uses the spiral structure to increase the cross-section area of the equivalent conductor. For achieving a higher inductance, it is necessary to increase the coil length and the winding area. However, a greater winding area in the chip not only reduces the space available to other transistors and the size of the chip but also increases the parasitic capacitance between the carrier and the coil. The higher parasitic capacitance prolongs the delay time of the electronic elements, and decreases the energy-storage efficiency of the planar inductor in a higher-frequency application.
U.S. Pat. No. 7,262,680 and No. 7,173,508 disclosed a vertically-stacked inductor having multiple conductive layers, wherein each conductive layer is arranged by a coil which is spiraled up to form an inductor with multiple conductive layers vertically-stacked, whereby the area of the induced magnetic field is increased and a greater inductance is generated. The vertically-stacked structure does not occupy a too large area of the system-on-chip. Although most elements directly attach to the substrate in a system-on-chip, this prior-art inductor structure does not influence the size of the system-on-chip too much. However, when the area of the induced magnetic field is increased, additional parasitic capacitance is still generated, which inevitably decreases the energy-storage efficiency of the inductor and prolongs the delay time of the circuits.
The primary objective of the present invention is to provide a reduction of module thickness, which can use the same area to achieve greater inductance without occupying additional space of a system-on-chip and raising parasitic capacitance, wherefore the present invention is exempt from decreasing the energy-storage efficiency of the inductor and increasing the delay time of the circuit.
To achieve the abovementioned objective, the present invention proposes an improved inductor structure, which applies to the semiconductor field, particularly to a system-on-chip, and which comprises a substrate, a first conductive patterned film, and a first insulating layer formed between the substrate and the first conductive patterned film. The substrate has a base and an accommodation portion formed on the base. A magnetic material is filled into the accommodation portion to form a magnetic region. The accommodation portion is fabricated via etching the base or drilling the base.
As mentioned above, the conventional technology increases the area of elements or vertically stacks the coils to increase the inductance. However, the present invention uses the characteristic of the electromagnetism of the magnetic region to enhance the mutual induction between the substrate and the first conductive patterned film. Therefore, the present invention can increase the inductance without occupying additional space of the system-on-chip.
Below, the technical contents of the present invention will be described in detail in cooperation with the drawings.
Refer to
In the embodiment, the accommodation portion 12 is fabricated via drilling a through-hole on the base 11. After the circuit patterned conductive film is formed with a photolithographic technology and an etching technology, a through-hole is drilled on the other side of the substrate 10, which is opposite to the first conductive patterned film 20, to form the accommodation portion 12. Then, a magnetic material is filled into the accommodation portion 12 to form the magnetic region 13.
A plurality of conductive wires 21 is arranged in a spiral way to form the first conductive patterned film 20. The fist conductive patterned film 20 has a plurality of gaps 22. The protective layer 40 overlays on the first conductive patterned film 20 and connects with the first insulating layer 30 through the gaps 22. The protective layer 40 is made of polyimide and isolates the contact of the first conductive patterned film 20 and moisture. The protective layer 40 has superior thermal stability, cryogenic resistance, tensile strength and abrasion resistance. Therefore, the protective layer 40 can prevent that a minor warpage cracks the substrate 10 and that a collision abrades the substrate 10.
In the embodiment, the position and dimension of the magnetic region 13 are corresponding to the position and dimension of the first conductive patterned film 20. In the same embodiment, the accommodation portion 12 is located exactly below the first conductive patterned film 20 and corresponding to the position and dimension of the first conductive patterned film 20. The magnetic region 13 inside the accommodation portion 12 can enhance the mutual induction between the substrate 10 and the first conductive patterned film 20 and thus increase the inductance. Therefore, the present invention can achieve a higher inductance without occupying additional space of the system-on-chip.
Refer to
Refer to
Refer to
In the conventional technologies, the inductance is increased via increasing the area of the elements or vertically stacking the elements. The improved inductor structure of the present invention uses the characteristic of the electromagnetism of the magnetic region formed on the substrate to enhance the mutual induction between the substrate and the first conductive patterned film and thus increase the inductance. In the present invention, the multi-layer structure of the second conductive patterned films and the second insulating layers can further increase the mutual induction. Therefore, the present invention can achieve a higher inductance without occupying additional space of the system-on-chip. As the conventional technologies usually have to increase the induction area of the inductor, the parasitic capacitance becomes very great. Because of the parasitic capacitor, the response speed of the electronic circuit is delayed in the conventional technologies. Nevertheless, the present invention can achieve greater inductance than the conventional inductor element without increasing the induction area. Therefore, the present invention will not increase the delay time caused by the parasitic capacitor.
The embodiments described above are only to exemplify the present invention but not to limit the scope of the present invention. Any equivalent modification or variation according to the spirit of the present invention is to be also included within the scope of the present invention.
