Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample

Abstract

An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 13/935,391, filed Jul. 3, 2013, entitled “ADAPTATION OF CROSSING DFE TAP WEIGHT,” with, which is herein incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

Often times high-speed serial data streams are sent without an accompanying clock signal. Clock and data recovery (CDR) methods allow for a receiver to generate a clock from an approximate frequency reference. As input/output speeds become higher, the data sampling point used by CDR becomes increasingly critical to the link performance. The sampling point is typically determined by bang-bang CDR, where the settling point may not be where the vertical eye opening is largest or at the middle of the eye. As a result, the sampling point may not be optimal and signal integrity issues may arise.

BRIEF SUMMARY OF THE INVENTION

Accordingly, a need exists for an apparatus and method to manipulate the CDR settling point to in an effort achieve an optimum sampling phase. Embodiments of the present invention disclose an apparatus and method for influencing a clock and data recovery settling point (CDR settling point) of a data sampling point signal by applying decision feedback equalization (DFE) on an input signal to produce a DFE output signal which is fed to a sampler which is clocked by the edge sample recovery clock. The sampler produces an edge sample signal. The edge sample signal is then used to influence the CDR settling point of a data sampling point sign.

More specifically, embodiments of the present invention are directed towards an apparatus comprising: a first module coupled to an input signal and operable to generate an edge signal using a first clock signal; and a second module operable to receive said edge signal and further operable to generate a data sampling phase signal, wherein said edge signal influences a settling point of said data sampling phase signal.

Embodiments include above and further comprising: a third module operable to generate a data sample signal using a second clock signal; and a fourth module operable to generate an error sample signal using a third clock signal and wherein said first module is a decision feedback equalizer.

Embodiments include the above and wherein said first module further comprises: a first path coupled to said input signal, said first path comprising: a first preamplifier; a first summing node coupled to said first preamplifier; and a first latch coupled to said first summing node and said first clock signal; a second path coupled to said input signal, said second path comprises: a second preamplifier; a summing node coupled to said second preamplifier and operable to apply feedback to its input signal based on a previously generated data sample; and a second latch coupled to said second summing node; and a multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples.

Embodiments include the above and wherein said first module further comprises: a first path coupled to said input signal, said first path comprising: a first preamplifier; a first summing node coupled to said first preamplifier and operable to apply a first feedback to its input signal based on a previously generated data sample; and a first latch coupled to said first summing node; a second path coupled to said input signal, said second path comprising: a second preamplifier; a second summing node coupled to said second preamplifier and operable to apply a second feedback to its input signal based on a previously generated data sample; and a second latch coupled to said second summing node; and a multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples.

Embodiments include the above and wherein said first module further comprises: a first path coupled to said input signal, said first path comprising: a first preamplifier operable to offset said input signal by a first predefined constant value; a first summing node coupled to said first preamplifier; and a first latch coupled to said summing node; a second path coupled to said input signal, said second path comprising: a second preamplifier operable to offset said input signal by a second predefined constant value; a second summing node coupled to said second preamplifier; a second latch coupled to said second summing node; and a multiplexer coupled to said first latch and said second latch, said multiplexer operable to select between an output of said first latch and said second latch based on a previously generated data sample.

Embodiments include the above and wherein said second module comprises: a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom; a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; and a phase interpolator coupled to said loop filter operable to generate said data sampling phase based upon said phase code.

The invention also includes a receiver embodiment, the receiver includes a first module coupled to receive an input signal and operable to employ Decision Feedback Equalization to an input signal and generate an edge sample signal. The receiver also includes a timing recovery module coupled to the first module and operable to receive the edge signal and generate a data sampling phase signal, wherein the edge signal influences a settling point of the data sampling phase signal.

In another embodiment, the present invention is drawn towards a method. The method comprising: receiving an input signal at an input of a receiver; applying decision feedback equalization (DFE) to said input signal based on prior recovered data values to generate an output DFE signal; using a sample module clocked by an X clock signal, sampling said output DFE signal to generate an edge sample signal; and using said edge sample signal to influence a settling point of a data sampling signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements.

FIG. 1 shows an exemplary computer system, in accordance with one embodiment of the present invention.

FIG. 2 shows an exemplary receiver, in accordance with one embodiment of the present invention, for applying DFE techniques to an input signal to recover an edge sample signal.

FIG. 3A shows an exemplary DFE block comprising constant offset blocks, buffers, and latches, in accordance with one embodiment of the present invention.

FIG. 3B shows an exemplary DFE block comprising a constant offset block, a feedback block, and a latch, in accordance with one embodiment of the present invention.

FIG. 3C shows an exemplary DFE block comprising a constant offset block, a feedback block, and a latch, in accordance with one embodiment of the present invention.

FIG. 4 shows an exemplary timing recovery module, in accordance with one embodiment of the present invention.

FIG. 5 shows a truth table used by a phase detector, in accordance with one embodiment of the present invention.

FIG. 6 shows an exemplary circuit employing DFE, in accordance with one embodiment of the present invention, to recover an edge sample signal.

FIG. 7 shows a flowchart of an exemplary computer controlled process employed by a receiver to apply DFE techniques to an input signal for recovery of an edge sample signal that will be used to influence a CDR settling point.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the present invention will be discussed in conjunction with the following embodiments, it will be understood that they are not intended to limit the present invention to these embodiments alone. On the contrary, the present invention is intended to cover alternatives, modifications, and equivalents which may be included with the spirit and scope of the present invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, embodiments of the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

FIG. 1 shows an exemplary computer system 100 in accordance with one embodiment of the present invention. Computer system 100 depicts the components in accordance with embodiments of the present invention providing the execution platform for certain hardware-based and software-based functionality, in particular, computer graphics rendering and display capability. In general, computer system 100 comprises a system board 106 including at least one central processing unit (CPU) 102 and a system memory 104. The CPU 102 can be coupled to the system memory 104 via a memory controller 120. In an embodiment, system memory 104 may be DDR3 SDRAM.

Computer system 100 also comprises a graphics subsystem 114 including at least one graphics processor unit (GPU) 110. For example, the graphics subsystem 114 may be included on a graphics card. The graphics subsystem 114 may be coupled to a display 116. One or more additional GPU(s) 110 can optionally be coupled to computer system 100 to further increase its computational power. The GPU(s) 110 may be coupled to the CPU 102 and the system memory 104 via a communication bus 108. The GPU 110 can be implemented as a discrete component, a discrete graphics card designed to couple to the computer system 100 via a connector (e.g., AGP slot, PCI-Express slot, etc.), a discrete integrated circuit die (e.g., mounted directly on a motherboard), or as an integrated GPU included within the integrated circuit die of a computer system chipset component (not shown). Additionally, memory devices 112 may be coupled with the GPU 110 for high bandwidth graphics data storage, e.g., the frame buffer. In an embodiment, the memory devices 112 may be dynamic random-access memory. A power source unit (PSU) 118 may provide electrical power to the system board 106 and graphics subsystem 114.

The CPU 102 and the GPU 110 can also be integrated into a single integrated circuit die and the CPU and GPU may share various resources, such as instruction logic, buffers, functional units and so on, or separate resources may be provided for graphics and general-purpose operations. The GPU may further be integrated into a core logic component. Accordingly, any or all the circuits and/or functionality described herein as being associated with the GPU 110 can also be implemented in, and performed by, a suitably equipped CPU 102. Additionally, while embodiments herein may make reference to a GPU, it should be noted that the described circuits and/or functionality can also be implemented and other types of processors (e.g., general purpose or other special-purpose coprocessors) or within a CPU.

System board 106 also includes a receiver device 121, in accordance with embodiments of the present invention, which may be placed on any communication link at the receiver end. As shown, receivers 121 are placed on the receiver ends of bidirectional communication link 108 (between CPU 102 and GPU 110) and communication link 130 (between GPU 110 and memory) and communication link 140 (between GPU 110 and the display). It is appreciated that these communication links are exemplary. Communication device 121 is operable to receive data (See FIG. 2). The receiver may be either local or remote to system 100.

System 100 can be implemented as, for example, a desktop computer system or server computer system having a powerful general-purpose CPU 102 coupled to a dedicated graphics rendering GPU 110. In such an embodiment, components can be included that add peripheral buses, specialized audio/video components, IO devices, and the like. Similarly, system 100 can be implemented as a portable device (e.g., cellphone, PDA, etc.), direct broadcast satellite (DBS)/terrestrial set-top box or a set-top video game console device such as, for example, the Xbox®, available from Microsoft Corporation of Redmond, Wash., or the PlayStation3®, available from Sony Computer Entertainment Corporation of Tokyo, Japan. System 100 can also be implemented as a “system on a chip”, where the electronics (e.g., the components 102, 104, 110, 112, and the like) of a computing device are wholly contained within a single integrated circuit die. Examples include a hand-held instrument with a display, a car navigation system, a portable entertainment system, and the like.

Influence Clock Data Recovery Settling Point by Applying Decision Feedback Equalization to a Crossing Sample

FIG. 2 shows an exemplary communication receiver 200, in accordance with one embodiment of the present invention. Receiver 200 is operable to receive an input signal 224. Typically, input signal 224 may be generated and transmitted via a transmitter (not shown). The transmitter may be remote or local.

Receiver 200 comprises a first circuit branch 226, second circuit branch 228, and a third circuit branch 230. Branch 226 is clocked by an x_clock signal 270. The x_clock signal 270 is the signal used to recover the edge sample signal 248. Branches 228 and 230 are clocked by the d_clock signal 272 which is used to recover the data sample signal and the error sample signal. In an embodiment, receiver 200 may comprise an odd path 232 and an even path 234, wherein both odd path 232 and even path 234 each comprise first circuit branch 226, second circuit branch 228 and third circuit branch 230. Both odd path 232 and even path 234 may simultaneously process a signal while odd path 232 operates on data of a first clock cycle and even path 234 operates on data of a second clock cycle. It is appreciated that the odd path is clocked by complement clocks, e.g., x_clock (bar) and d_clock (bar).

It is appreciated that first circuit branch 226 comprises a decision feedback equalization (DFE) block 220 coupled to a multiplexer 222. DFE block 220 is operable to apply DFE techniques to an input signal 224. Upon applying DFE to input signal 224, a DFE output is generated which is then sampled according to a sampler clocked by the x_clock 270, the result of this signal is then multiplexed via multiplexer 222 to produce an edge sample signal 248. Multiplexer 222 selects a single signal out of two or more outputs of DFE block 220. Branch 228 and 230 may also employ DFE techniques, e.g., h1 blocks.

The edge sample signal 248 is then transmitted to and used by a timing recovery module (See FIG. 4). The generated edge sample signal is then used to influence a clock and data recovery (CDR) settling point, described further below.

Second circuit branch 228, receives the d_clock 272 and comprises an h0 constant block 236, an h1 feedback block 238 (based on a prior received data bit), and a latch 240. Second circuit branch 228 is operable to generate an error sample signal based on the input signal 224. In an embodiment, h0 constant block 236 is subtracted from its incoming signal.

Third circuit branch 230, receives the d_clock 272 and comprises a buffer 242, h1 feedback block 238 (based on a prior received data bit), and a latch 240. Third circuit branch 230 is operable to generate a data sample signal based on the input signal 224.

In an embodiment, receiver 200 may also comprise a continuous time linear equalizer (CTLE) 242, h2 feedback 244, and an infinite impulse response (IIR) filter 246. CTLE 242, h2 244, and IRR 246 may be applied to input signal 224 prior to splitting input signal 224 into first circuit branch 226, second circuit branch 228, and third circuit branch 230. CTLE 242 is configured to shape an input pulse response to compensate for feedback from the DFE.

FIG. 3A shows an exemplary DFE block 220, which receives the x_clock 270, and comprises constant hx offset blocks 348, buffers 242, and latches 240, in accordance with one embodiment of the present invention. FIG. 3A is depicted as a shorthand block diagram of expressing the processing on the input signal to arrive at the edge sample signal 248. DFE block 220 applies DFE techniques to input signal 224 (FIG. 2). DFE block 220 comprises a first path 350 and a second path 352.

DFE block 220 offsets the input signal during a constant column 354 and applies feedback to the input signal during a feedback column 356.

First path 350 and second path 352 receive the input signal. In the constant column 354, first path 350 applies a +hx constant offset 348 (subtraction) to reduce the input signal, operable to offset (reduce) the input signal by a predetermined constant value. The input signal may be offset by a positive constant value or a negative constant value. In this case, hx may be 5 mV and the processed input signal may be offset (reduced) by 5 mV. In the constant column 354, second path 352 applies a −hx constant offset 348 to the input signal, operable to offset (reduce) the input signal by a predetermined value. In this case, reduction by a negative acts to add to the signal. In this case, hx may be −5 mV and the input signal may be offset (reduced) by −5 mV thereby adding 5 mV.

During the feedback column 356, neither first path 350 nor second path 352 apply any feedback to the signal. Rather, buffer 242 delays or buffer the signal for a predetermined amount of time.

Latches 240 are operable to sample the signal and store its value prior to multiplexer 222 selecting either the output of latch 240 from first path 350 or second path 352. Multiplexer 222 selects either an output between first path 350 or second path 352 based on logic attributed to its select line. In this particular embodiment, a select value of multiplexer 222 will be equal to one if a prior data value (dk−1) is equal to 1. In this case, first path 350 will be selected by the multiplexer 222 and will be output as the edge signal 248. Otherwise, if a prior data value (dk−1) is not equal to 1, second path 352 will be selected by the multiplexer 222 and will be output as the edge signal 248.

FIG. 3B shows an exemplary DFE block 220, receiving the x_clock signal 270, and comprising constant hx feedbacks 348, buffers 242, and latches 240, in accordance with one embodiment of the present invention. FIG. 3B is depicted as a shorthand method of expressing the processing on the input signal. DFE block 220 applies DFE techniques to input signal 224 (FIG. 2). DFE block 220 comprises a first path 350 and a second path 352.

DFE block 220 offsets the signal during a constant column 354 and applies feedback to the signal during a feedback column 356.

First path 350 and second path 352 receive the input signal. During the constant column 354, neither first path 350 nor second path 352 apply any constant offset to the signal. Rather, buffers 242 stall the signal for a predetermined amount of time.

During the feedback column 356, first path 350 applies (subtraction) a −hx feedback 348 (based on a prior received data bit) to the signal, thereby applying DFE techniques to the signal. Second path 352 applies (subtracts) a hx feedback 348 to the signal. Both −hx and hx feedback 348 are feedback based on a prior data value.

Latches 240 are operable to sample the signal and store its value prior to multiplexer 222 selecting either the output of latch 240 from first path 350 or second path 352. Multiplexer 222 selects either an output between first path 350 or second path 352 based on logic attributed to its select line. In this particular embodiment, a select value of multiplexer 222 will be equal to the result of an exclusive OR operation with a first and a second prior data values. In this case, first path 350 will be selected by the multiplexer 222 and will be output as the edge signal 248 if the result of the exclusive OR operation is 1. Otherwise, if the result of the exclusive OR operation is zero, second path 352 will be selected by the multiplexer 222 and will be output as the edge signal 248.

FIG. 3C shows an exemplary DFE block 220, receiving the x_clock signal 270 and comprising a buffer 242, hx feedback 348, and latches 240, in accordance with one embodiment of the present invention. FIG. 3B is depicted as a shorthand method of expressing the processing on the input signal. DFE block 220 applies DFE techniques to input signal 224 (FIG. 2). DFE block 220 comprises a first path 350 and a second path 352.

DFE block 220 offsets the signal during a constant column 354 and applies feedback to the input signal during a feedback column 356.

First path 350 and second path 352 receive the signal. During the constant column 354, neither first path 350 nor second path 352 apply any constant offset to the signal. Rather, buffers 242 delay the signal for a predetermined amount of time.

During the feedback column 354, first path 350 uses buffer 242 to stall the signal, thereby applying no feedback to the signal. Second path 352 applies (subtracts) a hx feedback 348 to the signal, thereby applying DFE techniques to the signal. hx feedback 348 is feedback based on a prior data value.

Latches 240 are operable to sample the signal and store its value prior to multiplexer 222 selecting either the output of latch 240 from first path 350 or second path 352. Multiplexer 222 selects either an output between first path 350 or second path 352 based on logic attributed to its select line. In this particular embodiment, a select value of multiplexer 222 will be equal to the result of an exclusive OR operation with a first and a second prior data values. In this case, first path 350 will be selected by the multiplexer 222 and will be output as the edge signal 248 if the result of the exclusive OR operation is 1. Otherwise, if the result of the exclusive OR operation is zero, second path 352 will be selected by the multiplexer 222 and will be output as the edge signal 248.

FIG. 3A, FIG. 3B, and FIG. 3C demonstrate three exemplary embodiments of DFE block 220 in accordance with the present invention. Typical latch 240 input is:

$r\left(t\right)=\sum _{i=-\infty }^{\infty }\left(d_i·g\left(t-i·T\right)\otimes h\left(t\right)\right)=\sum _{i=-\infty }^{\infty }\left(d_i·p\left(t-i·T\right)\right)$

Where p(t) is the equalized pulse response at the latch input. It includes the circuit branch and the equalizers at both a transmitter and the receiver 200 (CTLE, DFE, IIR, etc.).

The latch 240 samples are obtained by sampling latch 240 input at a data or crossing sampling phase:r_k-δ=r(t)|_{i=(k-δ)·T-τk}=Σ_i=−∞^∞(d_i·p((k−δ−i)·T−τ_k))=Σ_i=−∞^∞(d_i·P_k-δ-i^k)=Σ_j=−∞^∞(d_k-j·Pj-δ^k)=Σ_j=−∞^∞(d_k-j·p_j-δ)  (3)

Here τ_k is the data sampling phase at the kth symbol, δ is the IQ offset (in the unit of UI). For data samples, δ=0. When the CDR changes the data sampling τ_k, the samples of pulse response P_j-δ^k change with it. When the CDR moves left, p₁ increases and p₋₁ decreases even for the same latch.

The closed form expression of the latch sample derived is the foundation of the analysis of the CDR settling point. It also the basis of the equalizer design.

Taking DFE as an example (data equalization), without DFE the data latch sample can be obtained by equation (3) by setting δ=0

$r_k=\sum _{j=-\infty }^{\infty }{d}_{k-j}·p_j$

From the expression it is clear that there exists inter-symbol interference (ISI) from the data symbols both in the past and the future. By using DFE with N taps (data equalization), one can reduce the ISI in the data latch sample. When h_j=p_j, the residual ISI from the corresponding data symbol can be eliminated. Here, p_j is the pulse response sample at the DFE input.

$r_k-\sum _{i=1}^N\left(h_i·d_{k-i}\right)=\sum _{j=-\infty }^{-1}{d}_{k-j}·p_j+p_0·d_k+\sum _{j=1}^N\left(p_j-h_j\right)·d_{k-j}+\sum _{j=N+1}^{\infty }{d}_{k-j}·p_j$

For crossing latch samples, there also exists ISI from the data symbols both in the past and in the future. This is apparent from the equation above. One should note that the interferences are from the data symbols, not from other crossing latch outputs. The pulse response samples p_j-δ will be obtained at the sampling points of the cross latch, rather than that of the data latch. For example, if δ=0.4 the crossing ISI isτ_k-0.4= . . . +p_−0.4·d_k+p_0.6·d_k-1+p_1.6·d_k-2+ . . .

However, reducing the crossing ISI does not have direct impact on the data latch output or even the zero crossings of the data latch input eye. Hence what matters to the data latch is how the CDR settling point is impacted by the ISI in the crossing latch samples.

FIG. 4 shows an exemplary timing recovery module 400, in accordance with one embodiment of the present invention. Timing recovery module 400 is coupled to receiver 200 (FIG. 2) and receives edge sample signal 248 from receiver 200 (FIG. 2) and also receives the data sample signal. Timing recovery module 400 includes phase detector 454, loop filter 456, and phase interpolator 458.

Phase detector 454 receives edge sample signal 248 and data signals from receiver 200 (FIG. 2). Data signals include a current data value and a prior data value. Phase detector 454 is operable to generate a plurality of delta phases 460 based on the received edge signal 248, a current data value, and a prior data value.

Loop filter 456 is coupled to phase detector 454. Loop filter 456 receives the delta phases 460 generated by phase detector 454 and averages the delta phases 460 to generate a phase code 462. Loop filter 456 inherently functions as an adder, accumulator, and loop gain control.

Phase interpolator 458 is coupled to loop filter 456 and receives the phase code 462 generated by loop filter 456. Phase interpolator 458 interpolates the phase code 462 based upon values contained within a lookup table and generates a data sampling phase 464 therefrom. Interpolation or lookup table processing may be used interchangeably. Data sampling phase 464 settles at a point to become the clock and data recovery settling point (CRD settling point). Thus, effectively, the edge sample signal influences the clock and data recovery settling point of the data sampling phase 464 in accordance with embodiments of the present invention.

Bang-bang CDR adjusts the phase based on the triplet (d_k, x_k, d_k-1) where x_k is the crossing latch output with a sampling phase between that of d_k-1 and d_k. From the truth table (See FIG. 5), it is appreciated that bang-bang CDR is equivalent to the sign-sign version of a one-tap edge equalizer. It follows that what bang-bang CDR attempts to do is to adjust the sampling phase such that the term related to d_k-1 (the first crossing ISI tap) is minimized.

FIG. 5 shows a truth table 500 used by a phase detector 454 (FIG. 4), in accordance with one embodiment of the present invention. Truth table 500 is used by phase detector 454 (FIG. 4) in determining the delta phases as a function of the edge signal 248 (FIG. 2), a current data value (d_k), and a prior data value (d_k-1). Truth table 500 may be stored within memory 104 (FIG. 1) of system 100 (FIG. 1).

Timing recovery module 400 demonstrates a typical CDR loop. A first order CDR loop filter consists of two stages. The first stage of the loop filter provides a constant divide ratio or proportional gain μ. The divide ratio is large enough (or μ is small enough) that (Σμ·x_k·d_k-1)˜E[x_k·d_k-1]. The accumulation in the formula is achieved by the phase integrator in the 2^nd stage of the loop filter, which increments or decrements the phase code by 1 (or a fixed step size) or decrements it by 1 based on the output of the first stage.

To facilitate the analysis of the CDR settling point, the phase detector is replaced with equivalent gradient x_k·d_k-1. When the long term average of x_k·d_k-1 is 0, the phase code will not change or simply dither between two adjacent values. Consequently, the CDR phase settles to where the long term average of x_k·d_k-1 is 0.

Building on equation (3) and the relationship between CDR and equalizer, we can derive a closed-form expression for the CDR settling point. It follows from equation (3) that when there is a transition between the current data symbol and the previous one,

$\begin{array}{c}{r}_{k-\delta }·d_{k-1|d_k=-d_{k-1}}=\sum _{j=-\infty }^{\infty }\left(d_{k-j}·p_{j-\delta }\right)·d_{k-1|d_k=-d_{k-1}}\\ =\left(p_{1-\delta }-p_{-\delta }\right)·d_{k-1}^2+\sum _{j=-\infty ,j\ne 0,1}^{\infty }\left(p_{j-\delta }·d_{k-j}·d_{k-1}\right)\\ =p_{1-\delta }-p_{-\delta }+\Delta \end{array}$

where r_k-δ is the crossing latch sample andΔ=Σ_{j=−∞,j≠0.1}^∞(p_j-δ·d_k-j·d_k-1).

If the data symbols are independent and identically distributed, the long term average of is r_k-δ·d_k-1 is p_1-δ−p_−δ. In addition, r_k-δ·d_k-1 is symmetric around it, with equal number of values above and below it.

If the crossing latch threshold is 0, the latch output x_k·d_k-1=sgn(r_k-δ)·d_k-1=sgn(r_k-δ·d_k-1).

The long term average x_k·d_{k 1} of is zero if and only if there are equal number of r_k-δ·d_k-1 above and below 0. When p_−δ=p_1-δ, this is true. However, even p_−δ=p_1-δ, as long as the two r_k-δ·d_k-1 values closest to p_1-δ=p_−δ have different polarities, there will still be equal number of r_k-δ·d_k-1 above and below 0. As a result, bang-bang CDR will settle to a zone centered at p_−δ=p_1-δ.

One should note that p_−δ the sample of the pulse response seen by the crossing latch, not that seen by a data latch if they are different. For baud-rate CDR, using equation (e) and going through a similar analysis, we can express its settling point as p₋₁−p₁.

Once the closed-form expression of the CDR settling point is known, e.g. p_−δ=p_1-δ, it is apparent what can be done to influence its settling point. If the IQ offset δ is changed, the CDR settling point will change as a result.

FIG. 6 shows an exemplary circuit 600 employing DFE, in accordance with one embodiment of the present invention on the input signal to arrive at an edge sample signal. Circuit 600 demonstrates an embodiment of implementing the present invention. Circuit 600 includes an odd sampler circuit and even sampler circuit.

FIG. 6 shows an exemplary circuit 600 employing DFE, in accordance with one embodiment of the present invention on the input signal to arrive at an edge sample signal. Circuit 600 demonstrates an embodiment of implementing the present invention. Circuit 600 includes an odd sampler and an even sampler circuits.

Odd sampler circuit corresponds to circuit 220 of FIG. 2. It receives the X_clock signal 270 and applies DFE techniques to the input signal which is passed through a preamplifier. The output of the DFE is then passed to a sense amplifier circuit which is clocked by the X_clock signal 270. The output of the ODD sampler circuit is then the edge sample circuit. It is appreciated that Odd sampler circuit could also be replaced with an even sampler circuit in this embodiment. In this embodiment, both circuits of FIG. 6 would be even.

The Even Sampler circuit of the lower portion of FIG. 6 corresponds to branches 228 and 230 of FIG. 2 and receives the d_clock signal 272 and produces the error and data sample signals as described above.

More specifically, the even data sampler receives a feedback from a prior data value (d_k-1) and offsets it by a constant +h1·d_k-1. It is then summed with Vin from a preamp circuit and propagated through the rest of the circuit. Similarly, the even data sampler transmits a feedback from a prior data value (d_k-2) to the even edge sampler. The feedback is used to create an offset by an amount +hx·d_k-2 and summed with Vin from a preamp circuit. The even data sampler receives DCLK 272 and the even edge sampler receives XCLK 270. This embodiment is specific to half-rate Rx implementations however the invention could equally be used in full-rate Rx designs.

FIG. 7 shows a flowchart of an exemplary receiver implemented process of influencing a CDR settling point by applying DFE techniques to an input signal which produces and edge sample signal, in accordance with one embodiment of the present invention. In block 702, an input signal is received at an input of a receiver. For example, in FIG. 2, the input signal is received at the input of the receiver. Subsequently, CTLE, h2 feedback, and a IIR filter are applied to the signal prior to splitting the signal into a first circuit branch, second circuit branch, and third circuit branch.

In block 706, decision feedback equalization (DFE) is applied to the input signal based on prior recovered data values to generate an output DFE signal. This output DFE signal is then fed to a sampler that is clocked by the x_clock to produce an edge sample signal. For example, in FIG. 2, and in FIG. 6 the DFE circuit blocks apply DFE techniques to the input signal to recover the edge sample signal. The multiplexer selects one out of a plurality of outputs from the DFE block based on a logic function, the output of which is the edge sample signal.

In block 708, the edge sample signal is used to influence a settling point of a data sampling signal. For example, in FIG. 4, the edge sample signal is received by the timing recovery module. The timing recovery module uses a phase detector to generate delta phases based on the edge signal, a current data value, and a prior data value. The loop filter then averages the delta phases to generate a phase code. The phase interpolator uses the phase code and a look-up table to interpolate the phase code and generate a data sampling phase. The data sampling phase eventually settles into a clock and data recovery settling point. Thus, the DFE techniques used to produce the edge sample signal influence the clock and data recovery settling point of the receiver.

In an embodiment, the receiver may also comprise a continuous time linear equalizer (CTLE) configured to shape an input pulse response to compensate for feedback from the DFE.

In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. Thus, the sole and exclusive indicator of what is, and is intended by the applicants to be, the invention is the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. Hence, no limitation, element, property, feature, advantage, or attribute that is not expressly recited in a claim should limit the scope of such claim in any way. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

In an embodiment, the zero crossing signal may be offset by a predetermined constant.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings.

Claims

1. An apparatus comprising: a first module coupled to an input signal and operable to generate an edge signal using a first clock signal, wherein said first module further comprises: a first path coupled to said input signal, said first path comprising: a first preamplifier;a first summing node coupled to said first preamplifier; anda first latch coupled to said first summing node and said first clock signal;a second path coupled to said input signal, said second path comprises: a second preamplifier;a summing node coupled to said second preamplifier and operable to apply feedback to its input signal based on a previously generated data sample; anda second latch coupled to said second summing node; anda multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples; anda second module operable to receive said edge signal and further operable to generate a data sampling phase signal, wherein said edge signal influences a settling point of said data sampling phase signal.

2. The apparatus of claim 1 further comprising: a third module operable to generate a data sample signal using a second clock signal; anda fourth module operable to generate an error sample signal using a third clock signal and wherein said first module is a decision feedback equalizer.

3. The apparatus of claim 1 wherein said second module comprises: a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom;a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; anda phase interpolator coupled to said loop filter operable to generate said data sampling phase based upon said phase code.

4. The apparatus of claim 3 wherein said plurality of delta phases are generated as a function of said edge sample signal, a current data sample, and a prior data sample.

5. The apparatus of claim 1 further comprising a plurality of said first modules, wherein each of said plurality of modules operates on its own set of clocks.

6. The apparatus of claim 1 further comprising a linear equalizer configured to shape an input pulse response.

7. A receiver for arriving at a clock and data recovery settling point of a data sampling point signal, said apparatus comprising: a first module coupled to receive an input signal and operable to employ decision feedback equalization (DFE) on the input signal and operable to generate an edge sample signal therefrom using a first clock signal, wherein said first module further comprises: a first branch coupled to said input signal, said first path comprising: a first preamplifier;a first summing node coupled to said first preamplifier; anda first latch coupled to said first summing node and said first clock signal;a second branch coupled to said input signal, said second path comprises: a second preamplifier;a summing node coupled to said second preamplifier and operable to apply feedback to its input signal based on a previously generated data sample; anda second latch coupled to said second summing node; anda multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples; anda timing recovery module coupled to said first module and operable to receive said edge sample signal and generate a data sampling phase signal based on said edge sample signal.

8. The receiver of claim 7 wherein said first module comprises: wherein said first branch is operable to apply DFE to said input signal to generate said edge sample signal using said first clock signal, wherein said edge sample signal influences a settling point of said data sampling signal;wherein said second branch is operable to generate an error sample signal using a second clock signal; anda third branch comprising said multiplexer operable to generate a data sample signal using a third clock signal.

9. The receiver of claim 7 wherein said timing recovery module comprises: a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom;a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; anda phase interpolator coupled to said loop filter operable to generate said phase code based upon values contained within a lookup table and further operable to generate said data sampling phase signal.

10. The receiver of claim 7 wherein said first module further comprises an odd path and an even path simultaneously processing, wherein further said odd path uses a first clock cycle and said even path uses a second clock cycle.

11. An apparatus comprising: a first module coupled to an input signal and operable to generate an edge signal using a first clock signal; wherein said first module further comprises: a first path coupled to said input signal, said first path comprising: a first preamplifier;a first summing node coupled to said first preamplifier and operable to apply a first feedback to its input signal based on a previously generated data sample; anda first latch coupled to said first summing node;a second path coupled to said input signal, said second path comprising: a second preamplifier;a second summing node coupled to said second preamplifier and operable to apply a second feedback to its input signal based on a previously generated data sample; anda second latch coupled to said second summing node; anda multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples; anda second module operable to receive said edge signal and further operable to generate a data sampling phase signal, wherein said edge signal influences a settling point of said data sampling phase signal.

12. The apparatus of claim 11 further comprising: a third module operable to generate a data sample signal using a second clock signal; anda fourth module operable to generate an error sample signal using a third clock signal and wherein said first module is a decision feedback equalizer.

13. The apparatus of claim 11, wherein said second module comprises: a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom;a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; anda phase interpolator coupled to said loop filter operable to generate said data sampling phase based upon said phase code.

14. The apparatus of claim 13, wherein said plurality of delta phases are generated as a function of said edge sample signal, a current data sample, and a prior data sample.

15. The apparatus of claim 14, further comprising a plurality of said first modules, wherein each of said plurality of modules operates on its own set of clocks.

16. The apparatus of claim 14, further comprising a linear equalizer configured to shape an input pulse response.

17. An apparatus comprising: a first module coupled to an input signal and operable to generate an edge signal using a first clock signal, wherein said first module further comprises: a first path coupled to said input signal, said first path comprising: a first preamplifier operable to offset said input signal by a first predefined constant value;a first summing node coupled to said first preamplifier; anda first latch coupled to said summing node;a second path coupled to said input signal, said second path comprising: a second preamplifier operable to offset said input signal by a second predefined constant value;a second summing node coupled to said second preamplifier;a second latch coupled to said second summing node; anda multiplexer coupled to said first latch and said second latch, said multiplexer operable to select between an output of said first latch and said second latch based on a previously generated data sample; anda second module operable to receive said edge signal and further operable to generate a data sampling phase signal, wherein said edge signal influences a settling point of said data sampling phase signal.

18. The apparatus of claim 17 further comprising: a third module operable to generate a data sample signal using a second clock signal; anda fourth module operable to generate an error sample signal using a third clock signal and wherein said first module is a decision feedback equalizer.

19. The apparatus of claim 17, wherein said second module comprises: a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom;a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; anda phase interpolator coupled to said loop filter operable to generate said data sampling phase based upon said phase code.

20. The apparatus of claim 17, wherein said plurality of delta phases are generated as a function of said edge sample signal, a current data sample, and a prior data sample.