Field of the Invention
The present invention relates to a PDL drawing processing apparatus and method for generating raster data by using data described in a page description language (PDL) as input data.
Description of the Related Art
In general, PDL drawing processing for generating raster data by using PDL data for describing a drawing instruction as input can be divided into PDL analysis processing and rendering processing. In the PDL analysis processing, the PDL data is analyzed and converted into a drawing command having a lower level of abstraction. In the rendering processing, the drawing command is received, and processing for conversion into device coordinates and color compositing processing are conducted to create raster data. The raster data is output onto paper by a printer device or displayed on a monitor device. Existing examples of the PDL data include an XML paper specification (XPS) being a page description language of Microsoft Corporation and a portable document format (PDF) being a page description language of Adobe Systems Incorporated. The XPS and the PDF have a tile drawing instruction to conduct drawing by repeating the same drawing instruction once or more.
With the tile drawing instruction, it is possible to specify a width and a height of a tile (area being a unit of repetition) and an area to be covered by the tiles. The width and the height of the tile are specified in units of a coordinate system defined in PDL (hereinafter referred to as “PDL coordinates”). For example, the coordinate system of the XPS is defined as having the origin at the top left and units of 1/96 inch. The PDL coordinates are converted into coordinates defined by a device (hereinafter referred to as “device coordinates”) in a case of being converted into raster data to be output and displayed on the device in drawing processing. In general, the device coordinates are represented in units of pixels with the origin at the top left in a case of a printer.
In the conversion from the PDL coordinates into the device coordinates, which is included in the drawing processing, there are some cases where a content of the drawing specified as an integer in the PDL coordinates cannot be expressed in pixels due to the specification of an output size or a resolution. In order to solve this problem, in an XPS specification (ECMA-388), it is recommended to fill one tile with an average color of drawing results within the one tile when a drawing size of one tile drawing instruction becomes smaller than one pixel in a device coordinate system.
However, the related art, for example, a technology disclosed in Japanese Patent Application Laid-Open No. 2008-23960, in which a drawing using a mask pattern of a checkered pattern is converted into a drawing with an alpha channel, cannot be applied to a tile drawing including a drawing other than the mask pattern of the checkered pattern. Moreover, in a technology disclosed in Japanese Patent Application Laid-Open No. H08-235367, an interpolation method is determined based on a transparency level of a shading drawing instruction and a relation between a pixel of interest in a sub pixel level and a neighboring pixel, but the technology cannot be applied to a tile drawing including a drawing other than a shading.
In order to conduct accurate output when the drawing size of one tile drawing instruction becomes smaller than one pixel in the device coordinate system and a tile drawing has transparency, it is necessary to fill a tile drawing portion with an average color after temporarily conducting partial rendering with a resolution higher than an actual output resolution. However, it is necessary to conduct compositing processing with a background color taken into consideration, and overall processing becomes more complicated, which raises a problem in terms of performance.
In order to solve the above-mentioned problems, according to one embodiment of the present invention, there is provided an information processing apparatus, including: a PDL analysis unit that acquires an output resolution of input PDL data when a tile drawing instruction is included in the PDL data, and calculates a drawing size of a tile drawing based on the tile drawing instruction and the output resolution; an average color calculation unit that calculates an average color of the tile drawing based on the tile drawing instruction when the calculated drawing size is smaller than a predetermined value; and a rendering unit that renders the tile drawing instruction based on the calculated average color, in which the average color calculation unit calculates the average color based on a transparency level of a unit tile included in the tile drawing instruction.
According to the present invention, when the drawing size of the tile drawing instruction becomes smaller than one pixel in a device coordinate system and a tile drawing has transparency, an output result equivalent to that of a case where the tile drawing is enlarged and rendered to thereafter be filled with an average color can be obtained with a calculation amount smaller than in the related art.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
Now, an embodiment of the present invention is described in detail with reference to the attached drawings. In this embodiment, an XML paper specification (XPS), a portable document format (PDF), or the like is assumed as PDL data. In the following description, an “alpha value” represents a value indicating a transparency level of a color, and is assumed in this embodiment to be expressed by numerical values of from 0.0 (totally transparent) to 1.0 (totally opaque).
In the example of
In the example of
<Rendering Processing for Tile Instruction>
The rendering processing conducted for the drawing instruction described in the PDL data 201 by the information processing apparatus 101 is described.
In Step S901, the PDL analysis unit 202 acquires an output resolution. In Step S902, the PDL analysis unit 202 analyzes a drawing instruction described in the PDL data 201. In Step S903, the PDL analysis unit 202 examines whether or not the drawing instruction analyzed in Step S902 is a tile instruction. When the drawing instruction is the tile instruction, the processing advances to Step S904, and otherwise advances to Step S907.
In Step S904, the PDL analysis unit 202 uses information on the output resolution acquired in Step S901 and the drawing instruction acquired in Step S902 to calculate the drawing size of the tile instruction in the device coordinate system. In Step S905, the PDL analysis unit 202 determines whether or not the drawing size calculated in Step S904 is smaller than one pixel. When the drawing size is smaller than one pixel, the processing advances to Step S906, and otherwise advances to Step S907.
In Step S906, the tile average color calculation unit 203 calculates a tile average color, and replaces the tile instruction by a fill instruction using the calculated average color. This processing is described in detail with reference to
<Details of Tile Average Color Determining Processing>
In Step S1001, the tile average color calculation unit 203 acquires a number N of drawing instructions included in the tile drawing. Subsequently, in Step S1002, the tile average color calculation unit 203 initializes a counter i for counting the number of examined drawing instructions within the tile drawing to zero, and in Step S1003, initializes a variable Mode representing a mode of the tile average color calculation method to zero.
In Step S1004, the tile average color calculation unit 203 acquires an alpha value Alpha[0] held by the zeroth drawing instruction included in the tile drawing. In Step S1005, the tile average color calculation unit 203 compares the values between the counter i and N. When the counter i is smaller than N, Step S1006 is conducted, and otherwise Step S1010 is conducted.
In Step S1006, the tile average color calculation unit 203 acquires an alpha value Alpha[i] held by the i-th drawing instruction included in the tile drawing. In Step S1007, the tile average color calculation unit 203 compares the values between Alpha[0] acquired in Step S1004 and Alpha[i] acquired in Step S1006. When the values are equal to each other, Step S1008 is conducted, and otherwise Step S1009 is conducted. In Step S1008, the tile average color calculation unit 203 adds one to the value of the counter i, and returns to Step S1005.
In Step S1009, the tile average color calculation unit 203 sets the variable Mode representing the mode of the tile average color calculation method to one. When the processing from Step S1004 to Step S1009 is conducted for the unit tile of
In Step S1010, the tile average color calculation unit 203 examines whether or not the value of the variable Mode representing the mode of the tile average color calculation method is zero. When the variable Mode is zero, Step S1011 is conducted, and otherwise Step S1012 is conducted. In Step S1011, the tile average color calculation unit 203 uses a calculation method I to determine the tile average color, and in Step S1012, uses a calculation method II to determine the tile average color.
<Tile Average Color Determining Processing Using Calculation Method I>
In Step S1101, the tile average color calculation unit 203 acquires the number N of drawing instructions included in the tile drawing. In Step S1102, the tile average color calculation unit 203 calculates an average value color_avg of the colors of the drawing instructions included in the tile drawing. A calculation expression for the average value color_avg is as follows:
where color[i] represents the color value of the i-th drawing instruction included in the tile drawing.
In Step S1103, the tile average color calculation unit 203 calculates an average value alpha_avg of the alpha values of the drawing instructions included in the tile drawing. A calculation expression for the average value alpha_avg is as follows:
where alpha[i] represents the alpha value of the i-th drawing instruction included in the tile drawing.
In Step S1104, the tile average color calculation unit 203 conducts compositing processing for a background color color_bg, the average value color_avg calculated in Step S1102, and the average value alpha_avg calculated in Step S1103, and sets a result composite_result of the compositing as the tile average color. A calculation expression for the compositing processing is as follows.
composite_result=color_avg*alpha_avg+color_bg*(1−alpha_avg)
<Tile Average Color Determining Processing Using Calculation Method II>
In Step S1204, the tile average color calculation unit 203 uses the average value alpha_avg calculated in Step S1203 to calculate an average value color_avg′ after correction. A calculation expression for the average value color_avg′ is as follows.
In Step S1205, the tile average color calculation unit 203 conducts compositing processing for the background color color_bg and the average value color_avg′ calculated in Step S1204, and sets a result composite result of the compositing as the tile average color. A calculation expression for the compositing processing is as follows.
composite_result=color_avg′*alpha_avg+color_bg*(1−alpha_avg)
Embodiment(s) of the present invention can also be realized by a computer of a system or apparatus that reads out and executes computer executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be referred to more fully as a ‘non-transitory computer-readable storage medium’) to perform the functions of one or more of the above-described embodiment(s) and/or that includes one or more circuits (e.g., application specific integrated circuit (ASIC)) for performing the functions of one or more of the above-described embodiment(s), and by a method performed by the computer of the system or apparatus by, for example, reading out and executing the computer executable instructions from the storage medium to perform the functions of one or more of the above-described embodiment(s) and/or controlling the one or more circuits to perform the functions of one or more of the above-described embodiment(s). The computer may comprise one or more processors (e.g., central processing unit (CPU), micro processing unit (MPU)) and may include a network of separate computers or separate processors to read out and execute the computer executable instructions. The computer executable instructions may be provided to the computer, for example, from a network or the storage medium. The storage medium may include, for example, one or more of a hard disk, a random-access memory (RAM), a read only memory (ROM), a storage of distributed computing systems, an optical disk (such as a compact disc (CD), digital versatile disc (DVD), or Blu-ray Disc (BD)™), a flash memory device, a memory card, and the like.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2016-023639, filed Feb. 10, 2016, which is hereby incorporated by reference herein in its entirety.
Number | Date | Country | Kind |
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2016-023639 | Feb 2016 | JP | national |