This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-288237, filed on Sep. 30, 2004; the entire contents of which are incorporated herein by reference.
1. Field
Embodiments of the present invention relate to an information apparatus comprising a main processor and a sub-processor, and an initialize sequence method.
2. Description of the Related Art
An information apparatus such as a computer generally includes a sub-processor for performing such processing as control of an initialize sequence (startup sequence or boot sequence) and control of a specific input/output device, in addition to a CPU (Central Processor Unit) serving as a main processor. This sub-processor is implemented in the form of a single chip microcomputer or the like. The sub-processor is started first to execute the process of starting (booting) the CPU.
Japanese Patent Application Laid Open No. 2003-271258 discloses a computer equipped with a CPU and EC (Embedded Controller). In this computer, the EC serves the function of the sub-processor. The computer startup sequence is placed under the control of the EC.
As described above, in a system for starting the main processor (CPU) by the sub-processor (EC), the sub-processor is already in the process of running the program, when the main processor has started, and the operation of the sub-processor is under the control of the program being run.
Thus, if the program to be run by the sub-processor (EC) has been tampered, there is no guarantee to ensure the system operation after the main processor has started. Further, extension of the function of the sub-processor (EC) requires a change to be made in the hardware such as the ROM storing the program to be run by the sub-processor.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.
Embodiments of the invention are implemented to allow the sub-processor to run a required program after the main processor has started, namely placed into an active state. The following describes the various embodiments with reference to the drawings.
According to one embodiment of the invention, an information processing apparatus 10 comprises a first processor 100, a first memory controller (MC) 101, a first memory (e.g., DRAM) 102, an input/output (I/O) controller 103, a first configuration unit (CFG) 104, a second processor 200, a second memory controller (MC) 201, a second memory (e.g., DRAM) 202, input/output controller 203, a second configuration unit (CFG) 204, a third memory (e.g., ROM) 50, input/output device 70 and a control/status register (C/S) 80.
The second processor 200 controls each component through a bus 2. This second processor 200 serves as a sub-processor to control the startup sequence (initialize sequence or boot sequence) and specific input/output devices such as various operation buttons and input devices. The first processor 100 is initially stopped, namely placed in an inactive state.
The second processor 200 is implemented as a microcomputer. The second processor 200 can be started by either the ROM 50 or DRAM 202. The second configuration unit (CFG) 204 determines whether the ROM 50 or DRAM 202 is used as a boot device. Normally, the second processor 200 uses the ROM 50 as a boot device. For example, when the power is supplied at start-up, the second processor 200 is started up by the ROM 50 to run a boot program stored in the ROM 50.
The second memory controller (MC) 201 is connected with the DRAM 202. The MC 201 controls the DRAM 202 in response to the read/write request from the first processor 100 or second processor 200.
The input/output controller 203 is connected with the ROM 50. The ROM 50 stores a boot program 50A. The boot program 50A is first run by the second processor 200 when the second processor 200 has started operation.
The second configuration unit (CFG) 204 provides the operation setting and starts control of the second processor 200, MC 201 and input/output controller 203. The second configuration unit (CFG) 204 controls the MC 201 and input/output controller 203, and selects either the DRAM 202 or the ROM 50 as a boot device for the second processor 200. To be more specific, when the input/output controller 203 is selected by the CFG 204, the second processor 200 runs the boot program stored in the ROM 50. If the MC 201 is selected by the CFG 204, the second processor 200 runs the boot program stored in the DRAM 202.
After the second processor 200 has started up, the second processor 200 is processing information to start the first processor 100 by placing the first processor 100 into an active state. For instance, according to this embodiment of the invention, the second processor 200 allows the boot program to be run by the first processor 100, in the DRAM 202, and operates the first configuration unit (CFG) 104 via a C/S 80. The first processor 100 serves as a main processor of the present information processing apparatus and executes the operating system and various application programs.
The first processor 100 controls the components connected to the buses 1 and 2.
The first processor 100 runs the boot program loaded on the DRAM 202 by the second processor 200. The first processor 100 has a security function of verifying the validity of the program, and verifies the validity of the boot program loaded on the DRAM 202 by the second processor 200.
The MC 101 is connected with the DRAM 102. In response to the read/write request from the first processor 100, the MC 101 controls the DRAM 102. The I/O controller 103 controls interconnection between the buses 1 and 2.
The first configuration unit (CFG) 104 provides the operation setting and starts control of the first processor 100, MC 101 and I/O controller 103.
Referring to
(1) Start the second processor 200.
(2) Start the first processor 100 using the second processor 200.
(3) Restart the second processor 200 using the first processor 100.
After these operations, the information processing apparatus is put into the normal operation mode.
When power is supplied to the information processing apparatus, the bus 2, second processor 200, input/output controller 203, ROM 50, CFG 104 and CFG 204 are automatically enabled and placed into an active state. In this case, the CFG 104 disables the first processor 100, MC 101 and I/O controller 103 by placing these components into inactive states. The CFG 204 sets an input/output (I/O) controller 203 automatically to ensure that the ROM 50 is used as a boot device of the second processor 200.
When the information processing apparatus has been turned on, the second processor 200 starts up and runs the boot program 50A stored in the ROM 50. By running the boot program 50A, the second processor 200 enables the MC 201, DRAM 202 and input/output device 70.
By executing the boot program 50A, the second processor 200 loads the program 202A for start control of the first processor 100 from the input/output device 70 such as a hard disk into the DRAM 202, and runs the loaded program 202A. Thereafter, the second processor 200 runs the program 202A, whereby the boot program 202B to be run by the first processor 100 is loaded from the input/output device 70 into the DRAM 202, as shown in
In this case, the second processor 200 sets on the CFG 104 the information indicating the storage position of the program to be first executed by the first processor 100, in such a way that the first processor 100 runs the boot program 202B on the DRAM 202. Then the second processor 200 operates the CFG 104 to cancel the resetting of the first processor 100. This arrangement causes the first processor 100 to be started and the first processor 100 starts to run the boot program 202B stored in the DRAM 202. In this case, the first processor 100 verifies the validity of the boot program 202B loaded in the DRAM 202. If the boot program 202B has been found out to be illegal, the start sequence immediately terminates.
This is followed by the operation of the first processor 100 operating the program 102A so that a new boot program 202C to be run by the second processor 200 is loaded from the input/output device 70 into the DRAM 202, as shown in
Then the first processor 100 loads a desired program from the input/output device 70 and starts running the program. This operation causes the information apparatus to be set to the normal operation mode. During the normal operation mode, the second processor 200 correctly performs the processing of controlling the input/output device 70 and others.
Referring to the flowchart given in
The first processor 100 loads the program 102A (second processor restart program) for restarting the second processor 200 from the input/output device 70 (Block S101). The first processor 100 loads the DRAM 102 with the program 102A loaded from the input/output device 70, through the I/O controller 103, and runs the program 102A (Block S102). The first processor 100 operates the CFG 204 to stop the second processor 200 (Block S103). In the Block S103, the first processor 100 operates the CFG 204, thereby resetting the second processor 200, for example.
The first processor 100 loads the boot program 202C to be run by the second processor, from the input/output device 70 (Block S104). In Block S104, the first processor 100 loads the DRAM 202 with the boot program 202C loaded from the input/output device 70.
The first processor 100 operates the CFG 204 so that the second processor 200 starts up from the DRAM 202 (Block S105). In Block S105, the CFG 204 selects the MC 201, thereby allowing the boot device to be switched from the ROM 50 to the DRAM 202.
The first processor 100 releases the resetting of the second processor 200 and restarts the second processor 200, whereby the second processor 200 runs the new boot program 202C stored in the DRAM 202.
According to the present embodiment, as described above, after the first processor 100 has been started by the second processor 200, the second processor 200 is restarted under the control of the first processor 100, and the second processor 200 runs a new program automatically. This process allows the second processor 200 to run a desired program.
Thus, after the first processor 100 has been started, the operation of the second processor 200 is controlled by a new program loaded by the first processor 100. Thus, even if the boot program 50A in the ROM 50 has been tampered, the operation of the second processor 200 can be assured as long as the first processor 100 is started correctly.
The present embodiment has been described with reference to the case where the boot program 50A and boot program 202C are stored in the ROM 50 and DRAM 202, respectively. However, the boot program 50A and boot program 202C can be stored in two different storage areas on the DRAM 202, respectively. In this case, these two storage areas function as boot areas.
It is to be expressly understood, however, that the present invention is not restricted to the embodiments described above. The present invention can be embodied in a great number of variations of the components, without departing from the technological spirit of the invention claimed. It can be formed into various inventions by appropriate combinations of a plurality of components. For example, some of the components shown in the aforementioned embodiment can be eliminated. Further, these components can be appropriately combined to form a different embodiment.
Number | Date | Country | Kind |
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2004-288237 | Sep 2004 | JP | national |