Patent Application
20240061646
The present disclosure relates to an information processing apparatus, an information processing method, and an information processing program.
In recent years, a neural network which is a mathematical model imitating a mechanism of a cranial nervous system has attracted attention. Furthermore, a deep neural network (DNN) in which a neural network supports deep learning to deepen a network hierarchy is known.
Although achieving a high recognition rate by increasing the number of coefficients, the DNN has a large calculation amount. Thus, various methods for reducing a processing load of calculation on the DNN have been proposed. For example, Non Patent Literature 1 discloses a method of reducing a processing load by approximating a coefficient using logarithmic calculation.
Non Patent Literature 1: Daisuke Miyashita, and two others, “Convolutional Neural Networks using Logarithmic Data Representation”, [online], Mar. 3, 2016, arXiv, [searched on Feb. 1, 2021], Internet <URL: https://arxiv.org/pdf/1603.01025.pdf>
In the method disclosed in Non Patent Literature 1, however, coefficients close to zero are densely expressed, but coefficients close to the maximum value are sparsely expressed. Therefore, the recognition rate of the DNN may decrease.
Therefore, the present disclosure proposes a mechanism capable of reducing the decrease in a recognition rate of the DNN while inhibiting a processing load.
Note that the above-described problem or object is merely one of a plurality of problems or objects that can be solved or achieved by a plurality of embodiments disclosed in the present specification.
According to the present disclosure, an information processing apparatus is provided. The information processing apparatus includes a calculation unit that performs integration of an input value and a weight coefficient. Any one of the input value and the weight coefficient is expressed by a combination of addition or subtraction of n or less first bit strings. The first bit strings include one bit of 1.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that, in the present specification and the drawings, components having substantially the same functional configuration are denoted by the same reference signs, and redundant description thereof will be omitted.
One or a plurality of embodiments (including examples and variations) described below can be implemented independently. In contrast, at least a part of the plurality of embodiments described below may be appropriately combined with at least a part of other embodiments and implemented. The plurality of embodiments may include different novel features. Therefore, the plurality of embodiments may contribute to solving different objects or problems, and may exhibit different effects.
Note that the description will be given in the following order.
1. Outline of Present Disclosure
1.1. Background
1.2. Outline of Proposed Technology
2. First Embodiment
2.1. Configuration Example of Information Processing Apparatus
2.2. Configuration Example of Calculation Unit
2.3. Algorithm Example
2.4. Conversion Processing
2.5. Effects
3. Second Embodiment
4. Third Embodiment
5. Hardware Configuration Example
6. Conclusion
The technology according to the present embodiments relates to a DNN. The DNN is a neural network to which deep learning is applied.
Then, in the DNN, a plurality of inputs (input data) X1, X2, . . . , and Xm (m=4 in
That is, in the example of the DNN in
While a learning method using such a DNN has high accuracy, a heavy processing load according to the calculation is added. A calculation method of effectively reducing the processing load is thus required. In particular, since an edge terminal having an edge/computing function has limited processing capability and memory capacity, it is difficult to perform conventional DNN processing. Reduction in a DNN calculation amount is required.
Therefore, in recent years, for example, in Reference [1], the number of bits of coefficients is reduced by 8-bit fixed-point quantization to reduce the calculation amount.
Furthermore, for example, in a DNN calculation in hardware, a large calculation cost of multiplication of coefficients and activations is imposed. Specifically, at the time of a multiplication calculation, each coefficient bit is shifted, and the resulting value is added. Therefore, when 8-bit quantization is performed, eight shift calculations are performed.
Specifically, as illustrated in
Here, in order to inhibit the number of times of shift calculations, for example, power-of-two quantization of a coefficient is used in References [2] and [3] and Non Patent Literature 1. In the power-of-two quantization, the number of times of shift calculations is reduced to one by expressing a coefficient with a value of 2n. Only a small number of values, however, can be expressed by the power-of-two quantization, which degrades accuracy.
Non Patent Literature 1 and Reference [3] propose an approximation method using logarithmic calculation. In the methods of Non Patent Literature 1 and Reference [3], however, coefficients near zero are densely expressed, but values expressed near the maximum value are sparsely expressed, which may degrade recognition accuracy of the DNN.
Therefore, for example, Reference [4] proposes a method of optimizing a base value of quantization. In a normal power-of-two quantization, the base value of quantization is two, but, in Reference [4], values of 21/2 and 21/4 are used to adjust the distribution of quantization values.
In any of the methods of References [2] to [4] and Non Patent Literature 1, values in a specific range are densely expressed while there is a region having sparse expressible values. Therefore, in Reference [5], the number of times of shift calculations is mitigated as compared with that in the power-of-two quantization expression in References [2] to [4] and Non Patent Literature 1 to improve the distribution of values of coefficients that can be expressed by n times of additions. In Reference [5], the number of times of shift calculations is controlled by a maximum value n of the number of “1” in coefficient bits. Unfortunately, there is a problem of low memory efficiency due to addition of values having a plurality of base values.
[1] Vanhoucke, V., Senior, A., & Mao, M. Z. (2011). Improving the speed of neural networks on CPUs.
[2] Zhou, A., Yao, A., Guo, Y., Xu, L., & Chen, Y. (2017). Incremental network quantization: Towards lossless cnns with low-precision weights. arXiv preprint arXiv:1702.03044.
[3] Lee, E. H., Miyashita, D., Chai, E., Murmann, B., & Wong, S. S. (2017, March). Lognet: Energy-efficient neural networks using logarithmic computation. In 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (pp. 5900-5904). IEEE.
[4] Vogel, S., Liang, M., Guntoro, A., Stechele, W., & Ascheid, G. (2018, November). Efficient hardware acceleration of cnns using logarithmic data representation with arbitrary log-base. In Proceedings of the International Conference on Computer-Aided Design (pp. 1-8).
[5] Li, Y., Dong, X., & Wang, W. (2019, September). Additive Powers-of-Two Quantization: An Efficient Non-uniform Discretization for Neural Networks. In International Conference on Learning Representations.
As described above, it is required to further reduce a DNN calculation amount while inhibiting degradation in recognition accuracy of the DNN. Therefore, in the proposed technology of the present disclosure, one of an input bit string (input value) and a weight coefficient is expressed by a combination of addition and subtraction of the first bit strings including one “1”, so that the DNN calculation amount is reduced as compared with that in a normal quantization expression while the degradation in recognition accuracy of the DNN is inhibited. In order to simplify description, a case where a weight coefficient is expressed by the first bit string will be described below.
Furthermore, in the proposed technology of the present disclosure, for example, a weight coefficient of “00001110” is expressed by subtraction of “00000010” from “00010000”.
As described above, in the proposed technology of the present disclosure, the weight coefficient is expressed by addition or subtraction of n (n=2 in
As illustrated in
Since a first bit string includes one “1”, one shift calculation is required to be performed in accordance with a location of “one” of the first bit string in the multiplication of the input data and the first bit string.
Therefore, the number of times of shift calculations performed in the multiplication of the input data and the weight coefficient can be reduced to n (n=2 in
Furthermore, as described above, in the proposed technology of the present disclosure, a weight coefficient is expressed by addition or subtraction of first bit strings. As described above, a weight coefficient is decomposed by using not only addition but subtraction and expressed. This increases the number of weight coefficients that can be expressed by n first bit strings, and can reduce degradation in recognition accuracy of the DNN. Note that expression of a bit string with n first bit strings is also hereinafter referred to as “n-hot” expression. Furthermore, a quantization value represented by the “n-hot” expression is also referred to as an “n-hot” quantization value.
Note that, although, in the above-described example, a case of n=2 has been described, n may be 3 or more. For example, a set Pb obtained by combining a power-of-two quantization value of b bits and “0” is represented by Expression (1) below. Furthermore, the maximum value of the magnitude of a weight coefficient (one example of bit string) is set to α. That is, the weight coefficient has a value of [α, −α].
P
b
∈X={20,2−1,2−2, . . . ,2−(b-1),0} (1)
In this case, an “n-hot” quantization value Qn-hot(α, b, n) is expressed by Expression (2) below.
Q
n-hot(α,b,n)=αΣl=1n{(−1)c
For example, an example of the “n-hot” quantization value in the case of n=2 is represented by Expression (3) below.
Q
n-hot(α,b,n=2)=α[[{Pb,1+Pb,2}∪{(Pb,2−Pb,1}]∪[{−(Pb,1+Pb,2)}∪{−(Pb,2−Pb,1)}]] (3)
Note that, in Expression (3), the sum set of {Pb, 1+Pb,2} and {Pb2−Pb1} has a positive value, and the sum set of {−(Pb,1+Pb,2)} and {−(Pb2−Pb1)} has a negative value.
Next, an information processing apparatus 10 according to a first embodiment of the present disclosure will be described.
(Input Unit 110)
The input unit 110 has a function of detecting various input operations from an operator. For this purpose, the input unit 110 may include various devices for detecting input operations from the operator. The input unit 110 can be implemented by, for example, various buttons, a keyboard, a touch panel, a mouse, a switch, and the like.
(Calculation Unit 120)
The calculation unit 120 the calculation unit 120 has a function of calculating an output value by performing an inner product calculation based on a plurality of input values and a plurality of weight coefficients corresponding to the input values. In particular, the calculation unit 120 performs an inner product calculation related to forward propagation of a neural network.
The calculation unit 120 in
The calculation processing unit 122 calculates the weight coefficient converted into an “n-hot” expression by the conversion unit 121 and an input value, and outputs a calculation result. Details of the calculation unit 120 will be described later.
(Storage Unit 130)
The storage unit 130 has a function of storing programs, data, and the like used in each configuration of the information processing apparatus 10. The storage unit 130 stores, for example, various parameters used in the neural network.
(Output Unit 140)
The output unit 140 has a function of outputting various pieces of information to the operator. For this purpose, the output unit 140 may include a display device that outputs visual information. Here, the above-described display device can be implemented by, for example, a cathode ray tube (CRT) display device, a liquid crystal display (LCD) device, an organic light emitting diode (OLED) device, or the like.
The functional configuration example of the information processing apparatus 10 according to the first embodiment of the present disclosure has been described above. Note that the above-described functional configuration example is merely one example, and the functional configuration example is not limited to such an example. The information processing apparatus 10 may further include a configuration other than that in
As described above, the calculation unit 120 includes the conversion unit 121 and the calculation processing unit 122.
[Conversion Unit 121]
The conversion unit 121 in
(Conversion Processing Unit 1211)
The conversion processing unit 1211 performs “n-hot” conversion on a weight coefficient A, and expresses the weight coefficient A with n (n=2 in
For example, in the example of
As described above, the weight coefficient A can have a positive value and a negative value. Furthermore, the conversion processing unit 1211 converts the weight coefficient A into an expression (“n-hot” expression) obtained by addition or subtraction of n or less first bit strings.
(Search Unit 1212)
The search unit 1212 searches the n or less first bit strings obtained by performing “n-hot” conversion on the weight coefficient A for a sign bit and a location of “1” in the first bit strings. Here, since n=2 holds, the first first bit string is referred to as a bit string B1, and the second first bit string is referred to as a bit string B2 for distinction.
For example, the search unit 1212_1 searches the bit string B1 “+01000000”, and detects a sign bit “+” and the location of “1” in the bit string B1. In this case, the search unit 1212_1 detects that the location of “1” in the bit string B1 is the seventh from the LSB. Similarly, the search unit 1212_1 searches the bit string B2 “+00010000”, and detects that the sign bit “+” and the location of “1” in the bit string B2 are the fifth from the LSB.
The search unit 1212 outputs information indicating the detected sign bit and information indicating the location of “1” in the bit string B1 to the calculation processing unit 122.
For example, the search unit 1212_1 outputs a signal indicating that the sign bit of the bit string B1 is “+” and a bit string “110” indicating the location of “1” to the calculation processing unit 122 at a predetermined time t1. Furthermore, the search unit 1212_1 outputs a signal indicating that the sign bit of the bit string B2 is “+” and a bit string “100” indicating the location of “1” to the calculation processing unit 122 at a time t2 next to the predetermined time t1.
[Calculation Processing Unit 122]
The calculation processing unit 122 in
(Sign Inversion Unit 1221)
The sign inversion unit 1221 has a function of inverting the sign of the input bit string x. For example, when an input bit string x having a positive value is input, the sign inversion unit 1221 generates a sign inverted input bit string x (−1) inverted to a negative value, and outputs the sign inverted input bit string x (−1) to a coefficient calculation unit 1222. Furthermore, for example, when an input bit string x having a negative value is input, the sign inversion unit 1221 generates a sign inverted input bit string x (−1) inverted to a positive value, and outputs the sign inverted input bit string x (−1) to the coefficient calculation unit 1222.
(Coefficient Calculation Unit 1222)
The coefficient calculation unit 1222 performs multiplication of an input bit string x and the weight coefficient A1, and outputs output Y, which is a multiplication result. The coefficient calculation unit 1222 includes a selection unit 123, a shift calculation unit 124, an addition unit 125, and a delay unit 126.
The selection unit 123 selects one of the input bit string x and the sign inverted input bit string x (−1) in accordance with a signal indicating a sign bit output from the search unit 1212. The selection unit 123 the selection unit 123 selects one of the input bit string x and the sign inverted input bit string x (−1) in accordance with signs of the bit strings B1 and B2. The selection unit 123 selects the input bit string x when the bit strings B1 and B2 have positive signs, and selects the sign inverted input bit string x (−1) when the bit strings B1 and B2 have negative signs. The selection unit 123 outputs the selected bit string to the shift calculation unit 124.
The shift calculation unit 124 shifts the bit string (input bit string x or sign inverted input bit string x (−1)) output by the selection unit 123 by a shift amount in accordance with the location of “1” output by the search unit 1212.
For example, in
Furthermore, when a signal related to the bit string B2 of the weight coefficient A1 is input to the coefficient calculation unit 1222_1 at the time t2, the selection unit 123 selects the input bit string x, and the shift calculation unit 124 generates a shift signal obtained by shifting the input bit string x by five bits. This causes the coefficient calculation unit 1222_1 to perform integration of the input bit string x and the bit string B2.
The addition unit 125 adds output of the shift calculation unit 124 and output of the delay unit 126. The delay unit 126 holds output of the addition unit 125, and outputs the held output Y to the addition unit 125 at the next time (clock). That is, the addition unit 125 adds output of the shift calculation unit 124 at the current time to output Y at the previous time to generate output Y.
For example, in
Here, for example, when the above-described selection unit 123 selects the sign inverted input bit string x (−1), the addition unit 125 adds a result obtained by the shift calculation unit 124 performing shift calculation on the sign inverted input bit string x (−1). This is the same as the fact that the addition unit 125 subtracts a shift calculation result of the input bit string x. As described above, the selection unit 123 selects any one of the input bit string x and the sign inverted input bit string x (−1), so that the addition unit 125 adds or subtracts the shift calculation result. As described above, the addition unit 125 can also be said to be an addition/subtraction processing unit that performs any processing of addition and subtraction in accordance with a selection result of the selection unit 123.
This allows the coefficient calculation unit 1222 to perform multiplication of the weight coefficient A and the input bit string x by two shift calculations, so that the number of times of shift calculations can be reduced. Furthermore, the reduction in the number of times of shift calculations can reduce a calculation circuit, and can inhibit an increase in circuit scale.
Although a case where the above-described calculation unit 120 calculates the weight coefficient A subjected to the “n-hot” quantization by a circuit has been described, the calculation unit 120 can calculate the weight coefficient A subjected to the “n-hot” quantization by software. Therefore, a calculation of the weight coefficient A subjected to the “n-hot” quantization by software, that is, an “n-hot” quantization learning algorithm will be described.
A pseudo code Algorithm1 in
Note that symbols included in the pseudo code Algorithm1 are defined as follows.
As illustrated in
Next, processing of conversion into an “n-hot” expression according to the first embodiment of the present disclosure will be described.
The conversion processing unit 1211 scans a bit string which is the weight coefficient A in order from an MSB. Therefore, the conversion processing unit 1211 first detects a bit value of the MSB (Step S101). The conversion processing unit 1211 determines whether or not the detected bit value is “0”. (Step S102).
When the detected bit value is not “0”, that is, when the detected bit value is “1” (Step S102; No), the conversion processing unit 1211 increases the number of “1” by one (Step S103), and proceeds to Step S105. That is, the conversion processing unit 1211 counts the number of “1”, and proceeds to Step S107.
When the detected bit is “0” (Step S102; Yes), the conversion processing unit 1211 determines whether or not three or more “1” have been counted so far (Step S104). When less than three “1” have been counted (Step S104; No), the conversion processing unit 1211 determines whether or not the bit string which is the weight coefficient A has been scanned to the end (Step S105).
When the bit string has not been scanned to the end (Step S105; No), the conversion processing unit 1211 detects a one-level lower bit value of the bit string (Step S106), and returns to Step S102.
In contrast, when it is determined in Step S104 that three or more “1” have been counted (Step S104; Yes), the conversion processing unit 1211 determines whether or not “1” are continuous (Step S107).
When “1” are not continuous (Step S107; No), the conversion processing unit 1211 replaces “1” included in the bit string with “0” (Step S110), and converts the weight coefficient A into an “n-hot” quantization value of an addition expression (Step S108). When “1” are continuous (Step S107; Yes), the conversion processing unit 1211 converts the weight coefficient A into an “n-hot” quantization value of a subtraction expression (Step S109), and ends the processing.
This allows the conversion processing unit 1211 to convert the weight coefficient into an “n-hot” expression of addition or subtraction, and can further reduce the calculation amount while inhibiting degradation in accuracy due to the conversion of the weight coefficient.
Here, the above-described conversion processing will be described with reference to an example of a case where the conversion processing unit 1211 performs the “n-hot” quantization on the bit string in
As illustrated in
In the example of
The conversion processing unit 1211 detects “0” at the fifth bit from the MSB. The conversion processing unit 1211 determines whether or not three or more “1” have been counted. In the example of
Subsequently, the conversion processing unit 1211 determines whether or not the detected “1” are continuous. When “1” are continuous, the conversion processing unit 1211 performs an “n-hot” conversion on the bit string by subtraction. When “1” are not continuous, the conversion processing unit 1211 performs the “n-hot” conversion on the bit string by addition.
In the example of
In the conversion processing described above with reference to
As described above, there is a bit string that is not expressed in the “n-hot” expression according to the technology of the present disclosure. In the first embodiment of the present disclosure, such a bit string is projected to, for example, the closest bit string, and is expressed by an “n-hot” quantization value. Examples of the projection method include rounding up, rounding down, and rounding to the closest value.
For example, when the conversion processing unit 1211 is implemented by a circuit (hardware), it is considered that the circuit scale of the conversion processing unit 1211 can be further reduced by selecting rounding up or rounding down as a projection method. Furthermore, when the conversion processing unit 1211 is implemented by software, it is considered that conversion accuracy can be further improved by performing rounding to the closest value.
A value between “81” and “95” in the decimal number cannot be expressed by the “n-hot” expression. Therefore, as illustrated in
As described above, in the conversion processing according to the first embodiment of the present disclosure, there is a value not expressed by an “n-hot” expression. In the conversion processing according to the first embodiment of the present disclosure, however, the conversion processing unit 1211 performs conversion processing by using not only addition but subtraction. This can further inhibit degradation in accuracy due to the conversion processing.
This point will be described with reference to
In a comparative example in
Note that, in the examples of
As illustrated in
As illustrated in
In contrast, as illustrated in
As described above, the conversion processing according to the first embodiment of the present disclosure can further reduce the error included in the conversion result. In particular, in the conversion processing according to the present embodiment, an error in a case of a large value of the weight coefficient A can be made smaller than that in a case where only addition is performed. Therefore, the conversion processing according to the present embodiment can further inhibit degradation in recognition accuracy of the neural network due to the conversion.
Subsequently, reduction in a calculation amount in conversion processing will be described with reference to
As described above, the binary numbers of three bits are converted into “n-hot” expressions, so that a calculation amount at the calculation processing unit 122 can be reduced to ⅔ of that before the conversion.
Note that, similarly, all binary numbers of two bits can be expressed by the “n-hot” expression. Furthermore, in a case of four bits or more, as illustrated in
Here,
For example, in the case of four bits (b=4), the rate of values that can be expressed by n=1 is “0.375”. The rate of values that can be expressed by the conversion processing according to the embodiment, that is, the rate of values that can be expressed by addition and subtraction of n=2 is “0.938”. Furthermore, in the case of four bits, the calculation cost (calculation amount) rate at the time when n-hot conversion is performed by the conversion processing according to the embodiment is 2/4 as compared with that in a case where no n-hot conversion is performed.
Furthermore, in the case of eight bits (b=8), the rate of values that can be expressed by n=1 is “0.039”. The rate of values that can be expressed by the conversion processing according to the embodiment, that is, the rate of values that can be expressed by addition and subtraction of n=2 is “0.230”. Furthermore, in the case of eight bits, the calculation cost (calculation amount) rate at the time when n-hot conversion is performed by the conversion processing according to the embodiment is 2/8 as compared with that in a case where no n-hot conversion is performed.
As described above, the smaller number of bits increases the rate of values that can be expressed by the conversion processing according to the embodiment. The large number of bits reduces the rate of values that can be expressed by the conversion processing according to the embodiment, but can inhibit reduction in the rate as compared with those in the comparative examples.
Furthermore, the calculation cost (calculation amount) can be further reduced by converting the weight coefficient A into an “n-hot” expression by the conversion processing according to the embodiment.
As described above, the information processing apparatus 10 according to the first embodiment can further reduce the calculation cost while further inhibiting degradation in accuracy by converting the weight coefficient A into an “n-hot” expression.
Although, in the above-described first embodiment, the information processing apparatus 10 performs calculation of a neural network by converting the weight coefficient A into an “n-hot” expression, this is not a limitation. For example, the information processing apparatus 10 may perform the calculation by using the weight coefficient A preliminarily expressed by an “n-hot” expression. A method using a weight coefficient preliminarily subjected to the “n-hot” conversion will be described in a second embodiment.
Note that, for example, the weight coefficient A may be preliminarily expressed by an “n-hot” expression when a model of the neural network is generated, or may be converted into the “n-hot” expression and stored when the model is stored in the information processing apparatus 10A.
Furthermore, although, here, a signal representing the bit string B1 and the bit string B2, which are “n-hot” expressions of the weight coefficient A, is input from the storage unit 130 to the coefficient calculation unit 1222, this is not a limitation. For example, the storage unit 130 may store the bit string B1 and the bit string B2. The calculation unit 120A may search the bit string B1 and the bit string B2 for a sign bit and a location of “1”. In this case, the calculation unit 120A includes, for example, the search unit 1212 in
As described above, processing of performing “n-hot” conversion on the weight coefficient A can be reduced and a processing load on the information processing apparatus 10A can be further reduced by performing calculation by using the weight coefficient A preliminarily subjected to the “n-hot” conversion.
Although, in the above-described first and second embodiments, the information processing apparatuses 10 and 10A convert the weight coefficient A into an “n-hot” expression, this is not a limitation. For example, the information processing apparatuses 10 and 10A may convert an input bit string x into an “n-hot” expression. A method of converting the input bit string x into the “n-hot” expression as described above will be described in a third embodiment.
The conversion unit 121B converts the input bit string x into an “n-hot” quantization value. The calculation processing unit 122B calculates the input bit string x converted into the “n-hot” expression and the weight coefficient A, and outputs a calculation result.
The conversion unit 121B includes a conversion processing unit 1211B and a search unit 1212B. The conversion processing unit 1211B performs conversion processing of performing “n-hot” conversion on the input bit string x, and generates two first bit strings (bit string B1 and bit string B2). For example, in the example of
The search unit 1212B searches for sign bits of the bit strings B1 and B2 and locations of “1” included in the bit strings B1 and B2, and outputs a search result to a coefficient calculation unit 1222B.
Note that the processing in the conversion unit 121B is the same as the processing in the conversion unit 121 except that the processing is performed on the input bit string x.
The calculation processing unit 122B includes coefficient calculation units 1222B_1 to 1222_m in the number corresponding to the number of weight coefficients A1 to Am to be calculated. The coefficient calculation unit 1222B has the same functional configuration as the coefficient calculation unit 1222 in
The sign inversion unit 127 has a function of inverting a sign of the weight coefficient A. Note that the sign inversion unit 127 has the same function as the sign inversion unit 1221 in
The selection unit 123 selects one of the weight coefficient A and a weight coefficient obtained by inverting a sign (also referred to as sign inverted weight coefficient) in accordance with a signal related to a sign bit output from the search unit 1212B. The shift calculation unit 124 multiplies the bit string selected by the selection unit 123 by the input bit string x expressed in an “n-hot” expression.
The addition unit 125 adds a result of multiplication performed by the shift calculation unit 124 at the previous time and a result of multiplication performed by the shift calculation unit 124 at the current time. The delay unit 126 holds the addition result from the addition unit 125 until the next time.
As described above, also in a case where the conversion unit 121B converts the input bit string x into an “n-hot” expression, similarly to the first embodiment, calculation of the weight coefficient A and the input bit string x can be performed. A calculation amount can be further reduced while degradation in accuracy is inhibited.
Next, hardware configuration examples of the information processing apparatuses 10, 10A, and 10B according to the embodiments of the present disclosure will be described. Although the hardware configuration example of the information processing apparatus 10 according to the first embodiment will be described below, the same applies to the other embodiments.
(CPU 871)
The CPU 871 functions as, for example, a calculation processing device or a control device, and controls the overall or part of the operation of each component based on various programs recorded in the ROM 872, the RAM 873, the storage 880, or a removable recording medium 901.
(ROM 872, RAM 873)
The ROM 872 is a device that stores a program read by the CPU 871, data used for calculation, and the like. The RAM 873 temporarily or permanently stores, for example, a program read by the CPU 871, various parameters that appropriately change at the time of execution of the program, and the like.
(Host Bus 874, Bridge 875, External Bus 876, Interface 877)
The CPU 871, the ROM 872, and the RAM 873 are mutually connected via, for example, the host bus 874 capable of high-speed data transmission. In contrast, the host bus 874 is connected to the external bus 876 having a relatively low data transmission speed via the bridge 875, for example. Furthermore, the external bus 876 is connected to various components via the interface 877.
(Input Device 878)
For example, a mouse, a keyboard, a touch panel, a button, a switch, and a lever are used as the input device 878. Moreover, a remote controller (hereinafter, remote) capable of transmitting a control signal by using infrared rays or other radio waves may be used as the input device 878. Furthermore, the input device 878 includes a voice input device such as a microphone.
(Output Device 879)
The output device 879 is a device capable of visually or audibly notifying a user of acquired information, such as a display device including a cathode ray tube (CRT), an LCD, and an organic EL, an audio output device including a speaker and a headphone, a printer, a mobile phone, and a facsimile. Furthermore, the output device 879 according to the present disclosure includes various vibration devices capable of outputting tactile stimulation.
(Storage 880)
The storage 880 is a device for storing various pieces of data. Examples of the storage 880 include a magnetic storage device such as a hard disk drive (HDD), a semiconductor storage device, an optical storage device, and a magneto-optical storage device.
(Drive 881)
The drive 881 is a device that reads information recorded on the removable recording medium 901 such as a magnetic disk, an optical disk, a magneto-optical disk, and a semiconductor memory, or writes information to the removable recording medium 901.
(Removable Recording Medium 901)
The removable recording medium 901 includes, for example, a DVD medium, a Blu-ray (registered trademark) medium, an HD DVD medium, and various semiconductor storage media. Of course, the removable recording medium 901 may be, for example, an IC card mounted with a non-contact IC chip or an electronic device.
(Connection Port 882)
The connection port 882 connects an external connection device 902. The connection port 882 includes, for example, a universal serial bus (USB) port, an IEEE 1394 port, a small computer system interface (SCSI), an RS-232C port, and an optical audio terminal.
(External Connection Device 902)
The external connection device 902 includes, for example, a printer, a portable music player, a digital camera, a digital video camera, and an IC recorder.
(Communication Device 883) The communication device 883 is a communication device for connection to a network. The communication device 883 includes, for example, a wired or wireless LAN, Bluetooth (registered trademark), a communication card for wireless USB (WUSB), a router for optical communication, a router for an asymmetric digital subscriber line (ADSL), and a modem for various communications.
Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments as it is, and various modifications can be made without departing from the gist of the present disclosure. Furthermore, components of different embodiments and variations may be appropriately combined.
Furthermore, the effects in the embodiments described in the present specification are merely examples and not limitations. Other effects may be exhibited.
Note that the present technology can also have the configurations as follows.
(1)
An information processing apparatus comprising
The information processing apparatus according to (1) or (2), wherein any one of the input value and the weight coefficient is expressed by one or two first bit strings.
(3)
The information processing apparatus according to claim 1, further comprising a conversion unit that converts any one of the input value and the weight coefficient into a combination of the first bit strings.
(4)
The information processing apparatus according to any one of (1) to (3),
The information processing apparatus according to (4),
The information processing apparatus according to any one of (1) to (5), wherein the input value is expressed by the combination of the first bit strings.
(7)
The information processing apparatus according to any one of (1) to (5), wherein the weight coefficient is expressed by the combination of the first bit strings.
(8)
An information processing method comprising
An information processing program causing a computer to execute
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-023619 | Feb 2021 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/002493 | 1/25/2022 | WO |
