BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a graph showing the relation between exposure time and the noise amount;
FIG. 2 is a graph showing the relation between luminance when taking images and an S/N ratio;
FIG. 3 is a block diagram showing a configuration example of an embodiment of an imaging apparatus to which the invention is applied;
FIG. 4 is a block diagram showing the detailed configuration example of a class-classification adaptive processing unit of FIG. 3;
FIGS. 5A and 5B are views showing tap structure examples of a prediction tap and a class tap;
FIG. 6 is a flowchart explaining the noise removal processing of the imaging apparatus of FIG. 3;
FIG. 7 is a block diagram showing a configuration example of a learning apparatus which calculates a prediction coefficient;
FIG. 8 is a block diagram showing the detailed configuration example of a learning data generating unit of FIG. 7;
FIG. 9 is a block diagram showing the detailed configuration example of a noise image generating unit of FIG. 8;
FIG. 10 is a view explaining generation of learning data;
FIGS. 11A and 11B are views explaining generation of learning data;
FIG. 12 is a view explaining generation of learning data;
FIG. 13 is a view explaining generation of learning data;
FIG. 14 is a flowchart explaining learning processing of the learning apparatus of FIG. 7;
FIG. 15 is a flowchart explaining learning data generating processing of step S31 of FIG. 14;
FIGS. 16A and 16B are views explaining the concept of a detection method detecting a defective pixel;
FIGS. 17A and 17B are views explaining the concept of a detection method detecting a defective pixel;
FIG. 18 is a block diagram showing a configuration example of a defective pixel detection system;
FIG. 19 is a block diagram showing a configuration example of a second embodiment of an imaging apparatus;
FIG. 20 is a flowchart explaining noise removal processing of the imaging apparatus of FIG. 19;
FIG. 21 is a block diagram showing a configuration example of a third embodiment of an imaging apparatus;
FIG. 22 is a block diagram explaining a configuration example of a chip in the imaging apparatus of FIG. 3;
FIG. 23 is a block diagram explaining a configuration example of a chip in the imaging apparatus of FIG. 3;
FIG. 24 is a block diagram explaining a configuration example of a chip in the imaging apparatus of FIG. 3;
FIG. 25 is a block diagram explaining a configuration example of a chip in the imaging apparatus of FIG. 3; and
FIG. 26 is a block diagram showing a configuration example of an embodiment of a computer to which the invention is applied.