BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating a typical hardware configuration of an information processing apparatus according to an embodiment of the present invention;
FIG. 2 is a block diagram illustrating in detail a typical hardware configuration of a functional device in a controller for the information processing apparatus, which is shown in FIG. 1;
FIG. 3 is a block diagram illustrating in detail a typical hardware configuration of a functional device in an NETM for the information processing apparatus, which is shown in FIG. 1;
FIG. 4 is a block diagram illustrating in detail a typical hardware configuration of an interface device for the information processing apparatus, which is shown in FIG. 1;
FIG. 5 shows a typical structure of a message that is transmitted on a message bus, which is shown in FIG. 4 and other figures;
FIG. 6 illustrates the concept of data transfer operations that are performed between modules of the information processing apparatus shown in FIG. 1 via a system bus; and
FIG. 7 shows a typical structure of data that is transmitted on a data bus, which is shown in FIG. 4 and other figures.