Information Processing Device

Abstract

An information processing device retrieves external data stored in an external memory and performs predetermined first processing for the external data thus retrieved. Here, the information processing device has: a storage that stores retrieval control information transmitted from outside; and a retrieval controller that controls retrieval of the external data according to the retrieval control information. This makes it possible to efficiently perform the retrieval of data from the external memory, and alleviate the burden on a control device corresponding to a BB-CPU.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

This and other objects and features of this invention will become clear from the following description, taken in conjunction with the preferred embodiments with reference to the accompanied drawings in which:

FIG. 1 is a configuration diagram of a communication terminal of an embodiment of the invention.

FIG. 2 is a flow chart showing processing performed in the embodiment of the invention.

FIG. 3 is a configuration diagram of a conventional communication terminal.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention will be described, taking up a communication terminal (for example, a cellular telephone) as an example. Now, descriptions will be given of the configuration of this communication terminal with reference to FIG. 1.

This communication terminal 1 includes a communication processor 2, a BB-CPU 3, an IC chip 4, and the like. Though not illustrated, the communication terminal 1 also includes, for example, an operation portion provided with push-button switches and the like, a display, and a power supply connector.

The communication processor 2 is provided with an antenna, a modulation circuit, a demodulation circuit, and the like. Under the control of the BB-CPU 3, the communication processor 2 performs various communication processing such as transmission/reception of voice data of a caller and data modulation/demodulation. This ensures a communication capability which telephones are required to offer.

The BB-CPU 3 performs communication processing via the communication processor 2 and other various processing. For music playback processing using an external memory, the BB-CPU 3 writes given information into a register array 41. Note that the configuration of the BB-CPU 3 itself is basically similar to that of a commonly used CPU.

The IC chip 4 includes, for example, a register array 41, a sequencer 42, a FIFO memory 43, an audio decoder 44, a DAC 45, an SD card I/F 46, and a NAND flash I/F 47.

The IC chip 4 also includes, as a terminal for external input/output operations, a terminal to which data (external data) stored in an SD card 5 and a NAND flash 6 (hereinafter collectively referred to as the “external memory”) is inputted, a terminal to which start information and stop information (retrieval control information), which will be described later, is inputted from the BB-CPU 3, and a terminal from which data obtained by performing audio decoding and DA conversion to the retrieved digital music data is outputted.

Information for music playback can be written into the register array 41 by the BB-CPU 3. Though not limited thereto, some specific examples of information for music playback are the format of music data, bitrate at which music is played back, the time at which music starts being played back, the time at which music playback is stopped (for example, at which a given time has elapsed after the start of playback), and the type of external memory (an SD card or a NAND flash memory) from which data is read out. It is to be noted that, in the present specification, the information described above is referred to simply as the “initial information”.

According to the information written into the register array 41, the sequencer 42 reads out music data from the external memory and then writes the music data thus read out into the FIFO memory 43 (specifically, the sequencer 42 performs the procedure from steps S21 to S26, which will be described later). Since the sequencer 42 is specialized in performing the processing described above, it has a configuration and design best suited therefor. This makes efficient retrieval of external data possible.

A given amount of music data can be written into the FIFO memory 43 by the sequencer 42, and the written music data is sequentially outputted to the audio decoder 44. This helps coordinate the timing of readout of music data with the timing of decoding and audio output, making it possible to play back music with no interruption.

After the music data outputted from the FIFO memory 43 is decoded by the audio decoder 44, it is converted into an analog signal by the DAC 45. Then, a loudspeaker produces an audio output according to the music data.

Since the SD card I/F 46 and the NAND flash I/F 47 are provided as an interface with the external memory, data (for example, AD converted digital music information) can be read out and written into the SD card 5 and the NAND flash 6 via the SD card I/F 46 and the NAND flash I/F 47 respectively.

With the configuration described above, data transmission from the external memory to the FIFO memory in music playback processing is controlled by the sequencer 42. Here, the flow of the above-described data transmission will be described with reference to a flow chart shown in FIG. 2. It is to be noted that, in this embodiment, the time at which music playback is stopped is the time at which the user enters a stop instruction.

When the user enters a music playback instruction (for example, by operating a predetermined button), the BB-CPU 3 writes initial information into the register array 41 (step S1). As described earlier, the initial information includes information (start information) indicating the start of music playback.

In the meantime, the sequencer 42 monitors the information being written into the register array 41. When the start information is found to be written thereinto (Y in step S21), the sequencer 42 starts transmitting music data based on the contents of the initial information (step S22).

What is referred to here as the data transmission is data transmission from the external memory (5 or 6) to the FIFO memory 43. More specifically, the sequencer 42 monitors the amount of music data stored in the FIFO memory 43 (step S24), and, when the amount of music data stored in the FIFO memory 43 is found to be equal to or smaller than a predetermined threshold amount, the sequencer 42 further transmits a predetermined amount of music data to the FIFO memory 43 (step S25).

When the user enters a music playback stop instruction (for example, by operating a predetermined button), the BB-CPU 3 writes information (stop information) indicating stop of music playback into the register array 41 (step S13).

In the meantime, after the start of transmission of music data, the sequencer 42 checks whether or not stop information is written into the register array 41 (step S23). When stop information is found to be written thereinto, the sequencer 42 stops transmitting music data.

The procedure described above makes it possible to transmit music data from the external memory to the FIFO memory 43. For a role for the BB-CPU 3 in this procedure, the BB-CPU 3 simply has to write initial information into the register array 41 and write stop information into the register array 41 in response to a playback stop instruction.

As described above, the BB-CPU 3 is made to transmit start information and stop information (retrieval control information) to the register array 41. This makes it possible, while realizing retrieval of external data in a way in which the control of the BB-CPU 3 is reflected to some extent, to alleviate the burden on the BB-CPU 3 as much as possible.

Additionally, the retrieval of data from the external memory is mainly controlled by the sequencer (retrieval controller) 42 provided in an information processing device, and the sequencer 42 is specialized in controlling the data retrieval. This makes it possible to realize more efficient data retrieval as compared with the conventional technology by which the BB-CPU is made to perform overall control of the retrieval of external data.

The embodiment described above deals with a communication terminal. This, however, is not meant to limit the application of the invention in any way. The invention may be practiced in any other manner than specifically described above, with any modification or variation made within the spirit of the invention.

As described above, according to the information processing device of this embodiment, the retrieval of data from the external memory is mainly controlled by the sequencer (retrieval controller) 42 provided in the information processing device, and the sequencer 42 is specialized in controlling the data retrieval. This makes it possible to realize more efficient data retrieval as compared with the conventional configuration in which the BB-CPU is made to perform overall control of the retrieval of external data.

Furthermore, the BB-CPU 3 is made to transmit start information and stop information (retrieval control information) to the sequencer 42. This makes it possible, while realizing retrieval of external data in a way in which the control of the BB-CPU 3 is reflected to some extent, to alleviate the burden on the BB-CPU 3 as much as possible.

Claims

1. An information processing device for retrieving external data stored in an external memory and performing predetermined first processing for the external data thus retrieved, the information processing device comprising: a storage that stores retrieval control information transmitted from outside; anda retrieval controller that controls retrieval of the external data according to the retrieval control information.

2. The information processing device of claim 1, wherein the retrieval controller controls only processing for reading out the external data and writing the external data thus read out into a predetermined memory provided in the information processing device according to the retrieval control information.

3. The information processing device of claim 1, wherein the retrieval control information includes information indicating a timing of start or stop of the data retrieval,wherein the retrieval controller starts or stops the data retrieval according to the retrieval control information.

4. The information processing device of claim 1, wherein the external data is AD converted digital music information,wherein at least DA conversion is performed as the first processing.

5. The information processing device of claim 1, wherein the information processing device is an IC chip,wherein the IC chip comprises: an input terminal to which the external data is inputted;an input terminal to which the retrieval control information is inputted; andan output terminal from which a result obtained by the predetermined first processing is outputted to an outside.

6. A communication terminal comprising: a communication controller that controls at least communication processing; andthe information processing device of claim 1,wherein the communication controller transmits the retrieval control information to the information processing device.