BRIEF DESCRIPTION OF THE DRAWINGS
Other objects of the present invention will become clear from the following description of the preferred embodiments and the appended claims. Those skilled in the art will appreciate that there are many other advantages of the present invention by embodying the present invention.
FIG. 1 is an illustration showing the schematic structure of an information processing apparatus according to a first embodiment of the present invention;
FIG. 2 is an illustration schematically showing contents of the source file of FIG. 1 according to the first embodiment of the present invention with machine language instruction sequence;
FIG. 3 is a flowchart showing the procedure for judging information of the register changed by a compiler shown in FIG. 1;
FIG. 4 is an illustration showing information table on a valid register of the machine language instruction sequence shown in FIG. 2;
FIG. 5 is an illustration showing a changed register information table obtained as a result of the judging procedure of FIG. 3, according to the first embodiment of the present invention;
FIG. 6 is an illustration showing the result of logic products applied to the valid register information table of FIG. 4 and the result shown in FIG. 5, according to the first embodiment of the present invention;
FIG. 7 is an illustration schematically showing contents of the source file of FIG. 1 according to the second embodiment of the present invention with machine language instruction sequence;
FIG. 8 is an illustration showing a changed register information table obtained as a result of the judging procedure of FIG. 3, according to a second embodiment of the present invention; and
FIG. 9 is an illustration showing the result of logic products applied to the valid register information table of FIG. 4 and the result shown in FIG. 8, according to the second embodiment of the present invention
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the information processing method according to the present invention will be described in detail referring to the accompanying drawings. FIG. 1 illustrates the information processing method according to an embodiment of the present invention. In FIG. 1, “A” is an instruction generating device. The instruction generating device A comprises a compiler 2, an object file 3, a changed register information table 4, a valid register information table 5, a linker 6, and an execution format file 7.
The compiler 2 translates a source file 1 that is written by a user. The object file 3 is generated when the complier 2 performs compile processing. The changed register information table 4 is formed through collecting the registers whose values are changed by the interrupt processing that is generated by the compiler 2. The valid register table 5 shows the one collected whether the registers are valid or not. The linker 6 links to the object file 3. The execution format file 7 is generated with the linker 6. The execution format file 7 is loaded on an instruction memory 8, and executed by a CPU 9. For the devices other than the instruction generating device A, the typical structures are employed.
First Embodiment
FIG. 2 is an illustration schematically showing the contents of the source file 1 according to the first embodiment. Here, the meanings of the machine language instructions shown in FIG. 2 are as follows.
ADD OP1, OP2 : Transfer the contents of OP1+OP2 to OP2
ADD OP1, OP2, OP3 : Transfer the contents of OP1+OP2 to OP3
- CLR: OP Clear the contents of OP to “0”
MOV OP1, OP2: Transfer the contents of OP1 to OP2
MOV OP, (addr): Transfer the contents of OP to the address indicated by addr
- INC4 OP: Increments the contents of OP by 4
- RTI: Return from interruption program
In FIG. 2, the start and the end of the interrupt processing are specified by (_INT_START) and (_INT_END) respectively. In the case of using a method where the interrupt processing and non-interrupt processing can be discriminated, the start and the end of the interrupt processing may be specified by other methods.
The compiler 2 judges the valid register of every instruction (existing technique) from the machine language instruction sequence shown in FIG. 2. As the result of the judgments on the valid registers of each instruction, the compiler 2 generates the valid register information table 5 shown in FIG. 4. In FIG. 4, the CPU 9 comprises the registers D0, D1, D2, D3, A0, A1, A2, A3, and “1” in the table indicates that the register is valid and “0” indicates that the register is invalid.
For the machine language instruction sequence of FIG. 2, the compiler 2 judges the registers whose values are possible to be changed during the period from (_INT_START) to (_INT_END). FIG. 3 shows an example of the judging procedure thereof.
First, in FIG. 3, when (_INT_START) is detected (S1), the next instruction is judged whether or not it is an instruction by which the value of the register is changed with respect to each instruction (S2). When it is judged as the instruction by which the value is changed, there is performed judgment on the register whose value is to be changed so as to find whether or not that register has already been registered to the changed register data (S3). When it is judged that it is not registered, the register is registered to the changed register data (S4). The processing described above is repeated until detecting (_INT_END).
As a result of performing the above-described operations to the machine language instruction sequence of FIG. 2, the compiler 2 generates the changed register information table 4 that is shown in FIG. 5 from the changed register data. In FIG. 5, the CPU 9 comprises the registers D0, D1, D2, D3, A0, A1, A2, A3, and “1” in the table indicates that the register value is changed and “0” indicates that the register value is not changed.
The compiler 2 gives the changed register information table 4 and the valid register information table 5 along with the object file 3 to the linker 6. Based on the changed register information table 4 and the valid register information table 5, the linker 6 determines the position (the position in the instruction sequence) for arranging an interrupt permitting instruction (INT_PERMIT), i.e. existing technique in the instruction sequence in the following manner. The interrupt permitting instruction means an instruction where a control for permitting the interruption is carried out only when this instruction is decoded.
The linker 6 calculates the logic products with respect to each register from the values obtained from the changed register information table 4 shown in FIG. 5 and the values obtained from the valid register information table 5 shown in FIG. 4. FIG. 6 shows the results of calculations. In FIG. 6, the position where all the values become “0” is selected, and the interrupt permitting instruction (INT_PERMIT) is inserted to the position just before the selected instruction. At this time, it is not necessary to insert evacuation/return processing of the register in each interrupt processing.
Furthermore, in FIG. 6, the linker 6 may select the position where the values of the registers, for example, other than D0 and A3 become all “0”, and insert the interrupt permitting instruction (INT_PERMIT) to the position just before the selected instruction. In this case, the evacuation/return instruction for the registers D0, A3 is inserted in each interrupt processing. However, it is not necessary to insert the evacuation/return instruction for other registers.
In the first embodiment, all the interrupt processing is formed into a group so as to manage collectively. However, it is possible to control with respect to each interrupt processing individually. Such method will be described in a second embodiment.
Second Embodiment
FIG. 7 is an illustration schematically showing the contents of the source file 1 shown in FIG. 1 according to the second embodiment. First, in creating the source file, the start and the end of the interrupt processing are clearly specified with (_INT_START_[INT_NO]) and (_INT_END_[INT_NO]) respectively, by each processing. [INT_NO] indicates the interruption number, and the interruption number corresponding to the respective interrupt processing is applied to each processing.
The compiler 2 judges the valid registers by each instruction, and it is an existing technique. The compiler 2 creates the valid register information table 5 that is shown in FIG. 4, based on the judgments of the valid registers performed by each instruction. In FIG. 4, the CPU 9 comprises the registers D0, D1, D2, D3, A0, A1, A2, A3, and “1” in the table indicates that the register is valid and “0” indicates that the register is invalid.
In compiling the source file, the compiler 2 judges the registers whose values are possible to be changed during the period from (_INT_START_[INT_NO]) to (_INT_END[INT_NO]). At this time, the registers whose values are possible to be changed are judged separately with respect to each interruption number. The structure required for this judgment is the same as that of the first embodiment shown in FIG. 3.
As a result of performing the above-described operations to the machine language instruction sequence of FIG. 7, the compiler 2 generates the changed register information table 4 that is shown in FIG. 8 from the changed register data. In FIG. 8, the CPU 9 comprises the registers D0, D1, D2, D3, A0, A1, A2, A3, and “1” in the table indicates that the register value is changed and “0” indicates that the register value is not changed.
The compiler 2 gives the changed register information table 4 and the valid register information table 5 along with the object file 3 to the linker 6. Based on the changed register information table 4 and the valid register information table 5, the linker 6 determines the position for arranging an interrupt permitting instruction in the following manner. The interrupt permitting instruction means an instruction with which a control for permitting the interruption is carried out only when this instruction is decoded.
The linker 6 calculates the logic products with respect to each register from the values obtained from the changed register information table 4 shown in FIG. 8 and the values obtained from the valid register information table 5 shown in FIG. 4. FIG. 9 shows the results of calculations. In FIG. 9, the position where all the values become “0” is selected with respect to each interruption number, and the interrupt permitting instruction (INT_PERMIT_[INT_NO]) is inserted to the position just before the selected instruction. (INT_PERMIT_[INT_NO]) is an instruction that permits the interruption by specifying the interrupt processing to be permitted from the interruption number indicated in [INT_NO]. At this time, it is not necessary to insert evacuation/return processing of the register in each interrupt processing.
Besides, in FIG. 9, with respect to each interrupt processing, the linker 6 may select the position where the values of the registers other than D0, for example, for int_handler1 become all “0”, and select the position where the values of the registers other than A0 for int_handler2 become all “0”. Then, the interrupt permitting instruction (INT_PERMIT_[INT_NO]) may be inserted to the position just before the selected instruction. In this case, in each interrupt processing, the evacuation/return instruction of the register D0 is inserted for int_handler1, and the evacuation/return instruction of the registers A3 is inserted for int_handler2. However, it is not necessary to insert the evacuation/return instruction of other registers.
The present invention has been described in detail referring to the most preferred embodiments. However, various combinations and modifications of the components are possible without departing from the spirit and the broad scope of the appended claims.
Patent Application
20070266230
