Claims
- 1. An information processing system comprising:
- a plurality of information processing units, each of which includes a processor circuit integrated with a plurality of internal circuits and an internal data selection circuit for selecting result data based on priority provided to a respective internal circuit and outputting the result data output from said processor circuit, at predetermined timing; and
- a comparator which executes a comparison among result data selected and output from said internal data selection circuit of each information processing unit;
- wherein said plurality of information processing units and said comparator are on a single semiconductor substrate in one chip.
- 2. An information processing system according to claim 1, further including a first bus connecting said plurality of information processing units and a second bus for connecting said comparator with said plurality of information processing units, wherein at least one of said plurality of information processing units inputs a signal output from said internal data selection circuit of said information processing unit via said first and second buses.
- 3. An information processing system comprising:
- a plurality of information processing units, each of which includes a processor circuit integrated with a plurality of internal circuits and an internal data selection circuit for selecting result data based on priority provided to a respective internal circuit and outputting the result data output from said processor circuit, at predetermined timing and at least one of which includes a comparator which executes a comparison among result data selected and output from said internal data selection circuit of each information processing unit;
- wherein said plurality of information processing units are on a single semiconductor substrate in one chip.
- 4. An information processing system according to claim 3, further including a bus for connecting said plurality of information processing units, wherein at least one of said plurality of information processing units inputs a signal output from said internal data selection circuit in said information processing unit via said bus.
- 5. An information network system including a plurality of information processing systems which are connected to each other via a bus, each information processing system comprising:
- a plurality of information processing units, each of which includes a processor circuit integrated with a plurality of internal circuits and an internal data selection circuit for selecting result data based on priority provided to a respective internal circuit and outputting the result data output from said processor circuit, at predetermined timing;
- a comparator, which executes a comparison among result data selected and output from said internal data selection circuit of each information-processing-unit; and
- a first bus connecting said plurality of information processing units and a second bus connecting said comparator with said plurality of information processing units, at least one of said plurality of information processing units inputting a signal output from said internal data selection circuit in said information processing unit via said first and second buses
- wherein said plurality of information processing units and said comparator are on a single semiconductor substrate in one chip.
- 6. An information network system including a plurality of information processing systems which are connected to each other via a bus, each information processing system comprising:
- a plurality of information processing units, each of which includes a processor circuit integrated with a plurality of internal circuits and an internal data selection circuit for selecting based on priority provided to a respective internal circuit and outputting result data output from said processor circuit, at predetermined timing, at least one of said plurality of information processing units includes a comparator which executes a comparison among result data selected and output from said internal data selection circuit in each information processing unit; and
- a bus for connecting said plurality of information processing units, at least one of said plurality of information processing units inputting a signal output from said internal data selection circuit in said information processing unit via said bus;
- wherein said plurality of information processing units are on a single semiconductor substrate in one chip.
- 7. Information network system comprising:
- a plurality of information processing units, each of which includes a processor circuit integrated with a plurality of internal circuits and an internal data selection circuit for selecting based on priority provided to a respective internal circuit and outputting result data output from said processor circuit, at predetermined timing;
- a first comparator which executes a comparison among result data selected and output from said internal data selection circuit of each information processing unit; and
- a second comparator which executes a comparison among result data selected and output from said plurality of information processing units;
- wherein said plurality of information processing units and said comparators are on a single semiconductor substrate in one chip.
Priority Claims (1)
Number |
Date |
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Kind |
8-4127 |
Jan 1996 |
JPX |
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Parent Case Info
This application is a continuation of Ser. No. 08/778,685 filed Jan. 3, 1997 U.S. Pat. No. 5,848,238.
US Referenced Citations (11)
Foreign Referenced Citations (1)
Number |
Date |
Country |
7-129426 |
May 1995 |
JPX |
Non-Patent Literature Citations (1)
Entry |
"Fault Tolerance Achieved in VLSI", by R. Emmerson et al., IEEE Micro., Dec. 1984, pp 34-43. |
Continuations (1)
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Number |
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Parent |
778685 |
Jan 1997 |
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