Claims
- 1. A data processing apparatus, integrated on a single semiconductor substrate, and coupled to an external memory via address bus, comprising:
a clock generator including a phase lock loop circuit; and a logic device coupled to clock generator, wherein said clock generator receives a first clock signal from an oscillator, and generates a second clock signal whose frequency is lager than that of said first clock signal, and wherein said logic device receives said second clock signal from said clock generator, and performs decoding and processing of commands.
- 2. A data processing apparatus according to claim 1, wherein said frequency of said second clock signal is a multiple of said first clock signal.
- 3. A data processing apparatus according to claim 1, wherein said data processing apparatus includes a PMOS transistor and a NMOS transistor.
- 4. A data processing apparatus according to claim 1, wherein said logic device is coupled to the address bus and memory address is delivered to said address bus.
- 5. A data processing apparatus coupled to a memory via a data bus, and integrated on a single semiconductor substrate, comprising:
a clock generator, coupled to an oscillator, including a phase lock loop circuit; and a logic device coupled to said bus and clock generator, wherein said clock generator receives a first clock signal from the oscillator, and generates a second clock signal whose frequency is a multiple of said first clock signal, and wherein said logic device receives said second clock signal from said clock generator, and loads data from the memory.
- 6. A data processing apparatus according to claim 5, wherein said logic device executes floating-point arithmetic.
- 7. A data processing apparatus according to claim 5, wherein said data processing apparatus includes a CMOS transistor.
- 8. A data processing apparatus integrated on a single semiconductor substrates, comprising:
a clock generator; and a logic device couple to said a clock generator, wherein said clock generator comprises: a phase comparator coupled to a first clock signal having a first frequency, a low pass filter coupled to said phase comparator, a voltage controlled oscillator coupled to said low pass filter, a frequency divider coupled to said voltage controlled oscillator, and a feedback path coupled between said frequency divider and said phase comparator, wherein said clock generator produces a second clock signal whose frequency is a multiple of said first frequency, and wherein said logic device receives said second clock signal from said clock generator and subjects input data to a logical operation.
- 9. A data processing apparatus according to claim 8, wherein said logic device performs decoding and processing of commands.
- 10. A data processing apparatus according to claim 8, wherein said data processing apparatus includes a PMOS transistor and a NMOS transistor.
- 11. A data processing apparatus according to claim 8, wherein said logic device is coupled to the address bus and memory address is delivered to the address bus.
- 12. A data processing apparatus according to claim 8, wherein said logic device loads data from a memory via a data bus.
- 13. A data processing apparatus according to claim 8, wherein said logic device executes floating-point arithmetic.
- 14. A data processing apparatus according to claim 8, wherein said data processing apparatus includes a CMOS transistor.
Priority Claims (2)
Number |
Date |
Country |
Kind |
101930/87 |
Apr 1987 |
JP |
|
181060/87 |
Jul 1987 |
JP |
|
TITLE OF THE INVENTION
[0001] This application is a continuation of application Ser. No. 09/406,921, filed Sep. 28, 1999; which is a continuation of application Ser. No. 08/788,831, filed Jan. 27, 1997, now U.S. Pat. No. 5,974,560; which is a continuation of Ser. No. 08/279,887, filed Jul. 26, 1994, now U.S. Pat. No. 5,640,547; which is a divisional of Ser. No. 07/872,174, filed Apr. 22, 1992, now U.S. Pat. No. 5,388,249; which is a continuation of Ser. No. 07/184,782, filed Apr. 22, 1988, now U.S. Pat. No. 5,133,064; and is related to application Ser. No. 08/278,245, filed Jul. 21, 1994, now U.S. Pat. No. 5,506,982; and application Ser. No. 08/460,601, filed Jun. 2, 1995, now U.S. Pat. No. 5,542,083.
Divisions (1)
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Number |
Date |
Country |
Parent |
07872174 |
Apr 1992 |
US |
Child |
08279887 |
Jul 1994 |
US |
Continuations (4)
|
Number |
Date |
Country |
Parent |
09406921 |
Sep 1999 |
US |
Child |
10002444 |
Dec 2001 |
US |
Parent |
08788831 |
Jan 1997 |
US |
Child |
09406921 |
Sep 1999 |
US |
Parent |
08279887 |
Jul 1994 |
US |
Child |
08788831 |
Jan 1997 |
US |
Parent |
07184782 |
Apr 1988 |
US |
Child |
07872174 |
Apr 1992 |
US |