Claims
- 1. A processor system, comprising:
- a plurality of input devices, each of which is given an order of priority;
- a processing unit to which said input devices are connected and which executes predetermined processes in accordance with instructions entered from said input devices, wherein the nature of the processing which can be executed depends on the priority level of the input device which enters the instruction;
- a priority order changer which changes the order of priority given to said input devices;
- a display device; and
- a user interface which is displayed on said display device and which permits said input devices to select one of the predetermined processes at an arbitrary timing, wherein the predetermined processes include a process to change the order of priority given to said input devices by accessing said priority order changer.
- 2. A processor system as claimed in claim 1, wherein said priority order changer exchanges the priority order of one of said input devices with that of another.
- 3. The processor system of claim 2, wherein said priority order changer exchanges the priority level of the input device which accesses the priority order changer via said user interface with the priority level of an input device having the next lowest priority level.
- 4. A processor system as claimed in claim 1, wherein said priority order changer changes the priority order only by the instruction from said input devices having a specified priority order.
- 5. A processor system as claimed in claim 1, wherein said processing unit displays different pointers corresponding to each of said input devices on said display device.
- 6. A processor system as claimed in claim 5, wherein said processing unit displays said pointers with different color to define the priority order of corresponding input devices.
- 7. A processor system as claimed in claim 6, wherein said processing unit changes the color of said pointers in accordance with the change of the priority order of corresponding input devices.
- 8. A processor system as claimed in claim 1, wherein said input devices are mice.
- 9. A processor system as claimed in claim 1, wherein said input devices are wireless-connected to said processing unit.
- 10. A processor system as claimed in claim 9, wherein said input devices are connected to said processing unit via an infrared interface.
Priority Claims (1)
Number |
Date |
Country |
Kind |
6-154378 |
Jul 1994 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 08/498,411, filed Jul. 5, 1995, now abandoned.
US Referenced Citations (9)
Non-Patent Literature Citations (1)
Entry |
Nihon Keizai Shinbun; Part 2, p. 1, Oct. 1, 1993. |
Continuations (1)
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Number |
Date |
Country |
Parent |
498411 |
Jul 1995 |
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