Patent Grant
8201071
The present invention relates to information transmission and reception, such as the transmission and reception of a data-masking signal.
In modern high-speed electronic systems, pin counts are of high importance. This is the same for memory and CPU/GPU systems. Current DRAM systems offer features such as DBI (DBI=Data Bit Inversion), DM (DM=Data Masking), EDC (EDC=Error Detecting Code); training algorithms, etc. All these features require additional commands and frequently additional pins. Tradeoffs are normally made between performance, additional command complexity, pin count, and implementation complexity. For example, it is possible to provide dedicated DM pins. This enables maximum DM bandwidth, but at the cost of additional pins. Another possibility would be to transmit DM over the normal data pins. This saves pins, but at the cost of data bandwidth, since the data and the DM signal cannot be transmitted in parallel. Moreover, the common complexity is also increased. A further possibility would be to transmit the DM signal over address pins. This allows the DRAM signal to be transmitted parallel to the data, but also introduces new commands, and limits the bandwidth for transmission of the DM signal. In addition, there are normally fewer address pins in comparison to data pins.
According to an embodiment of the present invention, an information transmitting apparatus comprising an interface comprising a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information.
Accordingly, to an embodiment of the present invention, an information receiving apparatus comprising an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.
According to another embodiment of the present invention, an information transmitting apparatus, comprising an n-bit data input for an actual n-bit data word to be transmitted; a data bit inversion module coupled to the n-bit data input, and comprising an m-bit data output for an m-bit data word, the m-bit data word comprising an n-bit output data word and an inversion signal, the n-bit output data word being either inverted or non-inverted relative to the actual n-bit data word to be transmitted with the inversion signal indicating the inversion or non-inversion such that a number of 0s or 1s within bits of the m-bit data word is within a predetermined range; an m-bit data word output connectable to a receiver; an information input for an information to be transmitted; and a modifier coupled between the m-bit data output and the m-bit data word output, and being coupled to the information input, so as to provide at the m-bit data word output, the m-bit data word from the data bit inversion module or, instead of the m-bit data word from the data bit inversion module, an invalid m-bit data word in which the number of 0s or 1s within the bits of the invalid m-bit data word is not within the predetermined range.
Accordingly, to an embodiment of the present invention, an information receiving apparatus, comprising an m-bit data word input for an m-bit data word including an inversion signal and an n-bit data word; and a determiner coupled to the m-bit data word input and comprising an information output for an information signal representing an information, the information signal depending on whether the number of 0s or 1s within bits of the m-bit data word is within a predetermined range.
In the following, further embodiments of the present invention are described with respect to the drawings in more detail. There it is shown in
a and 5b are block diagrams of an information receiving apparatus for receiving data masking information according to further embodiments of the present invention;
a and 8b are the different examples for inbound and outbound data bit strings for illustrating the effect of the data bit inversion of the data bit inversion module of
The following list of reference symbols can be used in conjunction with the figures:
The interface 12 receives valid data words at the first input 14. At the second input 16, the interface 12 receives the information to be transmitted. The information to be transmitted may be of a binary type. However, the information to be transmitted may also assume more than two different states. In case of more than two states the information at the second input 16 may assume, one state of the information to be transmitted is distinguishable from the others as a state where, in fact, no information is currently to be transmitted. For example, the information to be transmitted may be used to switch a receiver to which the output 18 is coupled, into a certain operational mode, such as a power saving mode, and back. In such a case, the information to be transmitted may assume three states: no command, command to switch to this operational mode, and command to switch back from this operational mode, such as into normal mode. According to the following more detailed embodiments, the information to be transmitted is exemplarily a data masking signal, signaling as to whether a masking of the data word at the first input is to be performed or not.
Interface 12 is designed to, depending on the information to be transmitted at the second input 16, provide the data words from the first input 14 at the output 18, or a data word recognizable as an invalid data word at the output 18. To be more precise, in the absence of information to be transmitted at the second input 16, i.e., no information to be transmitted has to be signaled to the receiver, the interface 12 passes the valid data words from the first input 14 to the output 18. However, in case information to be transmitted at the second input 16 has to be signaled to the receiver, the interface 12 replaces a data word at the first input 14 by another data word recognizable as an invalid data word and outputs the latter at output 18 instead. For example, the output 18 is an n-bit output so that 2n possible bit combinations are representable at output 18. However, the valid data word at the first input 14 merely assumes bit combinations of these 2n possible bit combinations, within a subset of these 2n possible bit combinations, so that at least one of the 2n possible bit combinations lies outside this subset and may serve as the above-mentioned invalid data word. Hence, at the receiver, the signaling of the information to be transmitted is recognizable, depending on whether the data word at the output 18 is valid or invalid, i.e., falls within the subset or not.
However, in case of an invalid data word at the input 24, the interface 22 interprets this as a signalization of information to be transmitted from the transmitter side. The meaning of the signalization depends on the application. For example, in the case of binary information to be transmitted, the interface 22 merely has to indicate the detected signalization at the output 26. In case of a three-state or more-state information to be transmitted, interface 22 may distinguish between different kinds of signalizations by means of an evaluation of a part of or the whole invalid data word. For example, there may exist two or more invalid data words besides the subset of valid data words. In this case, one or more of the invalid data words may signalize a first command, whereas another invalid data word or other invalid data words may signalize another command, with the interface 22 outputting these commands at output 26. With regard to the above-mentioned example, one command could be to enter a power saving mode whereas the other command could be to close the power saving mode. In the meantime, in case of valid data words entered at input 24, no command would be signalized at output 26.
In the following embodiments, the information to be transmitted is a signalization, whether the data words to be transmitted or the data words received, respectively, are to be masked or not. That is, the information to be transmitted signalizes or is active, when the data word to be transmitted is not to be used or discarded by the receiver.
The mode of operation of the modifier 110 is substantially the same as that described above with respect to the interface 12 in
The interface 102 receives an n-bit data word at data input 104 and outputs the n-bit data word at the data output 106, which is modified or non-modified relative to the n-bit data word received from data input 104, in particular, such that the number of 0s in the n-bit data word output at the data output 106, is always within a predetermined range defined by, for example, a lower and an upper limit, or such that the number of 1s in the n-bit data word at the data output 106 is always within this predetermined range. In the following examples described in
In order to enable the reconstruction of the intended data word to be transmitted at data input 104 at the receiver side, interface 102 signalizes the modification or non-modification of the data word at the data output 106 relative to the data word at the data input 104, by means of a modification signal at the indication output 108.
The determiner 206 checks as to whether the number of 0s or 1s in the n-bit data word received from the data input 202 lies within the predetermined range or not. If not, the determiner 206 concludes that a data masking has been instructed and signals this data masking command at information receiving apparatus output 208. Otherwise, the determiner signalizes the absence of a data-masking signal.
As has been described with respect to
Elements in
a shows an information receiving apparatus 200′ which differs from
b shows an information receiving apparatus 200″ differing from the information receiving apparatus 200′ in
In the following, embodiments of the present invention will be described, according to which the data masking signal is transmitted between a transmitter and the receiver by use of unused states of a DBI interface.
The transmitter 300 comprises an 8-bit input data register 306, along with a data masking signal bit register 308, as well as a processor 310, a DBI module 312, a multiplexer 314 and an invalidator 316. The processor 310 is connected between the input data register 306 and the DBI module 312 and performs some processing on the data in the input data register 306, i.e., the 8-bit D0 to D7. The processing may comprise an encoding or scrambling or the like. Alternatively, processor 310 may be absent with the input data register 306 being directly coupled to the input of the DBI module 312.
The DBI module 312 is for mapping the incoming 8-bit data words into DBI'ed data words, such that the DBI'ed data words have a number of 0s or 1s, respectively, which is always below a predetermined limit, as will be described in more detail with respect to
The receiver 400 comprises a determining/discarding module 406, a reconstruction module 408 and a data mask command signaling output 410. The determining/discarding module 406 has an input connected to the data pins 404 and two data outputs, one of which is connected to an input of reconstruction module 408, and the other being connected to the data mask command signaling output 410. A further input of the reconstruction module 408 is connected to the DBI pin 402. Further, the reconstruction 408 comprises a data word output 412.
In the following, the functionality of the individual elements of
Data words to be transmitted to the receiver side are consecutively written into input data register 306. The data to be transmitted is accompanied by a data masking signal bit DM, which is written into data masking signal bit register 308. The registers 306, 308 are written to by means of other circuitry in the transmitter 300 not shown here, for ease of understanding of the main principles, with respect to the data masking signal transmission. The processor 310 performs some processing on the data DO to D7, and forwards the result to the DBI module 312.
The DBI module 312 performs, for example, a DBI DC functionality. That is, the DBI module 312 tries, for example, to minimize the occurrences of 0s in case the channel 500 is a high terminated system. Alternatively, the DBI module 312 may be implemented to minimize or reduce the occurrence of 1s, in case the channel 500 is a ground terminated system. The way, the DBI module 312 performs this minimization/reduction is described with respect to
In the following, it is assumed that each 8-bit word D<7:0> is accompanied by a further DBI bit which is preliminarily set to either 1 or 0. In particular, in the following example of
As is shown in
In order to illustrate the functionality of the DBI module 312 more clearly, two examples for an inbound data string and a resulting outbound data string are shown in
In the example of 8b, there are five ‘0’-bits in the data bit string including D<7:0> and DBI bit. Accordingly, the DBI module 312 sets the DBI bit to 0 and inverts the data bits D<7:0> with the resulting data string being shown at the bottom of
As already mentioned above, the DBI bit does not have to be preset. Accordingly, the determination in step 602 may be performed on the data bit D<7:0> only whereas the setting of the DBI bit could originally take place in steps 606 and 608, respectively, thereby forming the data bit string. Even in this case, the DBI state meanings of 0 and 1 may be switched. However, in this case only the number of 0s in the eight data bits D<7:0> would be limited to up to 4, and the resulting data string at 610 could have five zeros. In this case, the distinction between valid and non-valid data strings at the receiver would have to be performed based on the 8 data bits only by checking as to whether the number of 0s in these eight bits does not exceed four.
In any case, the DBI bit is forwarded to the DBI pin 302, whereas the remaining part of the data string is forwarded to multiplexer 314 and invalidator 316, respectively. As becomes clear from the above description of
The DBI data mapping performed by DBI module 312 is exploited to send the DM information in data masking signal bit register 308, by using these non-occurring or disallowed states, what will be described in more detail in the following.
As can be seen from
At the receiver side, the DBI receiver 400 is able to recognize a disallowed DBI state, i.e. more than M occurrences of 0s in the D-bit data string consisting of the DBI bit at DBI pin 402 and the data bits at data pins 404. If such a state is received, then the data is simply discarded. To this end, the determining/discarding module 406 checks the incoming data bits D<7:0> to see if the number of 0s in these data bits exceeds or is equal to D-M. If this is the case, the D-bit data string received from the transmitter side is invalid and determining/discarding module 406 interprets this as a data mask command, which is signaled at data mask command signaling output 410 indicating that the data bits at the data pins 404 have to be ignored. Otherwise, determining/discarding module 406 forwards the data bits D<7:0> to the reconstruction module 408, which reconstructs, based on these bits, along with the DBI bit, the actual data word D0 to D7 and outputs this data at data word output 412.
Various modifications could be performed on the above embodiments, for example, the DBI module 312 could be designed to reduce or minimize the number of 1s instead of the number of 0s in the data word in input data register 306. Moreover, the meaning of the DM bit in data masking signal bit register 308 could be logically inverted to indicate the masking of data when being 0. Further, it is possible to code additional information into the DM state to improve the probability of proper transmission as well. It is recalled, for example, that more than M 0s is a disallowed state, and will therefore be handled as DM=1 at the receiver 400. If only M plus 1 0s are coded, as illustrated in
In other words, the above mentioned embodiments of the present invention provide a method for transmitting information, such as a data mask signal, by overloading a data interface, such as by overloading data bit inversion states. Advantageously, the above-described embodiments do not suffer from problems resulting from other possibilities for transmitting the data mask signal. For example, the provision of a dedicated DM pin has the disadvantage in that this additional pin has to be provided on the chip. In comparison to sending the DM signal over the existing data+DBI pins, the above embodiments do not suffer from data and possibly DM signal bandwidth reduction, due to inability of sending data and DM signals in parallel. Moreover, no new command has to be coded on the command and address pins. Similarly, sending the DM signal over the address pins can be disadvantageous in that the DM bandwidth is reduced due to the reduced number of address pins in comparison to data pins, and the need for an additional command. Moreover, a mixing of internal addresses and data paths is not necessary. In comparison to these comparative possibilities, the above-mentioned embodiments send the information via invalid states of an existing interface. For example, in the embodiment of
A further advantage of the embodiment of
With regard to the above embodiments, it is noted that especially in the embodiments of
Regarding the possible implementations, it is noted that the discarder 214 in
Depending on certain implementation requirements of the embodiments of the inventive methods, embodiments of the inventive methods can be implemented in hardware or in software. The implementation can be performed using a digital storage medium, in particular, a disc, a CD or a DVD, having an electronically readable control signal stored thereon, which cooperates with a programmable computer system, such that an embodiment of the inventive methods is performed. Generally, an embodiment of the present invention is, therefore, a computer program product with a program code stored on a machine-readable carrier, the program code being operative for performing an embodiment of the inventive methods, when the computer program runs on the computer, a processor, or another integrated circuit. In other words, embodiments of the inventive methods are therefore, a computer program having a program code for performing at least one of the inventive methods, when the computer program runs on a computer, processor, or another integrated circuit.
While the foregoing has been particularly described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various other changes in the forms and details may be made without departing from the broader spirit and scope thereof. It is to be understood that various changes may be made in adapting to different embodiments without departing from the broad concept disclosed herein, and comprehended by the claims that follow.
Lastly, it is noted that in the present application the term “coupled” is used to indicate that a certain module is directly or indirectly connected to another module.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3851106 | Jacobaeus | Nov 1974 | A |
| 4223326 | D'Amato et al. | Sep 1980 | A |
| 4284843 | White | Aug 1981 | A |
| 4309694 | Henry | Jan 1982 | A |
| 4486739 | Franaszek et al. | Dec 1984 | A |
| 4499454 | Shimada | Feb 1985 | A |
| 4736464 | Tanson | Apr 1988 | A |
| 4811361 | Bacou et al. | Mar 1989 | A |
| 4876695 | Witters et al. | Oct 1989 | A |
| 4975916 | Miracle et al. | Dec 1990 | A |
| 5025458 | Casper et al. | Jun 1991 | A |
| 5048062 | Gregg et al. | Sep 1991 | A |
| 5144305 | Gotz et al. | Sep 1992 | A |
| 5177482 | Cideciyan et al. | Jan 1993 | A |
| 5434872 | Petersen et al. | Jul 1995 | A |
| 5546425 | Auclair et al. | Aug 1996 | A |
| 5692021 | Walker | Nov 1997 | A |
| 5825824 | Lee et al. | Oct 1998 | A |
| 5862160 | Irvin et al. | Jan 1999 | A |
| 5907566 | Benson et al. | May 1999 | A |
| 5944843 | Sharma et al. | Aug 1999 | A |
| 6243768 | Khandekar | Jun 2001 | B1 |
| 6346895 | Lee et al. | Feb 2002 | B1 |
| 6351501 | Murdock | Feb 2002 | B1 |
| 6405340 | Irvin et al. | Jun 2002 | B1 |
| 6414956 | Szczepanek | Jul 2002 | B1 |
| 6535858 | Blaukovitsch et al. | Mar 2003 | B1 |
| 6768429 | Kuo et al. | Jul 2004 | B2 |
| 6910167 | Barton et al. | Jun 2005 | B2 |
| 6950448 | Tornetta et al. | Sep 2005 | B2 |
| 7016430 | Grivna et al. | Mar 2006 | B1 |
| 7024518 | Halbert et al. | Apr 2006 | B2 |
| 7038599 | Kahlman | May 2006 | B2 |
| 7158575 | Gorecki et al. | Jan 2007 | B2 |
| 7187307 | Schmidt et al. | Mar 2007 | B1 |
| 7222270 | Meaney et al. | May 2007 | B2 |
| 7236686 | Ezaki | Jun 2007 | B2 |
| 7249305 | Kojima et al. | Jul 2007 | B2 |
| 7280053 | Hori | Oct 2007 | B2 |
| 7298294 | Oberg et al. | Nov 2007 | B1 |
| 7535836 | Lund | May 2009 | B2 |
| 20020156953 | Beiley et al. | Oct 2002 | A1 |
| 20030202610 | Terada et al. | Oct 2003 | A1 |
| 20030227947 | Shin et al. | Dec 2003 | A1 |
| 20030237041 | Cole et al. | Dec 2003 | A1 |
| 20040153613 | Roohparvar | Aug 2004 | A1 |
| 20040153952 | Sharma et al. | Aug 2004 | A1 |
| 20040257248 | Lund et al. | Dec 2004 | A1 |
| 20060153116 | Lida et al. | Jul 2006 | A1 |
| 20060215473 | Dietrich | Sep 2006 | A1 |
| 20060267810 | Widmer | Nov 2006 | A1 |
| 20070204204 | Sul et al. | Aug 2007 | A1 |
| Number | Date | Country |
|---|---|---|
| 10 2005 011 386 | Sep 2006 | DE |
| Number | Date | Country | |
|---|---|---|---|
| 20080115030 A1 | May 2008 | US |
