Patent Application
20080309384
The invention relates to redundancy initialization circuitry, and more particularly to redundancy initialization circuitry having improved resistance to parasitic leakage current and variations in power-on ramp rates.
In the manufacture of large-area integrated circuit systems, it is common for defects to occur in at least some of the elements that make up the systems. In order to increase the yield of the systems, redundant circuitry is sometimes added that can be used to selectively replace defective primary circuit elements. For example, in memory systems which may contain highly symmetric and repetitive device layouts, additional device columns or rows may be included in the circuit layout. These additional columns or rows may be selectively activated through redundancy switches. Specifically, if during circuit testing a primary element is determined to be defective, a corresponding redundancy switch can be programmed to enable redundant circuitry to replace the functionality of the defective element.
Several types of redundancy switch elements are programmed via the selective blowing of integrated fuses located within the redundancy switch circuitry. These integrated fuses are ideally binary elements which act as resistive elements in their initial (default) state, and act as open circuits when blown. In practice, however, blown fuses usually exhibit a certain amount of leakage current. In many cases, this leakage current may manifest in relatively benign consequences, such as minor increases in power consumption by the redundancy switch. However, depending on the switch circuitry configurations this leakage current also may result in the failure of the redundancy switch to function properly. This is especially true in newer technologies, where smaller device dimensions have resulted in increased leakage currents.
In the programmed position, the integrated fuses 106 and 108 are blown and ideally act as open circuits. In this configuration, node N1114 is no longer resistively coupled to VSS 122 and the capacitive coupling with VDD 120 through MP1118 eventually pulls N1114 up to VDD. This rise in voltage of N1114 is sufficient to turn on transistor MN1116 and set node N2110 to VSS. With N2110 tied to VSS 122, transistor MP2112 is turned on, thereby reinforcing the voltage of N1114 at VDD. With N1114 set to VDD, the output enable signal 102 is set to VDD and its complement 104 is set to VSS.
However, as noted above fuses do not act as ideal open circuits when blown and instead may present a source of leakage current. Thus, when switch control circuit 100 is in the programmed position and fuses 106 and 108 are blown, node N1114 is not entirely de-coupled from node VSS 122 and leakage current may flow from N1114 through fuse 108 to reference voltage VSS 122. Moreover, if blown fuse 108 provides too much leakage current, node N1114 may not be pulled up to VDD through the capacitive coupling of MP1118. In this case, N1114 is maintained at VSS and the output signals 102 and 104 are placed in the incorrect state. This condition is more pronounced when the power-on ramp rate of VDD is slower, since leakage current through blown fuse 108 is provided a greater opportunity to drain charge provided to N1114 through capacitive coupling to VDD.
Thus, there exists the possibility that existing switch control circuits may operate incorrectly in certain situations, especially when blown fuses provide relatively large amounts of leakage current or when power-on ramp rates of reference voltages are relatively slow. Therefore, it would be beneficial to have a system or circuit that was more resistant to the conditions presented by these situations.
A system for initializing redundant circuitry is presented. The system includes a power-on reset circuit comprising a voltage switch, and a single fuse redundancy switch circuit, which together provide improved resistance against parasitic leakage currents.
In one example, the system comprises a power-on reset circuit having a detector circuit that receives a first reference voltage signal VDD, and outputs a detection signal, where the detection signal indicates that VDD has reached a threshold voltage; and a latch that receives the detection signal and outputs a power-on reset signal. The system further comprises a switch circuit connected to a first reference voltage signal VDD and a second reference voltage signal VSS, the switch circuit receiving the power-on reset signal and outputting an enable signal, and comprising a fuse where the enable signal evaluates to VDD when the fuse is blown and to VSS when the fuse is not blown. Additionally, the system may output a complement of the enable signal. Generally, the detection signal indicates that VDD has reached the threshold voltage by rising to substantially the voltage of VDD, and the power-on reset signal is VSS prior to the threshold voltage being reached, and is VDD after the detection signal indicates that VDD has reached the threshold voltage.
In another example, the switch circuit may comprise a PMOS transistor that selectively couples VDD to an internal node and that is operated by the power-on reset signal, an NMOS transistor that selectively couples the fuse to the internal node and that is operated by the power-on reset signal, another NMOS transistor that selectively couples an output node to VSS and that is operated by the internal node, another PMOS transistor that selectively couples the internal node to VDD and that is operated by the output node, and an inverter that receives the output node and outputs the enable signal. The latch may additionally comprise another second inverter that receives the enable signal and outputs an enable complement signal. Further, the switch circuit further comprises two PMOS transistors connected in series so as to selectively couple VDD to the output node, and which are operated by the internal node. Alternatively, a single transistor operated by the internal node may be used to selectively couple VDD to the output node. Additionally, the switch circuit may comprise other components, such as a capacitor connected between VDD and the internal node, a second capacitor connected between VSS and the output node, and a diode-connected PMOS transistor connected between VDD and the internal node.
In yet another example, the detector circuit may comprise a voltage divider circuit that outputs a voltage divider signal, where the voltage divider signal varies proportionately with the voltage differential between VDD and VSS, and a trigger circuit that receives the voltage divider signal and outputs the detection signal, where the detection signal indicates that VDD has reached the threshold voltage when the voltage divider signal exceeds a switch point voltage. The trigger circuit may comprise a hysteresis device, such as a Schmitt trigger, having a forward trigger voltage that receives the voltage divider signal and outputs a trigger signal, where the trigger signal indicates if the voltage divider signal exceeds the forward trigger voltage, and an inverter that receives the trigger signal and outputs the detection signal. The voltage divider circuit may comprise a first resistor and a second resistor connected in series. Further, the detector circuit may comprise a first PMOS transistor that selectively couples VDD to the voltage divider circuit, and the latch may generate a feedback signal such that the first PMOS transistor receives the feedback signal and decouples VDD from the voltage divide circuit when the feedback signal approaches VDD.
In yet another example, the latch may comprise a NOR device that outputs a NOR output signal, a first inverter that receives the NOR output signal and outputs a feedback signal, and wherein the NOR device receives as input the detection signal and the feedback signal. The latch may further comprise additional components such as a diode-connected PMOS transistor connected between VDD the NOR output signal, a diode-connected NMOS transistor connected between VSS and the feedback signal, a capacitor connected between the NOR output signal and VDD, and a third capacitor connected between the feedback signal and VSS.
These as well as other aspects and advantages will become apparent to those of ordinary skill in the art by reading the following detailed description, with reference where appropriate to the accompanying drawings. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the invention as claimed.
Certain examples are described below in conjunction with the included figures, wherein like reference numerals refer to like elements in the various figures, and wherein:
A system and method for initializing circuitry, such as redundant circuitry, is described. The system includes a power-on ramp circuit for measuring the ramp-up of the power reference voltage, and which quickly ramps up an output signal to the level of the power reference voltage once the power reference voltage exceeds a certain threshold. In addition, the system includes a switch circuit, such as may be used to enable redundant circuitry, which can be programmed through the conditioning of a single fuse.
Referring to
The control switch circuit 204 is connected to reference voltages VDD 212 and VSS 214, and receives signal NPOR 206 output by the power-on reset circuit 202. Switch circuit 204 outputs an enable signal 210 as well as the complement of the enable signal 208. The switch circuit 204 can be programmed to operate in two different states: a first (inactive or default) state, and a second (active) state. In the inactive state, the switch circuit 204 functions to drive the enable signal 210 low and its complement 208 high. In the active state, the switch circuit 204 functions to drive the enable signal 210 high and its complement 208 low. Given the programmable nature of control switch circuit 204 and corresponding output enable signal 210, the switch circuit 204 can be used to selectively activate or deactivate one or more associated circuits by providing either a high or low output signal. The enable complement signal 208 can further be used to coordinate the selective activation or deactivation of the associated circuits.
For example, control switch circuit 204 can be used to coordinate the activation of a portion of a memory array (such as a row or column in a memory array) and redundant circuitry associated with the portion of the memory array. The portion of the memory array can be controlled through the enable complement signal 208 and the redundant circuitry can be controlled through the enable signal 210. Accordingly, in the inactive state the enable signal 208 is held low and disables the redundant circuitry, while the enable complement signal 210 is driven high and enables the portion of the memory array. If the switch circuit 204 is placed in the active state (for example, due to a determination that the portion of the memory array is non-functional), the enable signal 208 is driven high to enable the redundant circuitry, while the enable complement signal 210 is held low to disable the portion of the memory array.
In one embodiment, the control switch circuit 204 is programmed through the use of a fuse. The fuse is initially maintained in an un-blown (normal or default) state, which corresponds with the inactive state of the control switch circuit 204. The programmable fuse can then be blown, thereby placing the control switch circuit 204 into an active state.
According to an embodiment, the detector circuit 302 may comprise a voltage divider circuit 303 and a trigger circuit 305. The voltage divider circuit 303 outputs a voltage divider signal 312 whose voltage is a fractional portion of the voltage differential between VDD 212 and VSS 214. Accordingly, the voltage divider signal 312 of the voltage divider circuit 303 varies directly and proportionately with the voltage differential between VDD and VSS. In one embodiment, as shown in
The voltage divider circuit 303 may further comprise a capacitor 314 connected in series with the second resistor 308, and having a first terminal connected to voltage divider signal 312 and a second terminal connected to VSS 214. Capacitor C1314 may serve as a noise filter to prevent jitter in power supply reference voltage VDD 212 from artificially driving the voltage divider signal 312 above the threshold value of the trigger circuit, as further described below.
The trigger circuit 305 receives the voltage divider signal 312 output by the voltage divider circuit 303 and outputs the detection signal 319. The trigger circuit 312 drives detection signal 319 so as to indicate whether voltage divider signal 312 has reached or exceeds a switch point voltage. In one embodiment, and as shown in
As noted above, power-on reset circuit 300 further comprises a latch 304 that receives the detection signal 319 from detector circuit 302 and generates a power-on reset signal. Latch 304 is one-sided, such that it will latch a high value in response to the detection signal 312 rising above a threshold value, but will not respond to a drop in the detection signal 312 after that point. Latch 304 resets to a low value upon a reset of the circuit, or when power is no longer supplied to reference voltage VDD 212. In one embodiment, latch 304 comprises a NOR gate 320, and an inverter 322, where inverter 322 receives the output signal 321 of NOR gate 320. NOR gate 320 receives as its input the detection signal 319 and the output of inverter 322. The feedback provided to NOR gate 320 through the input of its inverted output reinforces the one-sided nature of latch 304. The output 323 of inverter 322 may serve as the output NPOR signal of power-on reset circuit 300. Alternatively, latch 304 may further comprise two inverters 332 and 334 connected in series, which may act as buffers. The output of the inverter 334 is representative of the relative voltage level (i.e. low or high) of output node 323, and may also serve as the output NPOR signal of power-on reset circuit 300.
In one embodiment, latch 304 may further comprise capacitors C2324 and C3326. Capacitor C2304 may have a first terminal coupled to VDD 212 and a second terminal coupled to the output node 321 of NOR gate 320, while capacitor C3326 may have a first terminal coupled to VSS 214 and a second terminal coupled to the output node 323 of inverter 322. Accordingly, capacitors C2324 and C3326 may provide capacitive coupling for node 321 to VDD and node 323 to VSS, respectively, during power-up. Further, a diode-connected PMOS transistor 328 may be connected in parallel with capacitor C2324, having its source and gate connected to VDD 212, and its drain connected to the output node 321 of the NOR gate. Similarly, a diode-connected n-type MOS (NMOS) transistor may be connected in parallel with capacitor C3326, with its source and gate connected to VSS 214 and its drain connected to the output node 323 of inverter 322. The diode connected transistors 328 and 330 serve to discharge nodes 321 and 323, respectively, during a power-down event.
Additionally, latch 304 may provide feedback to the detection circuit 302 via the output signal 323 of inverter 322. Specifically, output signal 323 may serve as a feedback signal that acts as the gate control input for PMOS transistor 310, thereby controlling the selective coupling of the voltage divider circuit 303 with VDD 212. After the detection signal 319 goes high, output node 321 of NOR gate 320 is forced low and output node 323 of inverter 322 is forced high. When node 323 goes high, PMOS transistor 310 is turned off, thus terminating the DC path to ground created by the voltage divider circuit 303 in the detector circuit 302.
According to the embodiment illustrated in
To provide output signals 210 and 208, two inverters 426 and 428 are connected in series to internal node B. The first inverter 428 receives internal node B 422 as its input, and produces the enable signal 210 as its output. The second series inverter 428 receives the output of the first inverter 426, and produces the enable complement signal 208. Both inverters 426 and 428 act as buffers between the switch circuit 400 and any circuits receiving outputs 208 and 210.
Switch circuit 400 further comprises a fourth PMOS transistor 416 having it source connected to VDD 212, its drain coupled to internal node A 404, and its gate coupled to output node B 422. Through PMOS transistor 416, output node B 422 affects the voltage of internal node A 404 and provides feedback in the system.
In an alternative embodiment, the two PMOS transistors 418 and 420 located in series between VDD 212 and internal node B 422 may be replaced by a single PMOS transistor (so that MP5 is removed altogether, for example). This single PMOS transistor may have its source coupled to VDD 212, its drain coupled to output node B 422, and its gate coupled to internal node A 404.
The switch circuit may further comprise additional devices and components in order to improve circuit performance or to provide additional stability. For example, switch circuit 400 comprises a diode-connected PMOS transistor 412 having its source and gate connected to VDD 212, and its drain coupled to internal node A 404. In addition, the switch circuit may comprise one or more capacitors, such as a first capacitor 414 having one terminal coupled to VDD 212 and its other terminal coupled to internal node A 404, or a second capacitor 424 having one plate coupled to output node B 422 and the other terminal coupled to VSS 214.
Although switch circuit 400 is programmed by a blowing fuse 402, and may therefore be susceptible to the effects of leakage current through the blown fuse, these effects are significantly mitigated when input signal NPOR 206 is provided by a circuit (such as power-on reset circuit 300) that ensures a relatively quick ramp rate for the input signal after VDD reaches the threshold voltage. Thus, in a system for initializing circuitry that includes power-on reset circuit 300 and switch circuit 400, the output signals evaluate to their intended state regardless of the ramp rate of the reference voltage.
As noted above, the output signals 208 and 210 of switch circuit 400 are used to initialize circuitry to a correct state upon power-up. Therefore, initially signal NPOR 206 is low which keeps PMOS transistor 406 on and keeps NMOS transistor 408 off. As a result, internal node A 404 follows the voltage of VDD 212 and turns on NMOS transistor 410. With NMOS transistor 410 turned on, output node B 422 is held at VSS, thereby forcing output enable signal 210 to a high state, and its complement 208 to a low state. With node B 422 at VSS, PMOS transistor 416 provides feedback and reinforces node A 404 at VDD.
Prior to the switching event of the input signal 206, the behavior of the switch circuit 400 is independent of the condition of the fuse 402. However, after the switching event the switch circuit 400 evaluates output signals 208 and 210 based on whether the fuse 402 is blown or un-blown. For the initial state in which fuse 402 is un-blown, when the switching event occurs and input signal 206 rises to VDD, PMOS transistor 406 turns off and NMOS transistor 408 turns on. With fuse 402 intact, internal node A 404 discharges to VSS, thereby turning on PMOS transistors 418 and 420, pulling output node B 422 high to VDD, and cutting off the feedback signal through PMOS transistor 416. After passing through inverters 426 and 428, the signal at output node B 422 forces enable signal 210 low and the enable complement signal 208 high.
In the active (programmed) state, fuse 402 of switch circuit 400 is blown, thereby severing the direct coupling between internal node A 404 and VSS 402. Again, prior to the switching event PMOS transistor 406 is on, NMOS transistor 408 is off, internal node A follows the voltage of VDD 212, internal node B 422 is held low to VSS 214, and feedback through PMOS transistor 416 reinforces the high state of internal node A 416. After the switching event occurs and input signal NPOR 206 quickly ramps up to VDD, PMOS transistor 406 is turned off and NMOS transistor 408 is turned on. Although there may be some parasitic leakage through the blown fuse, the feedback signal through PMOS transistor 416 ensures that internal node A stays high, which in turn maintains node B at VSS by keeping NMOS transistor 410 on. The low state of output node B 422 at VSS forces output enable signal 210 to a high state, and its complement 208 to a low state.
From the foregoing, it will be observed that numerous variations and modifications may be effected without departing from the spirit and scope of the invention as described above. It is to be understood that no limitation with respect to the specific methods or processes illustrated herein is intended or should be inferred. For example, where specific devices have been discussed for illustrative purposes, other devices having equivalent inputs and responses may be substituted in order to for accomplish the intended functions. In addition, it is understood that various presently unforeseen or unanticipated alternatives, modifications, variations or improvements may be subsequently made by those skilled in the art, which are intended to be encompassed by the following claims and those equivalents to which they are entitled.
The United States Government may have acquired certain rights in this invention pursuant to Contract No. DTRA01-03-D-0018-0005, awarded by the Defense Threat Reduction Agency.
