The invention will now be described in detail with reference to the following figures in which:
The present invention will now be described in detail with reference to one or more embodiments of the invention, examples of which are illustrated in the accompanying drawings. The examples and embodiments are provided by way of explanation only and are not to be taken as limiting to the scope of the invention. Furthermore, features illustrated or described as part of one embodiment may be used with one or more other embodiments to provide a further new combination.
It will be understood that the present invention will cover these variations and embodiments as well as variations and modifications that would be understood by a person skilled in the art.
As can be seen in
UDSM processes contain transistors capable of taking about 1.8V across the gate terminal and about 3.3V across the drain source terminals. These transistors are known as drain extended transistors. An aspect of the invention uses these existing drain extended transistors to design the 3V input buffer.
In one embodiment, the input buffer is designed to take an I/O VDD supply ranging from 2.7V to 3.3V. The VIL for the input buffer ranges from −0.3V to 0.3*VDDIO. The VII I for the input buffer ranges from 0.7*VDDIO to VDDIO+0.3. The input buffer therefore has to detect voltages ranging from—0.3V to 0.99V as low, and voltages ranging from 1.89V to 3.6V as high. It will be appreciated that the difference between VIL(max) and VIH(min) is only 0.9V.
According to one aspect of the present invention, the input signal is coupled to the core of the UDSM process via the gate of a degenerated drain extended transistor. However, the input signal should ideally be coupled through the gate when the source of the transistor is not grounded. The source may be raised from ground by the use of another device.
The circuit as shown in
In this configuration, transistor M2 degenerates the input transistor M1. The source of the input transistor M1 is a very low impedance node (designated as “MID” in
R
out=(gm2/gds2)/gm1 (1)
where the subscript number refers to the transistor number in
Since MID is a low impedance node, it responds very quickly to the input signal. Whenever the input signal goes high, MID follows the input signal due to the low impedance.
Due to the configuration of the transistors M2 and M3, transistor M1 goes into linear mode when the input signal goes very high. This limits the value of MID to 2(VT+VGST) (where VT is the threshold voltage of the transistor). This can be designed to be within 1.8V. When the input signal is only at VII I(min)transistor M1 enters saturation mode and the MID node goes to VINPUT−VT. This is high enough to be detected as a high by a first inverter 20. When the input signal goes low, transistor M1 cuts off, causing the current in resistor R1 to go to zero.
When this happens, node FB goes towards the VDDIO voltage, which is coupled to node FB1 through transistor M3. This then significantly increases the drive voltage of transistor M2, which then quickly pulls down the MID node.
The node MID is coupled to the core inverters 20 and 30 using transistor M4. This transistor ensures that the node MID1 (the input to the core inverters) is always lower than 1.8−VT(M4), which is within core transistor reliability limits.
Capacitor C1 is also provided at nodes FB and FB1 to increase the speed of coupling between these nodes.
the circuit of