Patent Application
20080007443
The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
The inverter circuit 22 is used to drive the PMOS transistor of the MOS switch 41. The MOS switch 41 is turned on and off in response to the voltage level on the analog/digital select terminal 12. Specifically, the MOS switch 41 is turned on when the analog/digital select terminal 12 is pulled up to the “High” level (simply referred to as the “H” level, hereinafter), while being turned off when the analog/digital select terminal 12 is pulled down to the “Low” level (simply referred to as the “L” level, hereinafter).
The MOS switch 42 is turned on and off in response to the voltage level on the analog/digital select terminal 12. Specifically, the MOS switch 42 is turned off when the analog/digital select terminal 12 is pulled up to the “H” level, while being turned on when the analog/digital select terminal 12 is pulled down to the “L” level. The MOS switches 41 and 42 perform complementary operations; the MOS switch 42 is turned off when the MOS switch 41 is turned on, and vice versa.
In this configuration, the MOS switch 41 and the resistor 32 operate together as a feedback circuit when the analog-digital select terminal 12 is pulled up to the “H” level. The MOS switch 41 is electrically connected between the output terminal 13 and the non-inverting input of the differential amplifier 21 to function as a feedback resistor, when the analog-digital select terminal 12 is pulled up to the “H” level. This allows the differential amplifier 21 to operate as a positive-phase amplifier that provides in-phase amplification for the input signal fed to the signal input terminal 11. When the analog-digital select terminal 12 is pulled down to the “L” level, on the other hand, the negative feedback loop is cut off, and the differential amplifier 21 operates as a comparator that compares the voltage levels on the inverting and non-inverting inputs thereof. In this case, the resistors 33 and 31 functions as a reference voltage level generator which generates a reference voltage level through voltage division of the power supply level Vdd.
The signal input terminal 11 receives an analog input signal or a digital input signal, and the signal output terminal 13 outputs an analog output signal or a digital output signal, accordingly. For achieving analog amplification of the input signal fed to the signal input terminal 11, the analog-digital select terminal 12 is pulled up to the “H” level. For digitizing the signal fed to the signal input terminal 11, on the other hand, the analog-digital select terminal 12 is pulled down to the “L” level.
One advantage of the input interface circuit according to the first embodiment is that the gain of the analog amplification can be adjusted independently of the threshold level of the signal digitization of the input signal.
A description is first given of the analog amplification of the input signal fed to the signal input terminal 11. In this case, the analog-digital select terminal 12 is pulled up to the “H” level, and the MOS switch 42 is turned off, while the MOS switch 41 is turned on. As a result, the output of the differential amplifier 21 is connected with the inverting input of the differential amplifier 21 through the resistor 32, and also connected to ground through the resistor 31. This allows the input interface circuit to operate as a positive-phase amplifier.
For the case that the on-resistance of the MOS switch 41 is sufficiently smaller than the resistance R2 of the resistor 32 (this is usually the case in practice), the gain Ga of the positive-phase amplifier is as follow:
Ga=1+R2/R1. (1)
For the signal digitalization of the input signal fed to the signal input terminal 11, on the other hand, the analog-digital select terminal 12 is pulled down to the “L” level. This results in that the MOS switch 42 is turned on, while the MOS switch 41 is turned off. In this case, the output signal of the differential amplifier 21 is not fed back, and the differential amplifier 21 operates as a comparator. Therefore, the signal level on the output of the differential amplifier 21 depends on the comparison result between the voltage levels on the inverting and non-inverting inputs. The inverting input of the differential amplifier 21 receives a reference voltage level Vth generated through voltage division of the power supply voltage Vdd by the resistors 33 and 31. The reference voltage level Vth is identical to the threshold level of the signal digitization of the input signal. When the signal level on the non-inverting input is higher than the reference voltage level Vth, the output of the differential amplifier 21 is pulled up to the “H” level. When the signal level on the non-inverting input is lower than the reference voltage level Vth, on the other hand, the output of the differential amplifier 21 is pulled down to the “L” level.
When the on-resistance of the MOS switch 41 is sufficiently smaller than the resistances R1 and R3 of the resistors 31 and 33 (this is usually the case in practice), the reference voltage level Vth, which is the threshold level of the signal digitization, is as follow:
Vth=Vdd×R1/(R1+R3). (2)
It should be noted that the gain Ga of the positive-phase amplifier depends on the resistance R2 while not depending on the resistance R3, and that the reference voltage level Vth depends on the resistance R3 while not depending on the resistance R2. This implies that the gain Ga of the positive-phase amplifier can be adjusted independently of the reference voltage level Vth.
The signal input terminal 11 is connected with the non-inverting input (denoted by the symbol “+”) of the differential amplifier 21. The MOS switch 42, the resistor 33, and the synthetic resistor circuit 23 is serially connected between a power supply line VDD and a ground line GND. The control terminal (or the gate) of the MOS switch 42 is connected with an analog/digital select terminal 12. The connecting node of the resistor 33 and the synthetic resistor circuit 23 is connected with the inverting input (denoted by the symbol “−”) of the differential amplifier 21, and also connected with one end of the resistor 32. The output terminal of the differential amplifier 21 is connected with a signal output terminal 13, and also connected with the other end of the resistor 32. One of the control terminals of the MOS switch 41 is directly connected with the analog/digital select terminal 12, and the other is connected with the analog/digital select terminal 12 through the inverter circuit 22.
The inverter circuit 22 is used to drive the PMOS transistor of the MOS switch 41, and the MOS switch 41 is turned on and off in response to the voltage level on the analog/digital select terminal 12. Specifically, the MOS switch 41 is turned on when the analog/digital select terminal 12 is pulled up to the “H” level. When the analog/digital select terminal 12 is pulled down to the “L” level, on the other hand, the while the MOS switch 41 is turned off.
The control terminal of the MOS switch 42 is connected with the analog/digital select terminal 12, and the MOS switch 42 is turned on and off in response to the voltage level on the analog/digital select terminal 12. Specifically, the MOS switch 42 is turned off when the analog/digital select terminal 12 is pulled up to the “H” level. When the analog/digital select terminal 12 is pulled down to the “L” level, on the other hand, the while the MOS switch 41 is turned on. It should be noted that the MOS switches 41 and 42 performs complementary operations; when one of the MOS switches 41 and 42 is turned on, the other is turned off.
In this configuration, the resistor 32 is electrically connected between the output terminal 13 and the non-inverting input of the differential amplifier 21 to function as a feedback resistor, when the analog-digital select terminal 12 is pulled up to the “H” level. This allows the differential amplifier 21 to operate as a positive-phase amplifier that provides in-phase amplification for the input signal fed to the signal input terminal 11. When the analog/digital select terminal 12 is pulled down to the “L” level, on the other hand, the negative feedback loop is cut off, and the differential amplifier 21 operates as a comparator that compares the voltage levels on the inverting and non-inverting inputs thereof. In this case, the resistors 33 and 31 functions as a reference voltage level generator which generates a reference voltage level through voltage division of the power supply level vdd.
The synthetic resistor circuit 23 is configured so that the resistance thereof is controllable in response to voltage levels on control terminals 14 to 16. Specifically, the resistors 31, 34 and 35 are connected in parallel, and the MOS switches 44, 45 and 46 are connected in series between the ground line and the resistors 31, 34 and 35 and, respectively. The control terminals of the MOS switches 44, 45 and 46 are connected with the control terminals 14, 15 and 16, respectively. The MOS switches 44, 45 and 46 are turned on and off in response to the voltage levels on the control terminals 14, 15 and 16, respectively. This allows controlling the resultant resistance of the synthetic resistor circuit 23 by the voltage levels on the control terminals 14, 15 and 16.
For the case that the on-resistances of the MOS switches 44, 45 and 46 are sufficiently smaller than the resistance R1, R4 and R5 of the resistors 31, 34 and 35 respectively (this is usually the case in practice), the resultant resistance Z of the synthetic resistor circuit 23 is as follows:
Z=R1×R4×R5/(R1×R4+R4×R5+R5×R1), (3)
when all of the control terminals 14, 15 and 16 are pulled up to the “H” level to turn on the MOS switches 44, 45 and 46, for example.
When the control terminals 14 and 15 are pulled up to the “H” level with the control terminal 16 pulled down to the “L” level, on the other hand, the resultant resistance Z of the synthetic resistor circuit 23 is as follows:
Z=R1×R4/(R1+R4). (4)
The signal input terminal 11 receives an analog input signal or a digital input signal, and the signal output terminal 13 outputs an analog output signal or a digital output signal, accordingly. For achieving analog amplification of the signal fed to the signal input terminal 11, the analog-digital select terminal 12 is pulled up to the “H” level. For digitizing the signal fed to the signal input terminal 11, on the other hand, the analog-digital select terminal 12 is pulled down to the “L” level.
The input interface circuit according to the second embodiment operates as follows: A description is first given of the analog amplification of the input signal fed to the signal input terminal 11. In this case, the analog-digital select terminal 12 is pulled up to the “H” level, and the MOS switch 42 is turned off, while the MOS switch 41 is turned on. As a result, the output of the differential amplifier 21 is connected with the inverting input of the differential amplifier 21 through the resistor 32, and also grounded through the synthetic resistor circuit 23. This allows the input interface circuit to operate as a positive-phase amplifier.
For the case that the on-resistance of the MOS switch 41 is sufficiently smaller than the resistance R2 of the resistor 32 (this is usually the case in practice), the gain Ga of the positive-phase amplifier is as follow:
Ga=1+R2/Z. (5)
It should be noted that the resultant resistance Z of the parallel resistance circuit 23 is dependent on the voltage levels on the control terminals 14 to 16. Therefore, the gain Ga can be adjusted by t the voltage levels on the control terminals 14 to 16 as desired.
For the signal digitalization of the input signal fed to the signal input terminal 11, on the other hand, the analog-digital select terminal 12 is pulled up to the “L” level. This results in that the MOS switch 42 is turned on, while the MOS switch 41 is turned off. In this case, the differential amplifier 21 operates as a comparator. The reference voltage level Vth fed to the non inverting input of differential amplifier 21, which is identical to the threshold level of the signal digitalization, is as follow:
Vth=Vdd×Z/(Z+R3). (6)
Since the resultant resistance Z of the parallel resistance circuit 23 is dependent on the voltage levels on the control terminals 14 to 16, the threshold level of the signal digitalization of the digital input signal can be adjusted by the voltage levels on the control terminals 14 to 16.
It should be noted that the configuration of the synthetic resistor circuit 23, in which the MOS switches 44, 45 and 46 are connected in series to the resistors 31, 34 and 35 in the configuration of
As thus described, the synthetic resistor circuit 23, which has a variable resistance, allows adjusting the gain of the analog amplification of the analog input signal and the threshold level of the signal digitization of the digital input signal.
The input interface circuit according to the third embodiment is provided with a differential amplifier 21, an inverter circuit 22, resistors 32 and 33, MOS switches 41 and 42, a synthetic resistor circuit 23, an A/D converter 26 and a resistance controller 26. The synthetic resistor circuit 23 includes resistors 31, 34 and 35 and MOS switches 44 to 46. The configuration of the input interface circuit according to the third embodiment is almost similar to that of the input interface circuit according to the third embodiment, except for that the input interface circuit according to the third embodiment additionally include an A/D converter 25 and a resistance controller 26. Therefore, a description is only given of the A/D converter 25 and the resistance controller 26 in the following.
The input of the A/D converter 25 is connected with the output of the differential amplifier 21, and the outputs of the A/D converter 25 are connected with A/D converted signal outputs 18 and the inputs of the resistance controllers 26. The control terminal of the A/D converter 25 is connected with the analog/digital selection terminal 12. The outputs of the resistance controllers 26 are connected with the control terminals of the MOS switches 44 to 46, respectively. The resistance controller 26 is connected with the analog/digital selection terminal 12, and also connected with a resistor control signal input 19. The resistance controller 26 controls the voltage levels of the control terminals of the MOS switches 44 to 46 in response to the voltage levels on the analog/digital selection terminal 12 and the resistor control signal input 19.
The input interface circuit according to the third embodiment is configured to provide digital signals to the internal circuit of the semiconductor IC. When a digital input signal is fed to the signal input terminal 11, a corresponding digital output signal, which is generated through signal digitization by the differential amplifier 21, is output from a digital signal output terminal 17. When an analog input signal is fed to the signal input terminal 11, on the other hand, a set of digital output signals generated through A/D conversion by the A/D converter 25 are output from the A/D converted signal outputs 18. The digital output signals output from the A/D converted signal outputs 18 represent a digital value corresponding to the signal level of the analog input signal fed to the signal input terminal 11
The A/D converter 25 is activated when the analog/digital selection terminal 12 is pulled up to the “H” level. In other words, the A/D converter 25 provides A/D conversion for the output signal of the differential amplifier 21, and feeds the resultant digital signals to the A/D converted signal outputs 18, when the input interface circuit operates as an analog circuit. When the analog/digital selection terminal 12 is pulled down to the “L” level, on the other hand, the A/D converter 25 is deactivated and the outputs of the A/D converter 25 are disenabled.
The resistor controller 26 generates control signals for controlling the MOS switches 44 to 46 in response to the digital output signals received from the A/D converter 25 (which are also fed to the A/D converted signal outputs 18). The operation of the resistor controller 26 is controlled in response to the voltage level on the analog/digital select terminal 12.
When the analog/digital select terminal 12 is pulled up to the “H” level, the resistor controller 26 feeds the control signals to the MOS switches 44 to 46 in response to the digital output signals received from the A/D converter 25. Specifically, the resistor controller 26 latches the digital output signals received from the A/D converter 25 in response to the pull-up of the resistor control signal input 19, and generates the control signals fed to the MOS switches 44 to 46 in response to the digital output signals latched. When the signal level of the output of the differential amplifier 21 is too small and only a reduced number of the digital output signals received from the A/D converter 25 are effectively used to indicate the signal level of the output of the differential amplifier 21, the resistor controller 26 controls the MOS switches 44 to 46 so as to increase the gain Ga of the analog amplification, which is indicated by the formula (5); the gain Ga is increased by decreasing the resultant resistance Z of the synthetic resistor circuit 33. When the signal level of the output of the differential amplifier 21 is too large, causing overflow of the digital output signals generated by the A/D converter 25, the resistor controller 26 controls the MOS switches 44 to 46 to decrease the gain Ga, and thereby avoids the saturation of the A/D converter 25. Such operation achieves automatic gain control and effectively increases the dynamic range of the analog input signal.
In an alternative embodiment, the resistor controller 26 may control the MOS switches 44 to 46 in response to the time-average of the digital value output from the A/D converter 25. This allows the input interface circuit to operate as an AGC (automatic gain control) circuit, achieving normalization of the amplitude of the analog input signal. Instead, the resistor controller 26 may control MOS switches 44 to 46 in response to the change in the digital value received from the A/D converter 25. This allows gain control in response to the changing speed of the digital value output from the A/D converter 25.
When the analog/digital select terminal 12 is pulled down to the “L” level to achieve signal digitization, the A/D converter 25 is deactivated; the output terminals of the A/D converter 25 are set to high-impedance. In this case, the A/D converted signal outputs 18 are used as input terminals used to feed control signals to the resistance controller 26 for controlling the resultant resistance Z of the synthetic resistor circuit 23. The control signals are fed to the A/D converted signal outputs 18 from an internal circuit (such as a CPU and a threshold setting register). The resistance controller 26 controls the MOS switches 44 to 46 to adjust the threshold level of the signal digitization in response to the control signals fed to the A/D converted signal outputs 18.
The control pattern of the MOS switches 44 to 46 for adjustment of the threshold level Vth may be different from that for the gain control of the analog amplification.
In one embodiment, the resistor controller 26 may include a storage device, such as a semiconductor memory, storing a database table describing the association of the pattern of the control signals fed to the resistor controller 26 with the pattern of the control signals 55 to 57 fed to the MOS switches 44 to 46. The database table is used for converting the control signals received from the A/D converted signal outputs 18 into the resistor controller 26 in to the control signals 55 to 57. In an alternative embodiment, the resistor controller 26 may include a logic circuit or firmware (or a software program) for converting the signals received from the output signals of A/D converter 25 or the A/D converted signal outputs 18 into the resistor controller 26. In another alternative embodiment, the MOS switches 44 to 46 may be controlled in response to only the voltage levels on the analog/digital select terminal 12 and the resistance control signal input 19, in the adjustment of the threshold level Vth.
As thus described, the input interface circuit according to the third embodiment is provided with the A/D converter 25 and the resistor controller 26, and thereby achieves sophisticated control including automatic gain control in addition to the external adjustment of the threshold level and the gain.
Specifically, the input interface circuit according to the fourth embodiment is provided with a differential amplifier 21, inverter circuits 22, 27 and 28, resistors 32 and 33, capacitors 37 and 38, MOS switches 41, 42, 47 and 48, a synthetic resistor circuit 23 and a MOS switch controller 51. The synthetic resistor circuit 23 includes resistors 31, 34 and 35, and MOS switches 44 to 46.
A signal input terminal 11 is connected with the non-inverting input (denoted by the symbol “+”) of the differential amplifier 21. The MOS switch 42, the resistor 33, and the synthetic resistor circuit 23 is serially connected between a power supply line VDD and a ground line GND. The control terminal (or the gate) of the MOS switch 42 is connected with the MOS switch controller 51. The connecting node of the resistor 33 and the synthetic resistor circuit 23 is connected with the inverting input (denoted by the symbol “−”) of the differential amplifier 21, and also connected with the resistor 32 and the capacitors 37 and 38. The output terminal of the differential amplifier 21 is connected with a signal output terminal 13, and also connected with the other end of the resistor 32. The connecting node of the MOS switch 41 and the resistor 32 is connected with the capacitors 37 and 38 through the MOS switches 47 and 48, respectively.
One of the control terminals of the MOS switch 41 is directly connected with the MOS switch controller 51, and the other is connected with the MOS switch controller 51 through the inverter circuit 22. The control terminal of the MOS switch 42 is also connected with the MOS switch controller 51 commonly with the other of the control terminals of the MOS switch 41. Therefore, the MOS switches 41 and 42 are turned on and off in response to an output signal 51 generated by the MOS switch controller 51. Specifically, the MOS switch 42 is turned off and the MOS switch 41 is turned on, when the control signal 52 is pulled up to the “H” level. When the control signal 52 is pulled down to the “L” level, on the other hand, the MOS switch 42 is turned on and the MOS switch 41 is turned off.
One of the control terminals of the MOS switch 47 is directly connected with the MOS switch controller 51, and the other is connected with the MOS switch controller 51 through the inverter circuit 27. The MOS switch 47 is turned on and off in response to a control signal 53 generated by the MOS switch controller 51. When the control signal 53 is pulled up to the “H” level, the MOS switch 47 is turned on to allow the capacitor 37, which has a capacitance of C2, to be electrically connected in parallel to the resistor 32.
Correspondingly, one of the control terminals of the MOS switch 48 is directly connected with the MOS switch controller 51, and the other is connected with the MOS switch controller 51 through the inverter circuit 28. The MOS switch 48 is turned on and off in response to another control signal 54 generated by the MOS switch controller 51. When the control signal 54 is pulled up to the “H” level, the MOS switch 48 is turned on to allow the capacitor 38, which has a capacitance of C1, to be electrically connected in parallel to the resistor 32.
The synthetic resistor circuit 23 is configured to have a variable resistance controlled by the MOS switch controller 51 Specifically, the resistors 31, 34 and 35 are connected in parallel, and the MOS switches 44, 45 and 46 are connected in series between the ground line and the resistors 31, 34 and 35 and, respectively. The control terminals of the MOS switches 44, 45 and 46 are connected with the MOS switch controller 51. The MOS switches 44, 45 and 46 are turned on and off in response to control signals 55, 56 and 57 received from the switch controller 51, respectively. In the following description, it is assumed that the resistances of the resistors 31, 34 and 35 are R1, R4 and R5, respectively, the on-resistances of the MOS switches 44 to 46 are sufficiently small compared with the resistances R1, R4, R5 of the resistors 31, 34 and 35. The resultant resistance Z of the synthetic resistor circuit 23 is obtained as the parallel connection resistance of selected ones of the resistors 31, 34 and 35, as described in the second embodiment.
The MOS switch controller 51 is connected with the analog/digital select terminal 12 to receive an input mode switch signal 58. The outputs of the MOS switch controller 51 are connected with the MOS switches 41, 42, 44, 45, 46, 47, 48. The MOS switch controller 51 feeds the control signals 52 to 57 to the associated MOS switches in response to the input mode switch signal 58. In this embodiment, the input mode switch signal 58 is fed through a single signal line from the analog/digital select terminal 12 as an encoded pulse signal. The MOS switch controller 51 controls the signal levels of the control signals 52 to 57 in response to the number of pulses and pulse widths of the respective pulses within the input mode switch signal 58.
The input interface circuit according to the fourth embodiment operates as follows: For providing signal digitization for the input signal fed to the signal input terminal 11, the MOS switch controller 51 pulls down the control signal 52 to the “L” level. This allows the MOS switch 42 to be turned on, and the MOS switch 41 to be turned off. The operation of the input interface circuit in implementing the signal digitization is identical to that in the second embodiment, except for that the MOS switches 44 to 46 are controlled by the MOS switch controller 51.
For providing analog amplification and filtering, on the other hand, the MOS switch controller 51 pulls up the control signal 52 to the “H” level. This allows the MOS switch 42 to be turned off, and the MOS switch 41 to be turned on. When both of the control signals 53 and 54 are pulled down to the “L” level by the MOS switch controller 51, the MOS switched 47 and 48 are turned off, allowing the input interface circuit to operate as a positive-phase amplifier, as is the case of the second embodiment. The gain Ga of the positive-phase amplifier is as follows:
Ga=1+R2/Z, (7)
where Z is the resultant resistance of the synthetic resistor circuit 23.
When the control signal 54 is pulled up to the “H” level, the MOS switch 48 is turned on, incorporating the capacitor 38 into the feedback loop of the differential amplifier 21 in parallel to the resistor 32. This allows the input interface circuit according to the fourth embodiment to operate as a low pass filter. The cut-off frequency f1 is as follows:
f1=1/(2π×C1×R2), (8)
where R2 is the resistance of the resistor 32, and C1 is the capacitance of the capacitor 38.
When the control signal 53 is additionally pulled up to the “H” level, the MOS switch 47 is turned on, additionally incorporating the capacitor 37 into the feedback loop of the differential amplifier 21 in parallel to the resistor 32. In this case, the cut-off frequency f2 is as follows:
f2=1/(2π×(C1+C2)×R2), (8)
The low pass filtering described above is preferably used as pre-filtering for an A/D converter.
Although the MOS switches 47 and 48 are each connected in series to the MOS switch 41 in this embodiment, the configuration of the feedback loop from the output of the differential amplifier 21 to the input thereof may be modified. For example, the MOS switches 41, 47 and 48 may be connected in parallel. In this case, the control logic of the MOS switch controller 51 is modified accordingly. Additionally, the feedback loop may additionally include resistors connected in series to the capacitors 37 and 38, respectively, to adjust not only the cut-off frequency but also the gain. The feedback loop may be modified so that the input interface circuit provides high-pass filtering or band-pass filtering.
In summary, the input interface circuits described in the above embodiments allows using the signal input terminal for both of digital and analog signal inputs, and thereby reduces the number of interface terminals. Additionally, the input interface circuits described in the above embodiments allows adjusting the gain of the analog signal input and the threshold level of the signal digitization for the digital signal input, independently.
It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope of the invention.
For example, although the synthetic resistor circuit 23 is described as including resistors 31, 34 and 35 and MOS switches 44, 45 and 46 in the above-described embodiments, the synthetic resistor circuit 23 may additionally include a resistor(s) and MOS switch(es). Each MOS switch may be selected from a PMOS transistor, an NMOS transistor, and a transfer gate depending on the use conditions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-188106 | Jul 2006 | JP | national |
