Claims
- 1. A CMOS circuit for driving a signal on an input terminal onto an output terminal, said circuit comprising
- a first pair of complementary transistors, a first transistor of said pair having a gate electrode, a source electrode connected to a first voltage supply at a nominal first voltage, a drain electrode connected to said output terminal, a second transistor of said pair having a gate electrode, a source electrode connected to a second voltage supply at a nominal second voltage, a drain electrode connected to said output terminal;
- means connected to said input terminal and to said gate electrodes of said transistors of said first pair for alternately turning one of said transistors of said pair on at a time responsive to a signal on said input terminal, said means connected between a third and fourth voltage supply, said third voltage supply at said nominal first voltage but not electrically connected to said first voltage supply, said fourth voltage supply at said nominal second voltage but not electrically connected to said second voltage supply; and
- a first transistor having a source electrode connected to said gate electrode of said second transistor of said first pair, a drain electrode connected to said fourth voltage supply and a gate electrode connected to said source electrode of said second transistor of said first pair;
- whereby said output terminal is substantially immune from voltage spikes in said second voltage supply.
- 2. The CMOS circuit as in claim 1 further comprising a second transistor having a source electrode connected to said third voltage supply, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode connected to said source electrode of said first transistor of said first pair whereby said circuit is substantially immunized from voltage spikes in said first voltage supply.
- 3. The CMOS circuit as in claim 1 wherein said alternately turning means comprises
- a second pair of complementary transistors, a first transistor of said pair having a source electrode connected to said third voltage supply, a gate electrode to said input terminal and a drain electrode connected to a gate electrode of said first transistor of said first pair, a second transistor of said pair having a source electrode connected to said fourth voltage supply, a gate electrode connected to said input terminal and a drain electrode connected to a gate electrode of said second transistor of said first pair;
- a third pair of complementary transistors, a first transistor of said pair having a source electrode connected to said third voltage supply, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode coupled to a first control terminal, a second transistor of said pair having a source electrode connected to said fourth voltage supply, a drain electrode connected to said gate electrode of said second transistors of said first pair and a gate electrode coupled to said first control terminal; and
- at least one transistor having a first source/drain electrode connected to said gate electrode of said first transistor of said first pair and a second source/drain electrode connected to said gate electrode of said second transistor of said first pair, and a gate electrode coupled to said first control terminal, said gate electrodes of said transistors of said third pair and said gate electrode of said one transistor coupled to said first control terminal so that said transistors of said third pair are on when said one transistor is off to disable said CMOS circuit, and off when said third transistor is on to enable said CMOS circuit.
- 4. The CMOS circuit as in claim 3 further comprising a second transistor having a source electrode connected to said third voltage supply, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode connected to said source electrode of said first transistor of said first pair whereby said circuit is substantially immunized from voltage spike in said first voltage supply.
- 5. The CMOS circuit as in claim 3 further comprising
- a fourth pair of transistors, said transistors having the same conductivity and connected in series between said gate electrode of said first transistor of said first pair and said gate electrode of said second transistor of said first pair, a first transistor of said fourth pair having a gate electrode coupled to said first control terminal so as to operate as said one transistor, and a second transistor of said fourth pair having a gate electrode connected to said output terminal;
- whereby said second transistor of said fourth pair substantially speeds switching of said output terminal from a high voltage state to a low voltage state.
- 6. The CMOS circuit as in claim 3 further comprising
- a fourth pair of transistors, said transistors having the same conductivity and connected in series between said gate electrode of said first transistor of said first pair and said gate electrode of said second transistor of said first pair, a first transistor of said fourth pair having a gate electrode coupled to said first control terminal so as to operate as said one transistor, and a second transistor of said fourth pair having a gate electrode connected to a second control terminal;
- whereby said second transistor of said fourth pair substantially speeds switching of said output terminal from a high voltage state to a low voltage state responsive to a signal on said second control terminal.
- 7. A CMOS circuit for driving a signal on an input terminal onto an output terminal, said circuit comprising
- a first pair of complementary transistors, a first transistor of said pair having a gate electrode, a source electrode at a first nominal voltage and a drain electrode connected to said output terminal, and a second transistor of said pair having a gate electrode, a source electrode at a second nominal voltage and a drain electrode connected to said output terminal;
- a second pair of complementary transistors, a first transistor of said pair having a source electrode connected to a voltage supply at said first nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to said gate electrode of said first transistor of said first pair, a second transistor of said pair having a source electrode connected to a voltage supply at said second nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to a gate electrode of said second transistor of said first pair; and
- a first transistor having source and drain electrodes coupled between said gate electrodes of said first and second transistors of said first pair, and a gate electrode connected to said output terminal;
- whereby said first transistor substantially speeds switching of said output terminal from a high voltage state to a low voltage state.
- 8. The CMOS circuit as in claim 7 further comprising a second transistor connected in series with said first transistor between said gate electrodes of said first and second transistors of first pair, said second transistor having a gate electrode connected to a first control terminal whereby operation of said first transistor is enabled by a signal on said first control terminal.
- 9. The CMOS circuit as in claim 8 further comprising
- a third pair of complementary transistors, a first transistor of said pair having a source electrode connected to said voltage supply at said first nominal voltage, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode coupled to said first control terminal, a second transistor of said pair having a source electrode connected to said voltage supply at said second nominal voltage, a drain electrode connected to said gate electrode of said second transistor of said first pair and a gate electrode coupled to said first control terminal; and
- a third transistor having a first source/drain electrode connected to said gate electrode of said first transistor of said first pair and a second source/drain electrode connected to said gate electrode of said second transistor of said first pair, and a gate electrode coupled to said first control terminal, said gate electrodes of said transistors of said third pair and said gate electrode of said third transistor coupled to said first control terminal so that said transistors of said third pair are on when said third transistor is off to disable said CMOS circuit, and off when said third transistor is on to enable said CMOS circuit.
- 10. The CMOS circuit as in claim 7 further comprising a first immunizing transistor having a source electrode connected to said voltage supply at said second nominal voltage, a drain electrode connected to said gate electrode of said second transistor of said first pair and a gate electrode connected to said source electrode of said second transistor of said first pair, and wherein said source electrode of said second transistor of said first pair is connected to a second voltage supply at said second nominal voltage, said second voltage supply electrically disconnected from said voltage supply at said second nominal voltage;
- whereby said output terminal is substantially immune from voltage spikes in said second voltage supply at said second nominal voltage.
- 11. The CMOS circuit as in claim 10 further comprising a second immunizing transistor having a source electrode connected to said voltage supply at said first nominal voltage, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode connected to said source electrode of said first transistor of said first pair and wherein said source electrode of said first transistor of said first pair is connected to a second voltage supply at said first nominal voltage, said second voltage supply electrically disconnected from said supply voltage at said first nominal voltage;
- whereby said output terminal is substantially immunized from voltage spikes in said second voltage supply at said first nominal voltage.
- 12. The CMOS circuit as in claim 7 further comprising a second transistor having source and drain electrodes coupled between said gate electrodes of said first and second transistors of said first pair in parallel with said first transistor, and a gate electrode connected to a control terminal whereby said second transistor substantially speeds switching of said output terminal from a high voltage state to a low voltage state responsive to a signal on said control terminal.
- 13. A CMOS circuit for driving a signal on an input terminal onto an output terminal, said circuit comprising
- a first pair of complementary transistors, a first transistor of said pair having a gate electrode, a source electrode at a first nominal supply voltage and a drain electrode connected to said output terminal, and a second transistor of said pair having a gate electrode, a source electrode at a second nominal supply voltage and a drain electrode connected to said terminal;
- a second pair of complementary transistors, a first transistor of said pair having a source electrode connected to a voltage supply at said first nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to said gate electrode of said first transistor of said first pair, a second transistor of said pair having a source electrode connected to a voltage supply at said second nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to a gate electrode of said second transistor of said first pair;
- a first transistor having source and drain electrodes coupled between said gate electrodes of said first and second transistors of said first pair, and a gate electrode connected to a first control terminal, whereby said first transistor substantially speeds switching of said output terminal from a high voltage state to a low voltage state responsive to a signal on said first control terminal; and
- a second transistor connected in series with said first transistor between said gate electrodes of said first and second transistors of first pair, said second transistor having a gate electrode connected to a second control terminal whereby operation of said first transistor is enabled by a signal on said second control terminal.
- 14. The CMOS circuit as in claim 13 further comprising
- a third pair of complementary transistors, a first transistor of said pair having a source electrode connected to said voltage supply at said first nominal voltage, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode coupled to said second control terminal, a second transistor of said pair having a source electrode connected to said voltage supply at said second nominal voltage, a drain electrode connected to said gate electrode of said second transistor of said first pair and a gate electrode coupled to said second control terminal; and
- a third transistor having a first source/drain electrode connected to said gate electrode of said first transistor of said first pair and a second source/drain electrode connected to said gate electrode of said second transistor of said first pair, and a gate electrode coupled to said second control terminal, said gate electrodes of said transistors of said third pair and said gate electrode of said third transistor coupled to said second control terminal so that said transistors of said third pair are on when said third transistor is off to disable said CMOS circuit, and off when said third transistor is on to enable said CMOS circuit.
- 15. A CMOS circuit for driving a signal on an input terminal onto an output terminal, said circuit comprising
- a first pair of complementary transistors, a first transistor of said pair having a gate electrode, a source electrode at a first nominal supply voltage and a drain electrode connected to said output terminal, and a second transistor of said pair having a gate electrode, a source electrode at a second nominal supply voltage and a drain electrode connected to said terminal;
- a second pair of complementary transistors, a first transistor of said pair having a source electrode connected to a voltage supply at said first nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to said gate electrode of said first transistor of said first pair, a second transistor of said pair having a source electrode connected to a voltage supply at said second nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to a gate electrode of said second transistor of said first pair;
- a first transistor having source and drain electrodes coupled between said gate electrodes of said first and second transistors of said first pair, and a gate electrode connected to a first control terminal, whereby said first transistor substantially speeds switching of said output terminal from a high voltage state to a low voltage state responsive to a signal on said first control terminal; and
- a first immunizing transistor having a source electrode connected to said gate electrode of said second transistor of said first pair, a drain electrode connected to said voltage supply at said second nominal voltage and a gate electrode connected to said source electrode of said second transistor of said first pair, and wherein said source electrode of said second transistor of said first pair is connected to a second voltage supply at said second nominal supply voltage, said second voltage supply electrically disconnected from said voltage supply at said second nominal supply voltage;
- whereby said output terminal is substantially immune from voltage spikes in said second voltage supply at said second nominal supply voltage.
- 16. The CMOS circuit as in claim 15 further comprising a second immunizing transistor having a source electrode connected to said voltage supply at said first nominal supply voltage, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode connected to said source electrode of said first transistor of said first pair and wherein said source electrode of said first transistor of said first pair is connected to a second voltage supply at said first nominal supply voltage, said second voltage supply electrically disconnected from said supply voltage at said first nominal supply voltage;
- whereby said output terminal is substantially immunized from voltage spikes in said second voltage supply at said first nominal supply voltage.
- 17. A CMOS circuit for driving a signal on an input terminal onto an output terminal, said circuit comprising
- a first pair of complementary transistors, a first transistor of said pair having a gate electrode, a source electrode at a first nominal supply voltage and a drain electrode connected to said output terminal, and a second transistor of said pair having a gate electrode, a source electrode at a second nominal supply voltage and a drain electrode connected to said terminal;
- a second pair of complementary transistors, a first transistor of said pair having a source electrode connected to voltage supply at said first nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to said gate electrode of said first transistor of said first pair, a second transistor of said pair having a source electrode connected to a voltage supply at said second nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to a gate electrode of said second transistor of said first pair; and
- a first transistor having source and drain electrodes coupled between said gate electrodes of said first and second transistors of said first pair, and a gate electrode connected to a first control terminal, whereby said first transistor substantially speeds switching of said output terminal from a high voltage state to a low voltage state responsive to a signal on said first control terminal; and
- a second transistor having source and drain electrodes coupled between said gate electrodes of said first and second transistors of said first pair in parallel with said first transistor, and a gate electrode connected to said output terminal;
- whereby said second transistor substantially speeds switching of said output terminal from a high voltage state to a low voltage state.
- 18. A CMOS circuit for driving a signal on an input terminal onto an output terminal, said circuit comprising
- a plurality of units, each unit connected in parallel to said input terminal and to said output terminal, each unit having
- a control terminal;
- means connected to said control terminal for enabling said unit responsive to a signal on said control terminal; and
- means for driving a signal on said input terminal onto said output terminal with a predetermined drive current;
- whereby said circuit drives signals onto said output terminal with selective drive currents responsive to signals on said unit control terminals.
- 19. The CMOS circuit as in claim 18 wherein each unit comprises a first pair of complementary transistors, said transistors of said first pair connected in series between first and second nominal supply voltages, said transistors having gate electrodes of said transistors coupled to said input terminal and a commonly connected source/drain electrode connected to said output terminal, each transistors sized to provide a predetermined drive current through said output terminal when said transistor is conducting.
- 20. The CMOS circuit as in claim wherein said enabling means comprises
- a second pair of complementary transistors, a first transistor of said pair having a source electrode connected to a voltage supply at said first nominal voltage, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode coupled to said control terminal, a second transistor of said pair having a source electrode connected to a voltage supply at said second nominal voltage, a drain electrode connected to said gate electrode of said second transistor of said first pair and a gate electrode coupled to said control terminal; and
- a first transistor having a first source/drain electrode connected to said gate electrode of said first transistor of said first pair and a second source/drain electrode connected to said gate electrode of said second transistor of said first pair, and a gate electrode coupled to said control terminal, said gate electrodes of said transistors of said second pair and said gate electrode of said first transistor coupled to said control terminal so that said transistors of said second pair are on when said first transistor is off to disable said CMOS circuit, and off when said first transistor is on to enable said CMOS circuit.
- 21. The CMOS circuit as in claim 20 further comprising a first immunizing transistor having a source electrode connected to said gate electrode of said second transistor of said first pair, a drain electrode connected to said voltage supply at said second nominal voltage and a gate electrode connected to said source electrode of said second transistor of said first pair, and wherein said source electrode of said second transistor of said first pair is connected to a second voltage supply at said second nominal supply voltage, said second voltage supply electrically disconnected from said voltage supply at said second nominal supply voltage;
- whereby said output terminal is substantially immune from voltage spikes in said second voltage supply at said second nominal supply voltage.
- 22. The CMOS circuit as in claim 21 further comprising a second immunizing transistor having a source electrode connected to said voltage supply at said first nominal supply voltage, a drain electrode connected to said gate electrode of said first transistor of said first pair and a gate electrode connected to said source electrode of said first transistor of said first pair and wherein said source electrode of said first transistor of said first pair is connected to a second voltage supply at said first nominal supply voltage, said second voltage supply electrically disconnected from said supply voltage at said first nominal supply voltage;
- whereby said output terminal is substantially immunized from voltage spikes in said second voltage supply at said first nominal supply voltage.
- 23. The CMOS circuit as in claim 20 further comprising
- a third pair of complementary transistors, a first transistor of said pair having a source electrode connected to said voltage supply at said first nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to said gate electrode of said first transistor of said first pair, a second transistor of said pair having a source electrode connected to said voltage supply at said second nominal voltage, a gate electrode connected to said input terminal and a drain electrode connected to a gate electrode of said second transistor of said first pair; and
- a second transistor having source and drain electrodes coupled between said gate electrodes of said first and second transistors of said first pair, and a gate electrode connected to a second control terminal;
- whereby said second transistor substantially speeds switching of said output terminal from a high voltage state to a low voltage state responsive to a signal on said second control terminal.
- 24. The CMOS circuit as in claim 23 further comprising a third transistor connected in series with said first transistor between said gate electrodes of said first and second transistors of first pair, said third transistor having a gate electrode connected to said control terminal whereby operation of said first transistor is enabled by a signal on said control terminal.
- 25. The CMOS circuit as in claim 23 further comprising a fourth transistor connected in series with said second transistor between said gate electrodes of said first and second transistors of first pair, said fourth transistor having a gate electrode connected to said output terminal whereby said fourth transistor substantially speeds switching of said output terminal from a high voltage state to a low voltage state.
Parent Case Info
This is a division of application Ser. No. 08/078,692 filed Jun. 17, 1993, which is a division of application Ser. No. 07/718,677 filed Jun. 21, 1991, which issued as U.S. Pat. No. 5,221,865.
US Referenced Citations (4)
Divisions (2)
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Number |
Date |
Country |
Parent |
78692 |
Jun 1993 |
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Parent |
718677 |
Jun 1991 |
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