BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
FIG. 1 is a circuit diagram showing an input protection circuit of a first embodiment of the present invention;
FIG. 2 is a circuit diagram showing an input protection circuit of a second embodiment of the present invention;
FIG. 3 is a circuit diagram showing an input protection circuit of a third embodiment of the present invention;
FIG. 4 is a circuit diagram showing an input protection circuit of a fourth embodiment of the present invention;
FIG. 5 is a circuit diagram showing an application of an input protection circuit provided for plural input terminals;
FIG. 6 is a circuit diagram showing an application of the input protection circuit of the third embodiment;
FIG. 7 is a circuit diagram showing an input protection circuit of a fifth embodiment of the present invention;
FIG. 8 is a circuit diagram showing an input protection circuit of a sixth embodiment of the present invention;
FIG. 9 is a circuit diagram showing an input protection circuit of a seventh embodiment of the present invention;
FIG. 10 is a circuit diagram showing an input protection circuit of an eighth embodiment of the present invention;
FIG. 11 is a circuit diagram showing an input protection circuit of a ninth embodiment of the present invention;
FIG. 12 is a circuit diagram showing an internal construction of a comparator in a tenth embodiment of the present invention; and
FIG. 13 is a circuit diagram showing a conventional input protection circuit;
FIG. 14 is a circuit diagram showing an input protection circuit of an eleventh embodiment of the present invention;
FIG. 15 is a sectional view showing a diode in a semiconductor integrated circuit;
FIG. 16 is a schematic view showing arrangement of circuit elements when an input protection circuit is integrated into an IC, in a twelfth embodiment of the present invention;
FIG. 17 is a schematic view showing only a corresponding portion of FIG. 14 in the arrangement of FIG. 16;
FIG. 18 is a schematic view showing conventional arrangement of circuit elements of an input protection circuit;
FIG. 19 is a schematic view showing only a corresponding portion of the input protection circuit in the arrangement of FIG. 18;
FIG. 20 is a circuit diagram showing an input protection circuit according to a thirteenth embodiment of the present invention;
FIG. 21 is a circuit diagram showing an input protection circuit according to a fourteenth embodiment of the present invention;
FIG. 22 is a circuit diagram showing an input protection circuit according to a fifteenth embodiment of the present invention;
FIG. 23 is a circuit diagram showing a further conventional input protection circuit;
FIG. 24 is a circuit diagram showing a modification of the conventional input protection circuit shown in FIG. 23 to meet a surge voltage of negative polarity; and
FIG. 25 is a sectional view showing a diode in a semiconductor integrated circuit.