Claims
- 1. A bias circuit comprising:
- at least a pair of bipolar transistors, the bases of said pair of bipolar transistors being connected to each other;
- a first junction field effect transistor, the source of which is connected to the emitter of one of said pair of bipolar transistors; and
- a second junction field effect transistor, the source of which is connected to the emitter of the other of said pair of bipolar transistors;
- wherein the gate electrodes of said first and second junction field effect transistors are connected to a low impedance node and the drain electrodes of said first and second junction field effect transistors are connected to a common bus.
- 2. A bias circuit comprising:
- load means comprising a pair of bipolar transistors, each having an emitter, a base, and a collector, the bases connected to each other; and
- a pair of junction field effect transistors, each having a source, a gate electrode, and a drain, one of the sources connected to one of the emitters, the other of the sources connected to the other of the emitters, the gate electrodes connected to a low impedance node, and the drains connected to a common bus.
Parent Case Info
This is a division of application Ser. No. 807,602, filed June 17, 1977, now U.S. Pat. No. 4,194,136, issued Mar. 18, 1980.
US Referenced Citations (4)
Non-Patent Literature Citations (2)
Entry |
RCA Tech Notes, Hybrid B. Por. and Mos. Flip-Flop Circuits by S. Katz, RCA TN No. 683, 6/66. |
IBM Tech. Dsclre. Bulletin, Monolithic Memory Cell with Junction FET Loads, S. Wiedmann, vol. 13, No. 2, 7/70. |
Divisions (1)
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Number |
Date |
Country |
Parent |
807602 |
Jun 1977 |
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