A general architecture that implements the various feature of the invention will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the invention and not to limit the scope of the invention.
Various embodiments according to the invention will be described hereinafter with reference to the accompanying drawings. In general, according to one embodiment of the invention, an input/output processing device includes an input controller configured to sequentially input stream data including a plurality of successive packets each having a fixed length, the input controller inputting the stream data in units of data blocks each having a first length shorter than the fixed length, an output controller configured to sequentially output, to a bus, data blocks each having a second length different from the fixed length, a transfer buffer configured to accumulate data blocks input by the input controller while data blocks are output to the bus by the output controller, and a transfer-buffer input controller configured to eliminate overflow, when the overflow occurs in the transfer buffer, by at least temporarily interrupting a data input operation of the input controller, and to cause the input controller to resume the data input operation with at least one of the packets lost.
The computer system of
The I/O device 10 includes a stream input controller 11, transfer buffer 12, bus master operation controller (data output controller) 13, transfer-buffer input controller 14 and transfer-buffer output controller 15. The host system 2 includes a system memory 21 and controller 22.
The I/O processing device 1 performs I/O processing during packet stream data transfer, and is realized as hardware. The I/O processing device 1 receives, from the I/O device 10, data in the form of a packet stream, and transfers it to the system memory 21 of the host system 2 connected to the device 1 via the bus 3. The packet stream input to the I/O processing device 1 is formed of a series of fixed-length packets each having a packet size corresponding to a fixed length of 192 bytes, and is a byte stream that can be transferred in units of bytes.
The stream input controller 11 sequentially inputs stream data in units of 16 bytes smaller than 192 bytes as the fixed length of each packet, and outputs it to the transfer buffer 12.
The transfer buffer 12 is a memory including a plurality of memory areas, and accumulates, in units of 128 bytes, the data input to the stream input controller 11 while data is output by the bus master operation controller 13 to the bus 3. The transfer buffer 12 is controlled by the transfer-buffer input controller 14 and transfer-buffer output controller 15 so that the buffer functions as a FIFO memory of 128 bytes×4 stages.
The bus master operation controller 13 sequentially inputs data of 128 bytes from the transfer buffer 12, and outputs, to the bus 3, data to be written to the system memory 21 of the host system 2.
The transfer-buffer input controller 14 controls the input operation of the transfer buffer 12 to make the buffer serve as a FIFO memory, and performs control upon occurrence of overflow. The transfer-buffer input controller 14 can recognize the data in the transfer buffer 12, utilizing information for controlling the stream input controller 11 or transfer buffer 12, or information acquired from the transfer-buffer output controller 15.
When overflow occurs in the transfer buffer 12, the transfer-buffer input controller 14 at least temporarily interrupts the data input operation of the stream input controller 11 to thereby eliminate the overflow, and resumes the input of data to the stream input controller 11 in the state in which data loss has occurred in units of packets (i.e., with at least one of the packets lost). In particular, when overflow has occurred after part of the data of a packet is input to the transfer buffer 12, the transfer-buffer input controller 14 temporarily interrupts the data input operation of the stream input controller 11, and discards at least the above-mentioned part of the data in the transfer buffer 12, thereby eliminating the overflow, and causing the stream input controller 11 to resume the data input operation beginning with a leading portion of a subsequent packet. At this time, the transfer-buffer input controller 14 performs the discarding operation in units of 128 bytes (i.e., in units of memory areas in the transfer buffer 12).
The transfer-buffer output controller 15 controls the output operation of the transfer buffer 12 to make the buffer serve as a FIFO memory. For instance, the transfer-buffer output controller 15 controls the transfer buffer 12 in accordance with the information acquired from the transfer-buffer input controller 14, controls the bus master operation controller 13, and supplies the transfer-buffer input controller 14 with information indicating data output.
On the other hand, the host system 2 receives data from the I/O processing device 1 via the bus 3, and processes it as packets each having the aforementioned length. The system memory 21 has a preset memory area (buffer) for processing, in units of 192 bytes, the data transferred from the I/O processing device 1 via the bus 3. The controller 22 processes, in units of 192 bytes, the data accumulated in the system memory 21, by executing the operating system and a preset application.
As described above, data input as a packet stream and output to the bus for writing is formed of packets having a fixed length of 192 bytes.
In
The stream input controller 11 detects the leading portion of a packet at the start of processing, then inputs data in units of 16 bytes, and outputs the data to the transfer buffer 12 having input thereof controlled so that the buffer serves as a FIFO memory.
When data more than 128 bytes is accumulated in the transfer buffer 12, the bus master operation controller 13 performs, in units of 128 bytes, control for inputting data from the transfer buffer 12 having output thereof controlled by the transfer-buffer output controller 15 so that the buffer serves as a FIFO memory, then outputting the data to the bus 3 for writing after the use of the bus 3 is enabled, and transferring the data to the system memory 21. The output processing time of the bus master operation controller 13 for outputting 128-byte data after the use of the bus 3 is enabled is sufficiently earlier than the inputting processing time of the stream input controller 11 for inputting 128-byte data in total (this inputting process is performed in units of 16 bytes).
The time, for which the bus master operation controller 13 is kept standby until the use of the bus 3 is enabled, depends upon the state of the system. When the amount of data input to the transfer buffer 12 by the stream input controller 11 exceeds, temporarily per unit time, the amount of data output by the bus mater operation controller 13, the transfer buffer 12 can accumulate data of up to 512 bytes (128 bytes×4). When data of 512 bytes has been accumulated, and further data input occurs in the stream input controller 11, the transfer-buffer input controller 14 detects the overflow state of the transfer buffer 12, and the stream input controller 11 does not output, to the transfer buffer 12, the data input thereto in response to an instruction from the transfer-buffer input controller 14, and stops further input of data.
The overflow state is eliminated when the bus master operation controller 13 causes the transfer buffer 12 to output data to the bus 3, or when the transfer-buffer input controller 14 discards data contained in the transfer buffer 12, thereby producing in the transfer buffer 12 a free space for permitting new data to be input thereto. When a free space is produced in the transfer buffer 12, the transfer-buffer input controller 14 issues an instruction to the stream input controller 11, and the stream input controller 11, in turn, detects the leading portion of a packet included in input stream data, and then inputs the input data to the transfer buffer 12.
When overflow has occurred upon the input of the leading byte of a 192-byte (fixed-length) packet as shown in state 1 of
Specifically, when, as is shown in state 1 of
When, as is shown in state 3 of
When, as shown in state 2 of
In state 1 shown in
In state 2 shown in
Similarly, in state 3 shown in
As shown in
As shown in
As described above, in the I/O processing device according to the embodiment, which operates with an output transfer size of a fixed length different from that of the packets included in input stream data, defective packets, in which part of the data is lost, are prevented from occurring because of overflow in the transfer buffer. Namely, data in units of packets is secured, and it is not necessary for the host system to consider processing of defective packets when utilizing the output results of the I/O processing device.
In the above-described embodiment, data is buffered as data blocks each having a length shorter than the length of each packet, and is then transferred to the system memory 21. Alternatively, it may be modified such that data is buffered as data blocks each having a length longer than the length of each packet, and is then transferred to the system memory 21.
As described above in detail, in the invention, data transfer in units of packets can be secured even when overflow has occurred in the transfer buffer.
While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2006-152539 | May 2006 | JP | national |