INSTRUMENTATION AMPLIFIER AND SIGNAL DETECTION SYSTEM

Abstract
An instrumentation amplifier can include: an input port configured to receive a sensor signal; a first-stage amplifier configured to amplify the sensor signal to obtain a first intermediate signal; a first high-pass filter circuit, having input terminals coupled to output terminals of the first-stage amplifier, and being configured to eliminate a signal that is in the first intermediate signal and associated with an offset voltage of the first-stage amplifier, in order to obtain a second intermediate signal; a first chopper, having input terminals coupled to output terminals of the first high-pass filter circuit, and being configured to perform chopper modulation and demodulation on the second intermediate signal to obtain a third intermediate signal; and a second-stage amplifier, having input terminals coupled to output terminals of the first chopper, and being configured to amplify the third intermediate signal to generate an output signal.
Description
RELATED APPLICATIONS

This application claims the benefit of Chinese Patent Application No. 202311764825.6, filed on Dec. 20, 2023, which is incorporated herein by reference in its entirety.


FIELD OF THE INVENTION

The present invention generally relates to the field of power electronics, and more particularly to instrumentation amplifiers and signal detection systems.


BACKGROUND

An instrumentation amplifier is a differential voltage amplifier with features such as high common-mode rejection ratio, high input impedance, low noise, low linear error, low offset drift, flexible gain setting, and ease of use, thus making it widely used in data acquisition and sensor signal amplification. It is popular in high-speed signal conditioning, medical instruments, and high-end audio equipment. In terms of sensor signal amplification, both the sensor and the amplifier may have offset voltages. The offset voltage can cause low system accuracy and average common-mode rejection ratio. Therefore, removing the offset voltage is important for the accuracy of the instrumentation amplifier.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a schematic block diagram of a first example instrumentation amplifier.



FIG. 2 is a schematic block diagram of a second example instrumentation amplifier.



FIG. 3 is schematic block diagram of an example signal detection system, in accordance with embodiments of the present invention.



FIG. 4 is a schematic block diagram of an example driving method of the sensor, in accordance with embodiments of the present invention.



FIG. 5 is a waveform diagram of the example sensor, in accordance with embodiments of the present invention.



FIG. 6 is a schematic block diagram of a first example instrumentation amplifier, in accordance with embodiments of the present invention.



FIG. 7 is a schematic block diagram of an example active resistor, in accordance with embodiments of the present invention.



FIG. 8 is an equivalent circuit diagram of the first instrumentation amplifier, in accordance with embodiments of the present invention.



FIG. 9 is a waveform diagram of the equivalent circuit of the first instrumentation amplifier, in accordance with embodiments of the present invention.



FIG. 10 is another equivalent circuit of the first instrumentation amplifier, in accordance with embodiments of the present invention.



FIG. 11 is a waveform diagram of the equivalent circuit of the first instrumentation amplifier of FIG. 10, in accordance with embodiments of the present invention.



FIG. 12 is a schematic block diagram of a second example instrumentation amplifier, in accordance with embodiments of the present invention.



FIG. 13 is a waveform diagram of the equivalent circuit of the second instrumentation amplifier, in accordance with embodiments of the present invention.





DETAILED DESCRIPTION

Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. With the development of economy, batteries have become one of the important clean energy sources in today's society. In general application, each battery pack consists of a plurality of battery modules connected in series, and each battery module consists of a plurality of battery cells or batteries connected in series.


In one approach for removing offset voltage, a ripple reduction loop (RRL) circuit can be used to eliminate ripples caused by the offset voltage. However, the RRL circuit may be relatively complex and require relatively large area and power consumption. Referring now to FIG. 1, shown is a schematic block diagram of a first example instrumentation amplifier. In this example, the instrumentation amplifier can include operational amplifiers A11, A12, A13 and multiple resistors. Here, the multiple resistors include resistors R11-R17. The non-inverting input terminal of operational amplifier A11 may receive input signal V11, and resistor R11 can connect between the inverting input terminal and the output terminal of operational amplifier A11. The non-inverting input terminal of operational amplifier A12 may receive input signal V12, and resistor R11 can connect between the inverting input terminal and the output terminal of operational amplifier A12. Resistors R13 and R14 can connect in series between the output terminal of operational amplifier A11 and a ground terminal. Resistors R16 and R17 can connect in series between the output terminal of operational amplifier A12 and the output terminal of operational amplifier A13. The non-inverting input terminal of operational amplifier A13 can connect to a common node between resistors R13 and R14, and the inverting input terminal of operational amplifier A13 can connect to a common node between resistors R16 and R17. Resistor R12 can connect between resistors R11 and R15.


In this example, when input signals V11 and V12 are common-mode signals, output signal Vout of operational amplifier A13 is 0. The circuit structure shown in FIG. 1 is relatively simple, and the area and power consumption are relatively low. However, the noise performance may not be ideal, and the offset voltage caused by the pre-stage sensor and the amplifier itself may not be removed, thus resulting in low system accuracy and general common-mode rejection ratio.


Referring now to FIG. 2, shown is a schematic block diagram of a second example instrumentation amplifier. In this particular example, the instrumentation amplifier can include operational amplifiers A21, A22 and A23, an integrator, capacitors C21, C22, C23 and C24, and choppers CH21 and CH22. Here, operational amplifier A21 is the first-stage amplifier, operational amplifier A22 is the second-stage amplifier. Operational amplifier A23, the integrator connected between operational amp A23 and chopper CH22, capacitors C23 and C24, and chopper CH22 may form a ripple reduction loop (RRL) circuit. In one example, after input signal Va is amplified by operational amplifier A21, the amplified signal can be modulated and demodulated by chopper CH21, and then the output signal of chopper CH21 may be amplified again by operational amplifier A22. Capacitors C21 and C22 can respectively connect between one input terminal and the output terminal of operational amplifier A22, and may form a Miller compensation amplifier with operational amplifier A22 to improve the gain of the high frequency signal. Since operational amplifier A21 itself has a non-zero offset voltage (equivalent to voltage Voffset in FIG. 2), the output signal of operational amplifier A21 can include both the amplification signal of input signal Va and the offset voltage of operational amplifier A21.


After the offset voltage of operational amplifier A21 is passed through chopper CH21 and operational amplifier A22, a ripple signal at the output terminal of the instrumentation amplifier may be generated by the offset voltage of operational amplifier A21. The RRL circuit can sample the output signal including the ripple signal at the output terminal of the instrumentation amplifier, and then the sampled signal may pass through chopper CH22 to obtain the DC value of the ripple signal. After the DC value of the ripple signal is integrated by the integrator, a compensation voltage may be generated at the input terminals of operational amplifier A23. The compensation voltage can compensate the offset voltage of operational amplifier A21 to reduce the amplitude of the ripple signal introduced by the offset voltage. In addition, the offset voltage of operational amplifier A22 can be suppressed by the gain of operational amplifier A21, so it can effectively be ignored. Therefore, this embodiment can realize the function of removing the offset voltage. However, this approach may only remove the offset voltage of the operational amplifier, not the offset voltage of the front-stage sensor. In addition, the offset voltage can be removed through the RRL circuit, which is relatively complex, and the area and power consumption are relatively large.


Referring now to FIG. 3, shown is schematic block diagram of an example signal detection system, in accordance with embodiments of the present invention. In this particular example, the signal detection system can include sensor 1, switching circuit 2, and instrumentation amplifier 3. Switching circuit 2 may obtain a sensor signal corresponding to the output voltage of sensor 1, and instrumentation amplifier 3 can generate an output signal according to the sensor signal, where the output signal may characterize the output voltage of sensor 1. For example, the sensor signal can be an output voltage, and may be generated by driving sensor 1 by switching circuit 2. In this example, sensor 1 can be various types of sensors (e.g., a temperature sensor, a pressure sensor, a Hall sensor, etc.). Here, a Hall sensor is taken as an example to illustrate, and sensor 1 can include four ports Q1, Q2, Q3, and Q4.


In one embodiment, switching circuit 2 may perform chopper modulation and demodulation on the DC output voltage of the sensor, in order to generate a sensor signal in the form of a square wave signal. For example, switching circuit 2 can include multiple switches and multiple ports, e.g., switching circuit 2 can include eight ports P1-P8. Ports P1-P4 can connect to four ports Q1-Q4 of sensor 1, respectively, port P5 may receive bias current IBIAS, port P8 can connect to ground terminal GND, and ports P6 and P7 can be read-out ports connected to the instrumentation amplifier. When the Hall sensor operates normally, an excitation source may be applied to the two ports in any direction, and the two ports in the other direction can read the output voltage of the sensor. By turning on and off multiple switches in switching circuit 2, the ports coupled to the excitation source and the ports coupled to the readout port in the sensor can be constantly switched between the two driving modes. For example, the four ports of the Hall sensor can continuously switch to different excitation sources or readout ports with operating frequency fs.


Referring now to FIG. 4, shown is a schematic block diagram of an example driving mode of the sensor, in accordance with embodiments of the present invention. Two driving modes of the sensor are shown in this particular example, and the schematic diagram on the left side is the first driving mode. Port Q1 of the sensor can connect to port P5, port Q2 of the sensor can connect to port P7, port Q3 of the sensor can connect to port P6, and port Q4 can connect to port P8. The schematic diagram on the right side is the second driving mode, port Q1 of the sensor can connect to port P7, port Q2 of the sensor can connect to port P5, port Q3 of the sensor can connect to port P8, and port Q4 of the sensor can connect to port P6.


Referring now to FIG. 5, shown is a waveform diagram of the example sensor, in accordance with embodiments of the present invention. In this particular example, the switching clock is a square wave signal with a predetermined frequency. When the switching clock is low, the switching phase is φ0, and thus the sensor is the first driving mode shown on the left side of FIG. 4. The driving angle of the sensor is 0°, and sensor signal VHALL is greater than 0. When the switching clock is high, the switching phase is φ1, and thus the sensor is the second driving mode shown on the right side of FIG. 4. The driving angle of the sensor is 90°, and sensor signal VHALL is less than 0. In addition, due to the existence of offset voltage VS1 of the sensor, the sensor signal may be shifted the amount of offset voltage VS1 upward from 0V as a whole. In other words, in the sensor signal read by the switching circuit, the offset voltage of the sensor itself is a DC signal, the output voltage of the sensor may become a high-frequency signal, and the high-frequency signal can be in the form of a square wave.


The frequency of the square wave may be the same as frequency fs of the switching clock, and also the same as the operating frequency of the system, such that subsequent signal processing can easily separate the offset voltage from the output voltage. In some embodiments, operating frequency fs can be selected to be more than twice the bandwidth of the amplifier. In this particular example, since the output voltage of the sensor and sensor signal VHALL are relatively small, the output voltage of the sensor can be amplified by instrumentation amplifier 3 to a reading range suitable for the instrument and the display.


Referring now to FIG. 6, shown is a schematic block diagram of a first example instrumentation amplifier, in accordance with embodiments of the present invention. In this particular example, the instrumentation amplifier can include an input port, first-stage amplifier A31, high-pass filter circuit 3a, chopper CH31, second-stage amplifier 3b, feedback circuit 3c, and an output port. The input port may receive sensor signal VHALL. Amplifier A31 can amplify sensor signal VHALL to obtain intermediate signal VM1. The input terminals of high-pass filter circuit 3a can connect with the output terminals of first-stage amplifier A31, and high-pass filter circuit 3a and may eliminate the signal included in first intermediate signal VM1 and associated with the offset voltage of first-stage amplifier A31 to obtain intermediate signal VM2.


The input terminals of first chopper CH31 can connect with the output terminals of first high-pass filter circuit 3a, and first chopper CH31 may perform chopper modulation and demodulation on second intermediate signal VM2 to obtain third intermediate signal VM3. The input terminals of second-stage amplifier 3b can connect to the output terminals of first chopper CH31, and second-stage amplifier 3b may amplify third intermediate signal VM3 to generate output signal Vout. Feedback circuit 3c can connect between the output terminals of second-stage amplifier 3b and the input terminals of first-stage amplifier A31, and may feedback output signal Vout to the input terminals of first-stage amplifier A31.


In one embodiment, the instrumentation amplifier can include a control circuit that can generate a control signal to control the operating frequency of the first chopper and/or the second chopper to perform chopper modulation and demodulation. The input port can include positive input terminal di and negative input terminal d2, and may receive sensor signal VHALL. The output port can include positive output terminal e1 and negative output terminal e2, and can generate output signal Vout.


In one embodiment, first-stage amplifier A31 can be a transconductance operational amplifier, including two input terminals and two output terminals. The inverting input terminal and the non-inverting input terminal of first-stage amplifier A31 may respectively connect to negative output terminal e2 and positive output terminal e1 through feedback circuit 3c. Amplifier A31 can receive sensor signal VHALL and feedback signal Vf output by feedback circuit 3c, and may perform amplifying process on sensor signal VHALL and feedback signal Vf, to generate intermediate signal VM1 through the inverting output terminal and the non-inverting output terminal. In some embodiments, stage amplifier A31 may have larger gain G1 (e.g., gain G1 can be set to be greater than 100).


It should be noted that the example of FIG. 6 is illustrated by the inverting input terminal of amplifier A31 being connected to negative output terminal e2 through feedback circuit 3c, and the non-inverting input terminal being connected to positive output terminal e1 through feedback circuit 3c, but other connection arrangements can be supported in certain embodiments. In addition, feedback circuit 3c can include chopper CH32 that can alternately output the input signal forward or reverse at a predetermined operating frequency. If the two terminals on the right side of second chopper CH32 are input terminals, and the two terminals on the left side are output terminals, one of the two input terminals can connect to positive output terminal e1, and the other of the two input terminals can connect to negative output terminal e2. Similarly, one of the two output terminals can connect to the inverting input terminal of first-stage amplifier A31, and the other of the two output terminals can connect to the non-inverting input terminal of first-stage amplifier A31. Therefore, according to the connection mode, output signal Vout may be modulated into a predetermined format by chopper CH32 and fed back to first stage amplifier A31. In this example, first-stage amplifier A31 only shows a single component, but the first-stage amplifier can include multiple components in certain embodiments.


The input terminals of high-pass filter circuit 3a can connect to the output terminals of first-stage amplifier A31, and high-pass filter circuit 3a may eliminate the signal associated with the offset voltage of first-stage amplifier A31 and included in first intermediate signal VM1 to obtain intermediate signal VM2. High-pass filter circuit 3a can include first capacitors and first impedance circuits. The first capacitor can connect between the one output terminal of amplifier A31 and one input terminal of chopper CH31. The first impedance circuit and the first capacitor can connect in series between the output terminal of first stage amplifier A31 and the reference terminal. For example, high-pass filter circuit 3a can include capacitors C31 and C32, and impedance circuits R31 and R32. Capacitor C31 can connect between the non-inverting output terminal of amplifier A31 and the first input terminal of chopper CH31. One terminal of impedance circuit R31 can connect to the common end of capacitor C31 and chopper CH31, and the other terminal of first circuit R31 can connect to the reference terminal. Capacitor C32 can connect between the inverting output terminal of amplifier A31 and the second input terminal of chopper CH31. One terminal of impedance circuit R32 can connect to the common end of capacitor C32 and chopper CH31, and the other terminal of impedance circuit R32 can connect to the reference terminal.


Here, the reference terminal may provide a reference voltage (common mode voltage) VCM, and reference voltage VCM can be set according to the particular application. In one example, the reference terminal is the ground terminal, and reference voltage VCM is 0. In another example, switching circuit 2 and instrumentation amplifier 3 may be integrated in one chip, and reference voltage VCM can be equal to the supply voltage of the chip multiplied by a proportional coefficient. Since the first stage amplifier itself may have an offset voltage, the offset voltage is a DC component, so intermediate signal VM1 may have both DC and AC components. Therefore, the first capacitor and the first impedance circuit can be set as a high-pass filter to connect to the output terminals of amplifier A31. Because the characteristic of the capacitor is isolated from the DC, the offset voltage of the first-stage amplifier may not pass, and the effective AC component can pass, such that high-pass filter circuit 3a can eliminate the signal associated with the offset voltage of first-stage amplifier A31 and included in intermediate signal VM1. In another example, the first impedance circuit is a resistive element. In yet another example, the first impedance circuit is an active resistor to significantly reduce the resistance area and cost.


Referring now to FIG. 7, shown is a schematic block diagram of an example active resistor, in accordance with embodiments of the present invention. The active resistor can include terminal RP, terminal RN, transistor K1, transistor K2, transistor K3, transistor K4, buffer buf1, buffer buf2, current source I1, and current source I2. Transistors K1 and K2 can connect in series between terminals RP and RN, the source of transistor K1 can connect to terminal RP, the source of transistor K2 can connect with terminal RN, and the drain of transistor K1 can connect with the drain of transistor K2. Therefore, transistors K1 and K2 can connect in series between terminals RP and RN to form the main body of the active resistor. Buffer buf1, transistor K3, and current source I1 can connect in series between terminal RP and ground terminal GND, where the input terminal of buffer buf1 can connect to terminal RP, the source of transistor K3 can connect to the output terminal of buffer buf1, current source I1 can connect between the drain of transistor K3 and ground terminal GND, and the control (or gate) terminals of transistors K1 and K3 can connect to current source I1. Buffer buf2, transistor K4, and current source I2 can connect in series between terminal RN and ground terminal GND, where the input terminal of buffer buf2 can connect with terminal RN, the source of transistor K4 can connect with the output terminal of buffer buf2, current source I2 can connect between the drain of transistor K4 and ground terminal GND, and the control (or gate) terminals of transistors K2 and K4 can connect with second current source I2.


For the first structure including terminal RP, transistor K1, transistor K3, buffer buf1, and current source I1, transistor K3 may generate bias voltage VBX under the bias of the first bias current generated by current source I1, such that transistor K1 may operate in the sub-threshold region. For example, buffer buf1 can prevent a resistive load effect of transistor K3 directly on terminal RP. Under the bias of the first bias current, bias voltage VBX can be generated at the high potential terminal of current source I1. Bias voltage VBX can control the operation state of transistors K1 and K3. Thus, by reasonably designing the size of transistors K1 and K3, and the size of the first bias current, transistor K1 can operate in the sub-threshold region under the control of bias voltage VBX. When the transistor operates in the sub-threshold region, a very small current may flow through the transistor, such as may equivalent to a large resistance.


For the second structure including port RN, transistor K2, transistor K4, buffer buf2, and current source I2, transistor K4 may generate bias voltage VBY under the bias of the second bias current generated by current source I2, such that transistor K2 operates in the sub-threshold region. For example, buffer buf2 can prevent the resistive load effect of transistor K4 directly on terminal RN. Under the bias of the second bias current, bias voltage VBY can be generated at the high potential end of current source I2. Bias voltage VBY can control the operation state of transistors K2 and K4. By reasonably designing the size of transistors K2 and K4 and the size of the second bias current, transistor K2 may operate in the sub-threshold region under the control of bias voltage VBY. When the transistor operates in the sub-threshold region, a relatively small current may flow through the transistor, thus being equivalent to a large resistance.


When the active resistor shown in FIG. 7 is applied in the instrumentation amplifier described in FIG. 6, one of terminals RP and RN can be coupled to the common end of the first capacitor (e.g., capacitor C31 or C32) and the first chopper, and the other one of terminals RP and RN can connect to the reference terminal to receive common mode signal VCM. In this way, a larger resistance value with a smaller area can be provided through the active resistor. By adding a buffer, there may be no driving capability requirement for the nodes at both terminals of the first impedance circuit, such that application limits may be reduced and the range expanded.


In particular embodiments, the input terminals of chopper CH31 can connect to the output terminals of high-pass filter circuit 3a, and chopper CH31 may perform chopper modulation and demodulation on intermediate signal VM2 to obtain intermediate signal VM3. Chopper CH31 can be a chopper modem, and may alternately output the input signal forward or reverse at a predetermined operating frequency, thereby performing chopper modulation and demodulation on intermediate signal VM2 to obtain intermediate signal VM3. Therefore, the chopper modulation and demodulation can be performed by chopper CH31, the signal passing through amplifier 3b may be an un-modulated signal, and the bandwidth requirement of second-stage amplifier 3b can be reduced.


In particular embodiments, other connection modes of chopper CH31 can be supported. Chopper CH31 may alternately output the input signal forward or reverse at a predetermined operating frequency. When the two terminals on the left side of chopper CH31 are the input terminals and the two terminals on the right side are the output terminals, one of the two input terminals can connect to the common end of resistor R31 and capacitor C31, and the other of the two input terminals can connect to the common end of resistor R32 and capacitor C32. Similarly, one of the two output terminals can connect to the inverting input terminal of operational amplifier A32, and the other of the two output terminals can connect to the non-inverting input terminal of operational amplifier A32. Therefore, according to the particular connection mode, chopper CH31 may be controlled to modulate and demodulate intermediate signal VM2 into a predetermined format to obtain intermediate signal VM3.


The input terminals of amplifier 3b can connect with the output terminals of chopper CH31, and stage amplifier 3b may amplify intermediate signal VM3 to generate output signal Vout. In certain embodiments, stage amplifier 3b can include operational amplifier A32 and capacitors C33 and C34, as shown in FIG. 6. Operational amplifier A32 can be a transconductance operational amplifier, including two input terminals and two output terminals. Capacitor C33 can connect between the inverting output terminal and the non-inverting output terminal of operational amplifier A32, and capacitor C34 can connect between the non-inverting input and inverting output terminals of operational amplifier A32. Thus, operational amplifier A32 and capacitors C33 and C34 may form a Miller compensation amplifier stage. The circuit bandwidth of the Miller compensation amplifier stage can be relatively narrow, which may provide a higher gain for the un-modulated signal and a smaller gain for the offset voltage modulated to the predetermined frequency, thereby further reducing the amplitude of the offset voltage in output signal Vout.


Feedback circuit 3c can connect between the output terminals of amplifier 3b and the input terminals of amplifier A31, and may feedback output signal Vout to amplifier A31. In certain embodiments, feedback circuit 3c can include chopper CH32, a third capacitor, and a third resistor. The input terminals of chopper CH32 can connect to the output terminals of amplifier 3b, and chopper CH32 can perform chopper modulation and demodulation on output signal Vout to obtain intermediate signal VM4. Chopper CH32 can be a chopper modem, and may alternately output the input signal forward or reverse at a predetermined operating frequency, and to chopper output signal Vout to obtain intermediate signal VM4. The third resistor can connect in parallel with the third capacitor to form the first circuit. The first circuit can connect between the output terminal of chopper CH32 and the input terminal of amplifier A31, and may feedback intermediate signal VM4 to amplifier A31. Here, the number of the third capacitor and the third resistor is 2, respectively, such as third capacitors C35 and C36, and third resistors R33 and R34 as shown in FIG. 7.


In some embodiments, the instrumentation amplifier also can include a control circuit that may generate a control signal to control the operating frequency of chopper CH31 and/or chopper CH32 for chopper modulation and demodulation. The frequency of the control signal can be the same as the frequency of the switching clock of the switching circuit.


The instrumentation amplifier of particular embodiments may receive the sensor signal through the input port. The first-stage amplifier can amplify the sensor signal to obtain the first intermediate signal. The first high-pass filter circuit may eliminate the signal associated with the offset voltage of the first-stage amplifier and included in the first intermediate signal to obtain the second intermediate signal. The first chopper can perform chopper modulation and demodulation on the second intermediate signal to obtain the third intermediate signal. The second-stage amplifier may amplify the third intermediate signal to generate an output signal. The feedback circuit can feed the output signal back to the first-stage amplifier. Therefore, the offset voltage of the first stage amplifier can be eliminated by the first high-pass filter circuit, which may reduce the complexity of the circuit, the circuit area, and power consumption.


Referring now to FIG. 8, shown is an equivalent circuit diagram of the first example instrumentation amplifier, in accordance with embodiments of the present invention. In this particular example, the first stage amplifier with the offset voltage can be equivalent to voltage source VOS1 and amplifier A31 without offset voltage connected in series. The output voltage of voltage source VOS1 can be equal to the offset voltage of the first stage amplifier. Without considering the offset voltage of the second stage amplifier, the connection mode of the other parts can be consistent with the example circuit of FIG. 6.


Referring now to FIG. 9, shown is a waveform diagram of an example equivalent circuit of the first instrumentation amplifier of FIG. 8, in accordance with embodiments of the present invention. The waveforms of sensor signal VHALL, superimposed signal VADD, intermediate signal VM1, intermediate signal VM2, intermediate signal VM3, and output signal Vout are shown in the example of FIG. 9. Superimposed signal VADD may be the signal provided to the first-stage amplifier after sensor signal VHALL and feedback signal Vf are superposed. Here, without considering the offset voltage of the sensor itself, sensor signal VHALL can be a square wave signal, and output signal Vout is a DC signal. After being modulated and demodulated by chopper CH32, feedback signal Vf in feedback circuit 3c may be a square wave signal.


After sensor signal VHALL and feedback signal Vf are superposed, superimposed signal VADD (e.g., voltage between nodes d3 and d4) may also be a square wave signal. Superimposed signal VADD and offset voltage VOS1 can be input to amplifier A31, which may output intermediate signal VM1 after the amplification for superimposed signal VADD and offset voltage VOS1. In addition, the first intermediate signal may have both AC and DC components, whereby DC component is G1*VOS1, and G1 is the gain of the first stage amplifier. Intermediate signal VM1 can be filtered by high-pass filter circuit 3a to obtain intermediate signal VM2. Chopper CH31 may perform chopper modulation and demodulation on intermediate signal VM2 to obtain intermediate signal VM3 (e.g., a DC signal). Intermediate signal VM3 can be amplified by second stage amplifier 3b to obtain output signal Vout. Thus, the signal associated with the offset voltage of first-stage amplifier A31 and included in intermediate signal VM1 can be eliminated by the first high-pass filter circuit.


Referring now to FIG. 10, shown is another equivalent circuit of the first instrumentation amplifier, in accordance with embodiments of the present invention. In this particular example, the operational amplifier with offset voltage may be equivalent to the series connection of voltage source VOS2 and operational amplifier A32 without offset voltage. The output voltage of voltage source VOS2 can be equal to the offset voltage of the operational amplifier. Without considering the offset voltage of the first stage amplifier, the connection mode of the other parts may be consistent with the example circuit of FIG. 6.


Referring now to FIG. 11, shown is a waveform diagram of another equivalent circuit of the first instrumentation amplifier of FIG. 10, in accordance with embodiments of the present invention. The waveforms of sensor signal VHALL, superimposed signal VADD, intermediate signal VM1, intermediate signal VM2, intermediate signal VM3, and output signal Vout are shown in the example of FIG. 11. Here, without considering the offset voltage of the sensor itself, sensor signal VHALL is a square wave signal, output signal Vout can be a DC signal, and after being modulated and demodulated by chopper CH32, feedback signal Vf in feedback circuit 3c can be a square wave signal. Due to the existence of voltage source VOS2, the loop may adjust its operating point, and generate a compensation signal at the input and output terminals of the first-stage amplifier. The compensation signal at the output terminals of the first-stage amplifier can be close to the absolute value of voltage source VOS2 (e.g., almost equal thereto), and the direction of the compensation signal can be opposite to that of voltage source VOS2 (e.g., one being positive and the other negative). Correspondingly, the compensation signal at the input terminals of the first-stage amplifier can be equal to a ratio of the compensation signal and the gain of the first stage amplifier.


Therefore, superimposed signal VADD may be the signal generated by the superposition of sensor signal VHALL, feedback signal Vf and the compensation signal at the input terminals of the first-stage amplifier, and superimposed signal VADD (e.g., the voltage between nodes d3 and d4) may also be a square wave signal. After superimposed signal VADD is input to first-stage amplifier A31, first-stage amplifier A31 may amplify the superimposed signal and output intermediate signal VM1. At this time, intermediate signal VM1 can be obtained as follows: VM1=G1*(VHALL+Vf)+Vcom, where Vcom is the compensation signal. Intermediate signal VM1 can pass through the first high-pass filter circuit to obtain intermediate signal VM2, and intermediate signal VM2 may pass through the first chopper to obtain intermediate signal VM3. As shown in the waveform corresponding to intermediate signal VM3, the waveform with the solid line is intermediate signal VM3, and the waveform with the dotted line is the signal corresponding to the compensation signal in intermediate signal VM3 at the output terminal of the first stage amplifier; that is, compensation signal Vcom at the output terminal of the first stage amplifier. The absolute value of compensation signal Vcom can be close to that of second voltage source VOS2 (e.g., almost equal thereto), and the direction of compensation signal Vcom may be opposite to that of voltage source VOS2. Most of the voltage of voltage source VOS2 can be canceled, and the un-canceled part of the voltage of voltage source VOS2 may be inversely proportional to gain G1 of the first stage amplifier. Because gain G1 is large, the un-canceled part of the voltage of voltage source VOS2 can effectively be ignored. As such, the offset voltage of the second stage amplifier can be removed.


The instrumentation amplifier of particular embodiments may receive the sensor signal through the input port. The first-stage amplifier can amplify the sensor signal to obtain the first intermediate signal. The first high-pass filter circuit may eliminate the signal associated with the offset voltage of the first-stage amplifier and included in the first intermediate signal to obtain the second intermediate signal. The first chopper can perform chopper modulation and demodulation on the second intermediate signal to obtain the third intermediate signal. The second-stage amplifier may amplify the third intermediate signal to generate the output signal. The feedback circuit can the output signal back to the first-stage amplifier. Therefore, the offset voltage of the first stage amplifier can be eliminated by the first high-pass filter circuit, which may reduce the complexity of the circuit, the circuit area, and power consumption.


In addition, most of the offset voltage of the second stage amplifiers can be eliminated by using the loop formed of feedback circuit 3c and the first and second stage amplifiers. In the first example shown in FIGS. 6-11, the offset voltage of the sensor may not be considered, but as shown in FIG. 5, the sensor itself may have a certain offset voltage. Therefore, in order to further improve the accuracy of the instrumentation amplifier, particular embodiments may also provide another instrumentation amplifier.


Referring now to FIG. 12, shown is a circuit diagram of a second example instrumentation amplifier, in accordance with embodiments of the present invention. In this particular example, the instrumentation amplifier can also include high-pass filter circuit 3d. High-pass filter circuit 3d can connect between the input port and amplifier A31, and may eliminate the signal associated with the offset voltage of the sensor and included in the sensor signal. High-pass filter circuit 3d can include the second capacitor and the second impedance circuit. The second capacitor can connect between one terminal of the input port and one input terminal of amplifier A31, and the second impedance circuit and the second capacitor can connect in series between one terminal of the input port and the reference terminal. In particular embodiments, high-pass filter circuit 3d can include capacitors C37 and C38, and impedance circuits R35 and R36. Capacitor C37 can connect between positive input terminal d1 and the inverting input terminal of amplifier A31, one terminal of impedance circuit R35 can connect to the common end of capacitor C37 and amplifier A31, and the other terminal of impedance circuit R35 can connect to the reference terminal. Capacitor C38 can connect between negative input terminal d2 and the non-inverting input terminal of first-stage amplifier A31. One terminal of impedance circuit R36 can connect to the common end of capacitor C38 and amplifier A31, and the other terminal of impedance circuit R36 can connect to the reference terminal.


Here, the reference terminal may provide a reference voltage (e.g., common mode voltage VCM), and the reference voltage can be set according to particular applications. In another example, the reference terminal can be the ground terminal, and the reference voltage may be 0. In another embodiment, switching circuit 2 and instrumentation amplifier 3 may be integrated in one chip, and the reference voltage can be equal to the supply voltage of the chip multiplied by a proportional coefficient. Since the first stage amplifier itself has an offset voltage, the offset voltage can be a DC component, so intermediate signal VM1 may have both DC and AC components. Therefore, the second capacitor and the second impedance circuit can be set as a high-pass filter to connect to the input terminals of first-stage amplifier A31. Because the characteristic of the capacitor is isolated from the DC component, the offset voltage of the first-stage amplifier may not pass, and the effective AC component can pass, such that the signal associated with the offset voltage of first-stage amplifier A31 and included in intermediate signal VM1 can be eliminated.


In another example, the second impedance circuit can be a resistive element. In yet another example, the second impedance circuit can be an active resistor (e.g., implemented by the circuit shown in FIG. 7). The instrumentation amplifier shown in FIG. 12 can simultaneously remove the offset voltage of the sensor, the offset voltage of the first amplifier, and the offset voltage of the second amplifier.


Referring now to FIG. 13, shown is a waveform diagram of the equivalent circuit of the second instrumentation amplifier, in accordance with embodiments of the present invention. The waveforms of sensor signal VHALL, filtered sensor signal VM5, superimposed signal VADD, intermediate signal VM1, intermediate signal VM2, intermediate signal VM3, and output signal Vout are shown. Due to offset voltage VS1 of the sensor, the average value of sensor signal VHALL can be moved up offset voltage VS1 from 0V. That is, in the sensor signal read by the switching circuit, the offset voltage of sensor itself can be a DC signal, the output voltage of the sensor may be a high frequency signal, and the high frequency signal can be square wave. The sensor signal may be filtered by high-pass filter circuit 3d to obtain filtered sensor signal VM5. Superimposed signal VADD may be provided to the first stage amplifier after filtered sensor signal VM5 and feedback signal Vf are superposed. Output signal Vout can be a DC signal. Feedback signal Vf after being chopper modulated and demodulated by chopper CH32 in feedback circuit 3c can be a square wave signal. Filtered sensor signal VM5 and feedback signal Vf may be superimposed to obtain superimposed signal VADD.


After superimposed signal VADD and offset voltage VOS1 are input to first-stage amplifier A31, first-stage amplifier A31 can output intermediate signal VM1 by amplifying superimposed signal VADD and offset voltage VOS1. Intermediate signal VM1 may have both AC and DC components, and the DC component is G1*VOS1, where G1 is the gain of the first-stage amplifier. Intermediate signal VM1 can be filtered by high-pass filter circuit 3a to obtain intermediate signal VM2. Chopper CH31 may perform chopper modulation and demodulation on intermediate signal VM2 to obtain intermediate signal VM3, which can be a DC signal. Intermediate signal VM3 may be further amplified by stage amplifier 3b to obtain output signal Vout. Thus, the signal included in the first intermediate signal and associated with the offset voltage of the first stage amplifier can be eliminated by the first high-pass filter circuit, and the part of the sensor signal associated with the offset voltage of the sensor can be eliminated by the second high-pass filter. For eliminating the offset voltage of the second-stage amplifier, the specific principle can be similar to that of FIGS. 10 and 11.


In particular embodiments may receive the sensor signal through the input port, the first-stage amplifier can amplify the sensor signal to obtain the first intermediate signal, and the first high-pass filter circuit may eliminate a part that is related to the offset voltage of the first-stage amplifier included in the first intermediate signal to obtain the second intermediate signal. Also, the first chopper may perform chopping modulation and demodulation on the second intermediate signal to obtain the third intermediate signal, the second stage amplifier can amplify the third intermediate signal to generate the output signal, and the feedback circuit may feed the output signal back to the first stage amplifier. Therefore, the offset voltage of the first-stage amplifier can be eliminated through the first high-pass filter circuit, thereby reducing the complexity of the circuit, and reducing the circuit area and power consumption. Further, the offset voltage of the sensor can be eliminated through the second high-pass filter circuit.


The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to particular use(s) contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims
  • 1. An instrumentation amplifier, comprising: a) an input port configured to receive a sensor signal, wherein the sensor signal is obtained by chopper modulating and demodulating an output voltage of a sensor;b) a first-stage amplifier configured to amplify the sensor signal to obtain a first intermediate signal;c) a first high-pass filter circuit, having input terminals coupled to output terminals of the first-stage amplifier, and being configured to eliminate a signal that is in the first intermediate signal and associated with an offset voltage of the first-stage amplifier, in order to obtain a second intermediate signal;d) a first chopper, having input terminals coupled to output terminals of the first high-pass filter circuit, and being configured to perform chopper modulation and demodulation on the second intermediate signal to obtain a third intermediate signal;e) a second-stage amplifier, having input terminals coupled to output terminals of the first chopper, and being configured to amplify the third intermediate signal to generate an output signal; andf) a feedback circuit coupled between output terminals of the second-stage amplifier and the input terminals of the first-stage amplifier, and being configured to feed back the output signal to the first-stage amplifier.
  • 2. The instrumentation amplifier of claim 1, wherein the first high-pass filter circuit comprises two first series structures, the first series structure comprising a first capacitor and a first impedance circuit coupled in series, wherein a first of the two first series structures is coupled between a first of the two output terminals of the first-stage amplifier and a reference terminal, and a second of the two first series structures is coupled between a second of the two output terminals of the first-stage amplifier and the reference terminal, wherein a compensation voltage is provided at the reference terminal.
  • 3. The instrumentation amplifier of claim 2, wherein the first capacitor is coupled between a corresponding output terminal of the first-stage amplifier and the first chopper, and the first impedance circuit is coupled between a common node of the corresponding first capacitor and the first chopper and the reference terminal.
  • 4. The instrumentation amplifier of claim 2, further comprising a second high-pass filter circuit coupled between the input port and the first stage amplifier, and being configured to eliminate a portion of the sensor signal that is associated with an offset voltage of the sensor.
  • 5. The instrumentation amplifier of claim 4, wherein the second high-pass filter circuit comprises two second series structures, and the second series structure comprises a second capacitor and a second impedance circuit coupled in series, wherein a first of the two second series structures is coupled between a first of the two terminals of the input port and the reference terminal, and a second of the two second series structures is coupled between a second of the two terminals of the input port and the reference terminal.
  • 6. The instrumentation amplifier of claim 5, wherein the second capacitor is coupled between a corresponding terminal of the input port and the first-stage amplifier, and the second impedance circuit is coupled between a common terminal of the corresponding first capacitor and the first-stage amplifier and the reference terminal.
  • 7. The instrumentation amplifier of claim 5, wherein at least one of the first impedance circuit and the second impedance circuit is an active resistor.
  • 8. The instrumentation amplifier of claim 7, wherein the active resistor comprises: a) a first port;b) a second port;c) a first transistor;d) a second transistor coupled in series with the first transistor between the first port and the second port; ande) wherein the voltages at the control terminals of the first transistor and the second transistor are controlled such that the first transistor and the second transistor both operate in a sub-threshold region.
  • 9. The instrumentation amplifier of claim 8, wherein when the first impedance circuit is configured as the active resistor, a first of the first port and the second port is coupled to a common node of the first capacitor and the first impedance circuit, and a second of the first port and the second port is coupled to the reference terminal.
  • 10. The instrumentation amplifier of claim 8, wherein when the second impedance circuit is configured as the active resistor, a first of the first port and the second port is coupled to a common node of the second capacitor and the second impedance circuit, and a second of the first port and the second port is coupled to the reference terminal.
  • 11. The instrumentation amplifier of claim 8, wherein the active resistor further comprises: a) a first buffer;b) a third transistor;c) a first current source, coupled in series with the first buffer and the third transistor between the first port and a ground terminal;d) a second buffer;e) a fourth transistor;f) a second current source coupled in series with the second buffer and the fourth transistor between the second port and the ground terminal; andg) wherein control terminals of the first transistor and the third transistor are coupled to the first current source, and control terminals of the second transistor and the fourth transistor are coupled to the second current source;h) wherein the third transistor is configured to generate a first bias voltage under the bias of a first bias current generated by the first current source, such that the first transistor operates in the sub-threshold region; andi) wherein the fourth transistor is configured to generate a second bias voltage under the bias of a second bias current generated by the second current source, such that the second transistor operates in the sub-threshold region.
  • 12. The instrumentation amplifier of claim 1, wherein the feedback circuit comprises: a) a second chopper coupled to the output terminals of the second-stage amplifier, and being configured to perform chopper modulation and demodulation on the output signal to obtain a fourth intermediate signal;b) two third capacitors;c) two third resistors; andd) wherein the third capacitor and the third resistor are coupled in parallel with between the output terminal of the second chopper and the input terminal of the first stage amplifier, and are configured to feed back the fourth intermediate signal to the first-stage amplifier.
  • 13. The instrumentation amplifier of claim 1, wherein the second stage amplifier comprises: a) an operational amplifier;b) two fourth capacitors; andc) wherein the two fourth capacitor are coupled between one output terminal and one input terminal of the operational amplifier.
  • 14. The instrumentation amplifier of claim 12, further comprising a control circuit configured to generate a control signal to control an operating frequency of at least one of the first chopper and the second chopper to perform chopper modulation and demodulation.
  • 15. A signal detection system, comprising the instrumentation amplifier of claim 1, and further comprising: a) a sensor configured to generate an output voltage; andb) a switching circuit configured to receive the output voltage to obtain a sensor signal corresponding to the output voltage of the sensor.
Priority Claims (1)
Number Date Country Kind
202311764825.6 Dec 2023 CN national